* Continuing sky R5900 / COP2 work. Added extra sanitize tags to hide
128-bit MIPS part. [ChangeLog] Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com> * interp.c (decode_coproc): Continuing COP2 work. (cop_[ls]q): Hide 128-bit COP2 more. * sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more. [ChangeLog.sky] Mon Mar 30 18:44:15 1998 Frank Ch. Eigler <fche@cygnus.com> * sky-libvpe.c: Code too wide - ran indent on SCEI code. * sky-vu.h (vu0_busy*, vu0_macro*): New entry points for COP2 interface. * sky-vu.c (vu0_busy*, vu0_macro*): Stub functions for above.
This commit is contained in:
Frank Ch. Eigler
parent
0d3e84dd92
commit
6ed00b0607
3 changed files with 114 additions and 62 deletions
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@ -1,3 +1,12 @@
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start-sanitize-sky
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Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
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* interp.c (decode_coproc): Continuing COP2 work.
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(cop_[ls]q): Hide 128-bit COP2 more.
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* sim-main.h (COP_[LS]Q): Hide 128-bit COP2 more.
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end-sanitize-sky
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Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
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* configure.in (mipstx39*-*-*): Use gencode simulator rather
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@ -30,13 +39,12 @@ start-sanitize-sky
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* sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
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status register.
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end-sanitize-sky
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* interp.c (cop_lq, cop_sq): New functions for future 128-bit
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access to coprocessor registers.
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* sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
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end-sanitize-sky
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Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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@ -3248,6 +3248,8 @@ cop_ld (SIM_DESC sd,
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}
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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void
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cop_lq (SIM_DESC sd,
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sim_cpu *cpu,
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@ -3258,11 +3260,9 @@ cop_lq (SIM_DESC sd,
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{
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switch (coproc_num)
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{
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/* start-sanitize-sky */
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case 2:
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/* XXX COP2 */
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break;
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/* end-sanitize-sky */
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default:
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sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
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@ -3272,6 +3272,8 @@ cop_lq (SIM_DESC sd,
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return;
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}
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#endif /* TARGET_SKY */
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/* end-sanitize-sky */
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unsigned int
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@ -3334,6 +3336,8 @@ cop_sd (SIM_DESC sd,
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}
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/* start-sanitize-sky */
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#ifdef TARGET_SKY
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unsigned128
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cop_sq (SIM_DESC sd,
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sim_cpu *cpu,
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@ -3341,14 +3345,12 @@ cop_sq (SIM_DESC sd,
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int coproc_num,
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int coproc_reg)
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{
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unsigned128 value = {0, 0};
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unsigned128 value = U16_8(0, 0);
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switch (coproc_num)
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{
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/* start-sanitize-sky */
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case 2:
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/* XXX COP2 */
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break;
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/* end-sanitize-sky */
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default:
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sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
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@ -3358,6 +3360,8 @@ cop_sq (SIM_DESC sd,
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return(value);
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}
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#endif /* TARGET_SKY */
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/* end-sanitize-sky */
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void
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@ -3513,9 +3517,9 @@ decode_coproc (SIM_DESC sd,
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int i_15_11 = (instruction >> 11) & 0x1f;
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int i_15_0 = instruction & 0xffff;
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int i_10_1 = (instruction >> 1) & 0x3ff;
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int i_5_0 = instruction & 0x03f;
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int interlock = instruction & 0x01;
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unsigned_4 vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT);
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int vpe_busy = (vpe_status & 0x00000001);
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int co = (instruction >> 25) & 0x01;
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/* setup for semantic.c-like actions below */
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typedef unsigned_4 instruction_word;
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int CIA = cia;
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@ -3535,91 +3539,128 @@ decode_coproc (SIM_DESC sd,
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if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(! vpe_busy) DELAY_SLOT(cia + 4 + offset);
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if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
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}
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else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(! vpe_busy) DELAY_SLOT(cia + 4 + offset);
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if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
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else NULLIFY_NEXT_INSTRUCTION();
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}
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else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(vpe_busy) DELAY_SLOT(cia + 4 + offset);
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if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
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}
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else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
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{
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address_word offset = EXTEND16(i_15_0) << 2;
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if(vpe_busy) DELAY_SLOT(cia + 4 + offset);
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if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
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else NULLIFY_NEXT_INSTRUCTION();
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}
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else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
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(i_25_21 == 0x06 && i_10_1 == 0x000)) /* CTC2 */
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(i_25_21 == 0x01)) /* QMFC2 */
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{
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int rt = i_20_16;
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int id = i_15_11;
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int to_vu = (i_25_21 == 0x06); /* transfer direction */
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address_word vu_cr_addr; /* VU control register address */
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unsigned_4 data;
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if(interlock)
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while(vpe_busy)
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{
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vu0_issue(sd); /* advance one clock cycle */
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vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT);
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vpe_busy = vpe_status & 0x00000001;
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}
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/* interlock checking */
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if(vu0_busy_in_macro_mode()) /* busy in macro mode */
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{
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/* interlock bit invalid here */
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if(interlock)
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; /* XXX: warning */
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/* always check data hazard */
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while(vu0_macro_hazard_check(id))
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vu0_issue(sd);
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}
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else if(vu0_busy_in_micro_mode() && interlock)
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{
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while(vu0_busy_in_micro_mode())
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vu0_issue(sd);
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}
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/* compute VU register address */
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vu_cr_addr = VU0_MST + (id * 16);
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if(i_25_21 == 0x01) /* QMFC2 */
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vu_cr_addr = VU0_VF00 + (id * 16);
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else /* CFC2 */
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vu_cr_addr = VU0_MST + (id * 16);
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/* read or write word */
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if(to_vu) /* CTC2 */
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{
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unsigned_4 data = GPR[rt];
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sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
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}
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else /* CFC2 */
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{
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unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
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GPR[rt] = EXTEND64(data);
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}
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data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
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GPR[rt] = EXTEND64(data);
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}
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else if((i_25_21 == 0x01) || /* QMFC2 */
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(i_25_21 == 0x05)) /* QMTC2 */
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else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
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(i_25_21 == 0x05)) /* QMTC2 */
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{
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int rt = i_20_16;
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int id = i_15_11;
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int to_vu = (i_25_21 == 0x05); /* transfer direction */
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address_word vu_cr_addr; /* VU control register address */
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unsigned_4 data;
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if(interlock)
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while(vpe_busy)
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{
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vu0_issue(sd); /* advance one clock cycle */
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vpe_status = sim_core_read_aligned_4 (cpu, cia, read_map, VPE0_STAT);
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vpe_busy = vpe_status & 0x00000001;
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}
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/* interlock checking */
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if(vu0_busy_in_macro_mode()) /* busy in macro mode */
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{
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/* interlock bit invalid here */
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if(interlock)
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; /* XXX: warning */
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/* always check data hazard */
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while(vu0_macro_hazard_check(id))
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vu0_issue(sd);
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}
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else if(vu0_busy_in_micro_mode())
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{
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if(interlock)
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{
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while(! vu0_micro_interlock_released())
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vu0_issue(sd);
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}
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}
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/* compute VU register address */
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vu_cr_addr = VU0_VF00 + (id * 16);
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if(i_25_21 == 0x05) /* QMTC2 */
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vu_cr_addr = VU0_VF00 + (id * 16);
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else /* CTC2 */
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vu_cr_addr = VU0_MST + (id * 16);
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/* read or write word */
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if(to_vu) /* CTC2 */
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{
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unsigned_4 data = GPR[rt];
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sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
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}
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else /* CFC2 */
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{
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unsigned_4 data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
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GPR[rt] = EXTEND64(data);
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}
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data = GPR[rt];
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sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
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}
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/* other COP2 instructions */
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else if( 0 /* XXX: ... upper ... */)
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{
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unsigned_4 vu_upper, vu_lower;
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vu_upper =
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0x00000000 | /* bits 31 .. 25 */
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instruction & 0x01ffffff; /* bits 24 .. 0 */
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vu_lower = 0x8000033c; /* NOP */
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while(vu0_busy_in_micro_mode())
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vu0_issue(sd);
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vu0_macro_issue(vu_upper, vu_lower);
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}
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else if( 0 /* XXX: ... lower ... */)
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{
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unsigned_4 vu_upper, vu_lower;
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vu_upper = 0x000002ff; /* NOP */
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vu_lower =
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0x10000000 | /* bits 31 .. 25 */
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instruction & 0x01ffffff; /* bits 24 .. 0 */
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while(vu0_busy_in_micro_mode())
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vu0_issue(sd);
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vu0_macro_issue(vu_upper, vu_lower);
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}
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/* XXX */
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/* ... other COP2 instructions ... */
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else
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{
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SignalException(ReservedInstruction,instruction);
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SignalException(ReservedInstruction, instruction);
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/* NOTREACHED */
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}
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@ -763,23 +763,26 @@ void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exceptio
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void cop_lw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
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void cop_ld PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
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void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned128 memword));
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unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
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uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
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unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
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#define COP_LW(coproc_num,coproc_reg,memword) \
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cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
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#define COP_LD(coproc_num,coproc_reg,memword) \
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cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
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#define COP_LQ(coproc_num,coproc_reg,memword) \
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cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
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#define COP_SW(coproc_num,coproc_reg) \
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cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
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#define COP_SD(coproc_num,coproc_reg) \
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cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
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/* start-sanitize-sky */
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void cop_lq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned128 memword));
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unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
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#define COP_LQ(coproc_num,coproc_reg,memword) \
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cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
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#define COP_SQ(coproc_num,coproc_reg) \
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cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
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/* end-sanitize-sky */
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void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
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#define DecodeCoproc(instruction) \
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