FreeChainXenon/binutils-gdb
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

* simops.c: Fix more bugs in "add imm,an" and

Browse source 
"add imm,dn".
Fixes a half-dozen (of several hundred :( c-torture failures.
This commit is contained in:
Jeff Law 1996-12-01 23:10:04 +00:00
parent c5c4495202
commit 6db7fc49d2
2 changed files with 13 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

5
sim/mn10300/ChangeLog
View file

@ -1,3 +1,8 @@
Sun Dec 1 16:05:42 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix more bugs in "add imm,an" and
"add imm,dn".
Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com) Wed Nov 27 09:20:42 1996 Jeffrey A Law (law@cygnus.com)
* simops.c: Fix bugs in "movm" and "add imm,an". * simops.c: Fix bugs in "movm" and "add imm,an".

16
sim/mn10300/simops.c
View file

@ -1034,10 +1034,10 @@ void OP_FAC00000 ()
int z, c, n, v; int z, c, n, v;
unsigned long reg1, imm, value; unsigned long reg1, imm, value;
reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)]; reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
imm = SEXT16 (insn & 0xffff); imm = SEXT16 (insn & 0xffff);
value = reg1 + imm; value = reg1 + imm;
State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value; State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
z = (value == 0); z = (value == 0);
n = (value & 0x80000000); n = (value & 0x80000000);
@ -1056,10 +1056,10 @@ void OP_FCC00000 ()
int z, c, n, v; int z, c, n, v;
unsigned long reg1, imm, value; unsigned long reg1, imm, value;
reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)]; reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
imm = ((insn & 0xffff) << 16) | extension; imm = ((insn & 0xffff) << 16) | extension;
value = reg1 + imm; value = reg1 + imm;
State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value; State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
z = (value == 0); z = (value == 0);
n = (value & 0x80000000); n = (value & 0x80000000);
@ -1100,10 +1100,10 @@ void OP_FAD00000 ()
int z, c, n, v; int z, c, n, v;
unsigned long reg1, imm, value; unsigned long reg1, imm, value;
reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)]; reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
imm = SEXT16 (insn & 0xffff); imm = SEXT16 (insn & 0xffff);
value = reg1 + imm; value = reg1 + imm;
State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value; State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
z = (value == 0); z = (value == 0);
n = (value & 0x80000000); n = (value & 0x80000000);
@ -1122,10 +1122,10 @@ void OP_FCD00000 ()
int z, c, n, v; int z, c, n, v;
unsigned long reg1, imm, value; unsigned long reg1, imm, value;
reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)]; reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
imm = ((insn & 0xffff) << 16) | extension; imm = ((insn & 0xffff) << 16) | extension;
value = reg1 + imm; value = reg1 + imm;
State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value; State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
z = (value == 0); z = (value == 0);
n = (value & 0x80000000); n = (value & 0x80000000);