Only allow 32-bit/64-bit registers for bndcl/bndcu/bndcn
gas/testsuite/ * gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX. * gas/i386/x86-64-mpx.s: Likwise. * gas/i386/mpx.d: Updated. * gas/i386/x86-64-mpx.d: Likewise. opcodes/ * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the default case. (OP_E_register): Move v_bnd_mode alongside m_mode. * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants. Drop Reg16 and Disp16. Add NoRex64. (bndmk, bndmov, bndldx, bndstx): Drop Disp16. * i386-tbl.h: Re-generate.
This commit is contained in:
H.J. Lu
parent
44dcb735e4
commit
6c75cc62a3
9 changed files with 120 additions and 78 deletions
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@ -1,3 +1,11 @@
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2013-10-12 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/mpx.s: Remove bndcl/bndcu/bndcn tests with AX.
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* gas/i386/x86-64-mpx.s: Likwise.
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* gas/i386/mpx.d: Updated.
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* gas/i386/x86-64-mpx.d: Likewise.
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2013-10-10 Sean Keys <skeys@ipdatasys.com>
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* gas/xgate/all_insns.d: Add com macro insn test.
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@ -6,7 +6,7 @@
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Disassembly of section .text:
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0+ <foo-0x2c1>:
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0+ <start>:
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[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1b 0d 99 03 00 00 bndmk 0x399,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1b 4a 03 bndmk 0x3\(%edx\),%bnd1
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@ -29,7 +29,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
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[ ]*[a-f0-9]+: f3 0f 1a 09 bndcl \(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 4a 03 bndcl 0x3\(%edx\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
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@ -37,7 +36,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 1a 4c 01 03 bndcl 0x3\(%ecx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 09 bndcu \(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 4a 03 bndcu 0x3\(%edx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
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@ -45,7 +43,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f2 0f 1a 4c 01 03 bndcu 0x3\(%ecx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 09 bndcn \(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 4a 03 bndcn 0x3\(%edx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
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@ -65,10 +62,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 0f 1a 93 34 12 00 00 bndldx 0x1234\(%ebx\),%bnd2
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[ ]*[a-f0-9]+: 0f 1a 53 03 bndldx 0x3\(%ebx\),%bnd2
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[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
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[ ]*[a-f0-9]+: f2 e8 6f 01 00 00 bnd call 2c1 <foo>
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[ ]*[a-f0-9]+: f2 e8 63 01 00 00 bnd call 2a9 <foo>
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[ ]*[a-f0-9]+: f2 ff 10 bnd call \*\(%eax\)
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[ ]*[a-f0-9]+: f2 0f 84 65 01 00 00 bnd je 2c1 <foo>
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[ ]*[a-f0-9]+: f2 e9 5f 01 00 00 bnd jmp 2c1 <foo>
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[ ]*[a-f0-9]+: f2 0f 84 59 01 00 00 bnd je 2a9 <foo>
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[ ]*[a-f0-9]+: f2 e9 53 01 00 00 bnd jmp 2a9 <foo>
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[ ]*[a-f0-9]+: f2 ff 21 bnd jmp \*\(%ecx\)
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[ ]*[a-f0-9]+: f2 c3 bnd ret
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[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%eax\),%bnd1
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@ -93,7 +90,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 1a c8 bndmov %bnd0,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%eax\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 0d 99 03 00 00 bndcl 0x399,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 49 03 bndcl 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
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@ -101,7 +97,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 1a 4c 02 03 bndcl 0x3\(%edx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%eax\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 0d 99 03 00 00 bndcu 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 49 03 bndcu 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
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@ -109,7 +104,6 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f2 0f 1a 4c 02 03 bndcu 0x3\(%edx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%eax\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 0d 99 03 00 00 bndcn 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 49 03 bndcn 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
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@ -127,13 +121,13 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 0f 1a 9a 99 03 00 00 bndldx 0x399\(%edx\),%bnd3
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[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%ebx,1\),%bnd2
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[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%edx\),%bnd1
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[ ]*[a-f0-9]+: f2 e8 0e 00 00 00 bnd call 2c1 <foo>
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[ ]*[a-f0-9]+: f2 e8 0e 00 00 00 bnd call 2a9 <foo>
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[ ]*[a-f0-9]+: f2 ff d0 bnd call \*%eax
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[ ]*[a-f0-9]+: f2 74 08 bnd je 2c1 <foo>
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[ ]*[a-f0-9]+: f2 eb 05 bnd jmp 2c1 <foo>
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[ ]*[a-f0-9]+: f2 74 08 bnd je 2a9 <foo>
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[ ]*[a-f0-9]+: f2 eb 05 bnd jmp 2a9 <foo>
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[ ]*[a-f0-9]+: f2 ff e1 bnd jmp \*%ecx
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[ ]*[a-f0-9]+: f2 c3 bnd ret
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0+2c1 <foo>:
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[a-f0-9]+ <foo>:
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[ ]*[a-f0-9]+: f2 c3 bnd ret
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#pass
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@ -1,7 +1,7 @@
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# MPX instructions
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.allow_index_reg
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.text
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start:
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### bndmk
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bndmk (%eax), %bnd1
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bndmk (0x399), %bnd1
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@ -30,7 +30,6 @@
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### bndcl
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bndcl (%ecx), %bnd1
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bndcl %ecx, %bnd1
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bndcl %ax, %bnd1
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bndcl (0x399), %bnd1
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bndcl 0x3(%edx), %bnd1
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bndcl (%eax,%ecx), %bnd1
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@ -40,7 +39,6 @@
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### bndcu
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bndcu (%ecx), %bnd1
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bndcu %ecx, %bnd1
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bndcu %ax, %bnd1
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bndcu (0x399), %bnd1
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bndcu 0x3(%edx), %bnd1
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bndcu (%eax,%ecx), %bnd1
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@ -50,7 +48,6 @@
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### bndcn
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bndcn (%ecx), %bnd1
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bndcn %ecx, %bnd1
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bndcn %ax, %bnd1
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bndcn (0x399), %bnd1
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bndcn 0x3(%edx), %bnd1
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bndcn (%eax,%ecx), %bnd1
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@ -111,7 +108,6 @@
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### bndcl
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bndcl bnd1, [eax]
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bndcl bnd1, ecx
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bndcl bnd1, ax
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bndcl bnd1, [0x399]
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bndcl bnd1, [ecx+0x3]
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bndcl bnd1, [eax+ecx]
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@ -121,7 +117,6 @@
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### bndcu
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bndcu bnd1, [eax]
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bndcu bnd1, ecx
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bndcu bnd1, ax
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bndcu bnd1, [0x399]
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bndcu bnd1, [ecx+0x3]
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bndcu bnd1, [eax+ecx]
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@ -131,7 +126,6 @@
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### bndcn
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bndcn bnd1, [eax]
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bndcn bnd1, ecx
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bndcn bnd1, ax
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bndcn bnd1, [0x399]
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bndcn bnd1, [ecx+0x3]
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bndcn bnd1, [eax+ecx]
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@ -6,7 +6,7 @@
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Disassembly of section .text:
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0+ <foo-0x434>:
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0+ <start>:
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[ ]*[a-f0-9]+: f3 41 0f 1b 0b bndmk \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1b 08 bndmk \(%rax\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1b 0c 25 99 03 00 00 bndmk 0x399,%bnd1
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@ -38,9 +38,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
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[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
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[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
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[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1a cb bndcl %r11,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %rcx,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1a 51 03 bndcl 0x3\(%r9\),%bnd2
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[ ]*[a-f0-9]+: f3 0f 1a 50 03 bndcl 0x3\(%rax\),%bnd2
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@ -50,9 +49,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
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[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
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[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a cb bndcu %r11,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %rcx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a 51 03 bndcu 0x3\(%r9\),%bnd2
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[ ]*[a-f0-9]+: f2 0f 1a 50 03 bndcu 0x3\(%rax\),%bnd2
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@ -62,9 +60,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
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[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
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[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1b cb bndcn %r11,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %rcx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1b 51 03 bndcn 0x3\(%r9\),%bnd2
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[ ]*[a-f0-9]+: f2 0f 1b 50 03 bndcn 0x3\(%rax\),%bnd2
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@ -88,11 +85,11 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
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[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
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[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
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[ ]*[a-f0-9]+: f2 e8 34 02 00 00 bnd callq 434 <foo>
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[ ]*[a-f0-9]+: f2 e8 25 02 00 00 bnd callq 416 <foo>
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[ ]*[a-f0-9]+: f2 ff 10 bnd callq \*\(%rax\)
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[ ]*[a-f0-9]+: f2 41 ff 13 bnd callq \*\(%r11\)
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[ ]*[a-f0-9]+: f2 0f 84 26 02 00 00 bnd je 434 <foo>
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[ ]*[a-f0-9]+: f2 e9 20 02 00 00 bnd jmpq 434 <foo>
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[ ]*[a-f0-9]+: f2 0f 84 17 02 00 00 bnd je 416 <foo>
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[ ]*[a-f0-9]+: f2 e9 11 02 00 00 bnd jmpq 416 <foo>
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[ ]*[a-f0-9]+: f2 ff 21 bnd jmpq \*\(%rcx\)
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[ ]*[a-f0-9]+: f2 41 ff 24 24 bnd jmpq \*\(%r12\)
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[ ]*[a-f0-9]+: f2 c3 bnd retq
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@ -127,9 +124,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
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[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 08 bndcl \(%rax\),%bnd1
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[ ]*[a-f0-9]+: f3 49 0f 1a cb bndcl %r11,%bnd1
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[ ]*[a-f0-9]+: f3 48 0f 1a c9 bndcl %rcx,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c8 bndcl %eax,%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1a cb bndcl %r11,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %rcx,%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1a 49 03 bndcl 0x3\(%r9\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a 48 03 bndcl 0x3\(%rax\),%bnd1
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@ -139,9 +135,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
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[ ]*[a-f0-9]+: f2 49 0f 1a cb bndcu %r11,%bnd1
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[ ]*[a-f0-9]+: f2 48 0f 1a c9 bndcu %rcx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c8 bndcu %eax,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a cb bndcu %r11,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %rcx,%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a 49 03 bndcu 0x3\(%r9\),%bnd1
|
||||
[ ]*[a-f0-9]+: f2 0f 1a 48 03 bndcu 0x3\(%rax\),%bnd1
|
||||
|
|
@ -151,9 +146,8 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
|
||||
[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
|
||||
[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
|
||||
[ ]*[a-f0-9]+: f2 49 0f 1b cb bndcn %r11,%bnd1
|
||||
[ ]*[a-f0-9]+: f2 48 0f 1b c9 bndcn %rcx,%bnd1
|
||||
[ ]*[a-f0-9]+: f2 0f 1b c8 bndcn %eax,%bnd1
|
||||
[ ]*[a-f0-9]+: f2 41 0f 1b cb bndcn %r11,%bnd1
|
||||
[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %rcx,%bnd1
|
||||
[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
|
||||
[ ]*[a-f0-9]+: f2 41 0f 1b 49 03 bndcn 0x3\(%r9\),%bnd1
|
||||
[ ]*[a-f0-9]+: f2 0f 1b 48 03 bndcn 0x3\(%rax\),%bnd1
|
||||
|
|
@ -177,15 +171,15 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
|
||||
[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
|
||||
[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
|
||||
[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd callq 434 <foo>
|
||||
[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd callq 416 <foo>
|
||||
[ ]*[a-f0-9]+: f2 ff d0 bnd callq \*%rax
|
||||
[ ]*[a-f0-9]+: f2 41 ff d3 bnd callq \*%r11
|
||||
[ ]*[a-f0-9]+: f2 74 0c bnd je 434 <foo>
|
||||
[ ]*[a-f0-9]+: f2 eb 09 bnd jmp 434 <foo>
|
||||
[ ]*[a-f0-9]+: f2 74 0c bnd je 416 <foo>
|
||||
[ ]*[a-f0-9]+: f2 eb 09 bnd jmp 416 <foo>
|
||||
[ ]*[a-f0-9]+: f2 ff e1 bnd jmpq \*%rcx
|
||||
[ ]*[a-f0-9]+: f2 41 ff e4 bnd jmpq \*%r12
|
||||
[ ]*[a-f0-9]+: f2 c3 bnd retq
|
||||
|
||||
0+434 <foo>:
|
||||
[a-f0-9]+ <foo>:
|
||||
[ ]*[a-f0-9]+: f2 c3 bnd retq
|
||||
#pass
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
# MPX instructions
|
||||
.allow_index_reg
|
||||
.text
|
||||
|
||||
start:
|
||||
### bndmk
|
||||
bndmk (%r11), %bnd1
|
||||
bndmk (%rax), %bnd1
|
||||
|
|
@ -41,7 +41,6 @@
|
|||
bndcl (%rax), %bnd1
|
||||
bndcl %r11, %bnd1
|
||||
bndcl %rcx, %bnd1
|
||||
bndcl %ax, %bnd1
|
||||
bndcl (0x399), %bnd1
|
||||
bndcl 0x3(%r9), %bnd2
|
||||
bndcl 0x3(%rax), %bnd2
|
||||
|
|
@ -55,7 +54,6 @@
|
|||
bndcu (%rax), %bnd1
|
||||
bndcu %r11, %bnd1
|
||||
bndcu %rcx, %bnd1
|
||||
bndcu %ax, %bnd1
|
||||
bndcu (0x399), %bnd1
|
||||
bndcu 0x3(%r9), %bnd2
|
||||
bndcu 0x3(%rax), %bnd2
|
||||
|
|
@ -69,7 +67,6 @@
|
|||
bndcn (%rax), %bnd1
|
||||
bndcn %r11, %bnd1
|
||||
bndcn %rcx, %bnd1
|
||||
bndcn %ax, %bnd1
|
||||
bndcn (0x399), %bnd1
|
||||
bndcn 0x3(%r9), %bnd2
|
||||
bndcn 0x3(%rax), %bnd2
|
||||
|
|
@ -147,7 +144,6 @@
|
|||
bndcl bnd1, [rax]
|
||||
bndcl bnd1, r11
|
||||
bndcl bnd1, rcx
|
||||
bndcl bnd1, ax
|
||||
bndcl bnd1, [0x399]
|
||||
bndcl bnd1, [r9+0x3]
|
||||
bndcl bnd1, [rax+0x3]
|
||||
|
|
@ -161,7 +157,6 @@
|
|||
bndcu bnd1, [rax]
|
||||
bndcu bnd1, r11
|
||||
bndcu bnd1, rcx
|
||||
bndcu bnd1, ax
|
||||
bndcu bnd1, [0x399]
|
||||
bndcu bnd1, [r9+0x3]
|
||||
bndcu bnd1, [rax+0x3]
|
||||
|
|
@ -175,7 +170,6 @@
|
|||
bndcn bnd1, [rax]
|
||||
bndcn bnd1, r11
|
||||
bndcn bnd1, rcx
|
||||
bndcn bnd1, ax
|
||||
bndcn bnd1, [0x399]
|
||||
bndcn bnd1, [r9+0x3]
|
||||
bndcn bnd1, [rax+0x3]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,13 @@
|
|||
2013-10-12 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
|
||||
default case.
|
||||
(OP_E_register): Move v_bnd_mode alongside m_mode.
|
||||
* i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
|
||||
Drop Reg16 and Disp16. Add NoRex64.
|
||||
(bndmk, bndmov, bndldx, bndstx): Drop Disp16.
|
||||
* i386-tbl.h: Re-generate.
|
||||
|
||||
2013-10-10 Sean Keys <skeys@ipdatasys.com>
|
||||
|
||||
* xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
|
||||
|
|
|
|||
|
|
@ -13808,7 +13808,6 @@ intel_operand_size (int bytemode, int sizeflag)
|
|||
}
|
||||
/* FALLTHRU */
|
||||
case v_mode:
|
||||
case v_bnd_mode:
|
||||
case v_swap_mode:
|
||||
case dq_mode:
|
||||
USED_REX (REX_W);
|
||||
|
|
@ -14090,6 +14089,7 @@ intel_operand_size (int bytemode, int sizeflag)
|
|||
abort ();
|
||||
oappend ("WORD PTR ");
|
||||
break;
|
||||
case v_bnd_mode:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -14129,6 +14129,7 @@ OP_E_register (int bytemode, int sizeflag)
|
|||
names = names64;
|
||||
break;
|
||||
case m_mode:
|
||||
case v_bnd_mode:
|
||||
names = address_mode == mode_64bit ? names64 : names32;
|
||||
break;
|
||||
case bnd_mode:
|
||||
|
|
@ -14143,7 +14144,6 @@ OP_E_register (int bytemode, int sizeflag)
|
|||
bytemode = v_mode;
|
||||
/* FALLTHRU */
|
||||
case v_mode:
|
||||
case v_bnd_mode:
|
||||
case v_swap_mode:
|
||||
case dq_mode:
|
||||
case dqb_mode:
|
||||
|
|
|
|||
|
|
@ -3061,14 +3061,17 @@ stac, 0, 0xf01, 0xcb, 2, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
|
|||
bnd, 0, 0xf2, None, 1, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, { 0 }
|
||||
|
||||
// MPX instructions.
|
||||
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
|
||||
bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND, RegBND }
|
||||
bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegBND }
|
||||
bndcl, 2, 0xf30f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
|
||||
bndcu, 2, 0xf20f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
|
||||
bndcn, 2, 0xf20f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Reg64|Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
|
||||
bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegBND }
|
||||
bndmk, 2, 0xf30f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
|
||||
bndmov, 2, 0x660f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND, RegBND }
|
||||
bndmov, 2, 0x660f1b, None, 2, CpuMPX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Xmmword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S|RegBND }
|
||||
bndcl, 2, 0xf30f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
|
||||
bndcl, 2, 0xf30f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
|
||||
bndcu, 2, 0xf20f1a, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
|
||||
bndcu, 2, 0xf20f1a, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
|
||||
bndcn, 2, 0xf20f1b, None, 2, CpuMPX|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Anysize|BaseIndex|Disp8|Disp32, RegBND }
|
||||
bndcn, 2, 0xf20f1b, None, 2, CpuMPX|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg64|Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
|
||||
bndstx, 2, 0x0f1b, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegBND, Anysize|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
bndldx, 2, 0x0f1a, None, 2, CpuMPX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Anysize|BaseIndex|Disp8|Disp32|Disp32S, RegBND }
|
||||
|
||||
// SHA instructions.
|
||||
sha1rnds4, 3, 0xf3acc, None, 3, CpuSHA, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|RegXMM|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, RegXMM }
|
||||
|
|
|
|||
|
|
@ -53874,7 +53874,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -53889,7 +53889,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -53907,19 +53907,34 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0 } } } },
|
||||
{ "bndcl", 2, 0xf30f1a, None, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "bndcl", 2, 0xf30f1a, None, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -53928,13 +53943,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "bndcu", 2, 0xf20f1a, None, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -53943,13 +53973,28 @@ const insn_template i386_optab[] =
|
|||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
{ { { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } } } },
|
||||
{ "bndcn", 2, 0xf20f1b, None, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -53967,7 +54012,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } } } },
|
||||
{ "bndldx", 2, 0x0f1a, None, 2,
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
@ -53979,7 +54024,7 @@ const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0 },
|
||||
{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 1, 0, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue