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x86: Support VEX/EVEX WIG encoding

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Add VEXWIG, defined as 3, to indicate that the VEX.W/EVEX.W bit is
ignored by such VEX/EVEX instructions, aka WIG instructions.  Set
VexW=3 on VEX/EVEX WIG instructions.  Update assembler to check
VEXWIG when setting the VEX.W bit.

gas/

	PR gas/23642
	* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
	the VEX.W bit.
	(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.

opcodes/

	PR gas/23642
	* i386-opc.h (VEXWIG): New.
	* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
	* i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu 2018-09-14 12:19:58 -07:00
parent 70df6fc9bc
commit 6865c0435a
6 changed files with 960 additions and 947 deletions
Download patch file Download diff file Expand all files Collapse all files

7
gas/ChangeLog
View file

@ -1,3 +1,10 @@
2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
PR gas/23642
* config/tc-i386.c (build_vex_prefix): Check VEXWIG when setting
the VEX.W bit.
(build_evex_prefix): Check VEXWIG when setting the EVEX.W bit.
2018-09-14 H.J. Lu <hongjiu.lu@intel.com> 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/23655 PR binutils/23655

31
gas/config/tc-i386.c
View file

@ -3499,10 +3499,13 @@ build_vex_prefix (const insn_template *t)
of RXB bits from REX. */ of RXB bits from REX. */
i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m; i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
/* Check the REX.W bit. */ /* Check the REX.W bit and VEXW. */
w = (i.rex & REX_W) ? 1 : 0; if (i.tm.opcode_modifier.vexw == VEXWIG)
if (i.tm.opcode_modifier.vexw == VEXW1) w = (i.rex & REX_W) ? 1 : 0;
w = 1; else if (i.tm.opcode_modifier.vexw)
w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
else
w = (i.rex & REX_W) ? 1 : 0;
i.vex.bytes[2] = (w << 7 i.vex.bytes[2] = (w << 7
| register_specifier << 3 | register_specifier << 3
@ -3629,19 +3632,13 @@ build_evex_prefix (void)
i.vrex &= ~vrex_used; i.vrex &= ~vrex_used;
gas_assert (i.vrex == 0); gas_assert (i.vrex == 0);
/* Check the REX.W bit. */ /* Check the REX.W bit and VEXW. */
w = (i.rex & REX_W) ? 1 : 0; if (i.tm.opcode_modifier.vexw == VEXWIG)
if (i.tm.opcode_modifier.vexw) w = (evexwig == evexw1 || (i.rex & REX_W)) ? 1 : 0;
{ else if (i.tm.opcode_modifier.vexw)
if (i.tm.opcode_modifier.vexw == VEXW1) w = i.tm.opcode_modifier.vexw == VEXW1 ? 1 : 0;
w = 1; else
} w = (i.rex & REX_W) ? 1 : 0;
/* If w is not set it means we are dealing with WIG instruction. */
else if (!w)
{
if (evexwig == evexw1)
w = 1;
}
/* Encode the U bit. */ /* Encode the U bit. */
implied_prefix |= 0x4; implied_prefix |= 0x4;

7
opcodes/ChangeLog
View file

@ -1,3 +1,10 @@
2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
PR gas/23642
* i386-opc.h (VEXWIG): New.
* i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
* i386-tbl.h: Regenerated.
2018-09-14 H.J. Lu <hongjiu.lu@intel.com> 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/23655 PR binutils/23655

2
opcodes/i386-opc.h
View file

@ -499,9 +499,11 @@ enum
0: Set by the REX.W bit. 0: Set by the REX.W bit.
1: VEX.W0. Should always be 0. 1: VEX.W0. Should always be 0.
2: VEX.W1. Should always be 1. 2: VEX.W1. Should always be 1.
3: VEX.WIG. The VEX.W bit is ignored.
*/ */
#define VEXW0 1 #define VEXW0 1
#define VEXW1 2 #define VEXW1 2
#define VEXWIG 3
VexW, VexW,
/* VEX opcode prefix: /* VEX opcode prefix:
0: VEX 0x0F opcode prefix. 0: VEX 0x0F opcode prefix.

930
opcodes/i386-opc.tbl
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opcodes/i386-tbl.h
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