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Add fr450 support.

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This commit is contained in:
Richard Sandiford 2004-03-01 10:11:46 +00:00
parent c7a48b9ac9
commit 676a64f422
74 changed files with 23588 additions and 1421 deletions
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11
bfd/ChangeLog
View file

@ -1,3 +1,14 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* archures.c (bfd_mach_fr450): New.
* bfd-in2.h: Regenerate.
* cpu-frv.c (arch_info_450): New bfd_arch_info_type.
(arch_info_500): Link to it.
* elf32-frv.c (elf32_frv_machine, frv_elf_merge_private_bfd_data)
(frv_elf_print_private_bfd_data): Handle fr405 and fr450 header flags.
(frv_elf_arch_extension_p): New function.
(frv_elf_merge_private_bfd_data): Use it.
2004-02-28 H.J. Lu <hongjiu.lu@intel.com>
* elf-bfd.h (_bfd_elf_link_add_archive_symbols): New prototype.

1
bfd/archures.c
View file

@ -285,6 +285,7 @@ DESCRIPTION
.#define bfd_mach_frvsimple 2
.#define bfd_mach_fr300 300
.#define bfd_mach_fr400 400
.#define bfd_mach_fr450 450
.#define bfd_mach_frvtomcat 499 {* fr500 prototype *}
.#define bfd_mach_fr500 500
.#define bfd_mach_fr550 550

1
bfd/bfd-in2.h
View file

@ -1717,6 +1717,7 @@ enum bfd_architecture
#define bfd_mach_frvsimple 2
#define bfd_mach_fr300 300
#define bfd_mach_fr400 400
#define bfd_mach_fr450 450
#define bfd_mach_frvtomcat 499 /* fr500 prototype */
#define bfd_mach_fr500 500
#define bfd_mach_fr550 550

5
bfd/cpu-frv.c
View file

@ -43,8 +43,11 @@ static const bfd_arch_info_type arch_info_300
static const bfd_arch_info_type arch_info_400
= FRV_ARCH (bfd_mach_fr400, "fr400", FALSE, &arch_info_300);
static const bfd_arch_info_type arch_info_450
= FRV_ARCH (bfd_mach_fr450, "fr450", FALSE, &arch_info_400);
static const bfd_arch_info_type arch_info_500
= FRV_ARCH (bfd_mach_fr500, "fr500", FALSE, &arch_info_400);
= FRV_ARCH (bfd_mach_fr500, "fr500", FALSE, &arch_info_450);
static const bfd_arch_info_type arch_info_550
= FRV_ARCH (bfd_mach_fr550, "fr550", FALSE, &arch_info_500);

42
bfd/elf32-frv.c
View file

@ -4032,6 +4032,8 @@ elf32_frv_machine (abfd)
default: break;
case EF_FRV_CPU_FR550: return bfd_mach_fr550;
case EF_FRV_CPU_FR500: return bfd_mach_fr500;
case EF_FRV_CPU_FR450: return bfd_mach_fr450;
case EF_FRV_CPU_FR405: return bfd_mach_fr400;
case EF_FRV_CPU_FR400: return bfd_mach_fr400;
case EF_FRV_CPU_FR300: return bfd_mach_fr300;
case EF_FRV_CPU_SIMPLE: return bfd_mach_frvsimple;
@ -4082,6 +4084,33 @@ frv_elf_copy_private_bfd_data (ibfd, obfd)
return TRUE;
}
/* Return true if the architecture described by elf header flag
EXTENSION is an extension of the architecture described by BASE. */
static bfd_boolean
frv_elf_arch_extension_p (flagword base, flagword extension)
{
if (base == extension)
return TRUE;
/* CPU_GENERIC code can be merged with code for a specific
architecture, in which case the result is marked as being
for the specific architecture. Everything is therefore
an extension of CPU_GENERIC. */
if (base == EF_FRV_CPU_GENERIC)
return TRUE;
if (extension == EF_FRV_CPU_FR450)
if (base == EF_FRV_CPU_FR400 || base == EF_FRV_CPU_FR405)
return TRUE;
if (extension == EF_FRV_CPU_FR405)
if (base == EF_FRV_CPU_FR400)
return TRUE;
return FALSE;
}
/* Merge backend specific data from an object file to the output
object file when linking. */
@ -4266,13 +4295,10 @@ frv_elf_merge_private_bfd_data (ibfd, obfd)
the generic cpu). */
new_partial = (new_flags & EF_FRV_CPU_MASK);
old_partial = (old_flags & EF_FRV_CPU_MASK);
if (new_partial == old_partial)
if (frv_elf_arch_extension_p (new_partial, old_partial))
;
else if (new_partial == EF_FRV_CPU_GENERIC)
;
else if (old_partial == EF_FRV_CPU_GENERIC)
else if (frv_elf_arch_extension_p (old_partial, new_partial))
old_flags = (old_flags & ~EF_FRV_CPU_MASK) | new_partial;
else
@ -4284,6 +4310,8 @@ frv_elf_merge_private_bfd_data (ibfd, obfd)
case EF_FRV_CPU_SIMPLE: strcat (new_opt, " -mcpu=simple"); break;
case EF_FRV_CPU_FR550: strcat (new_opt, " -mcpu=fr550"); break;
case EF_FRV_CPU_FR500: strcat (new_opt, " -mcpu=fr500"); break;
case EF_FRV_CPU_FR450: strcat (new_opt, " -mcpu=fr450"); break;
case EF_FRV_CPU_FR405: strcat (new_opt, " -mcpu=fr405"); break;
case EF_FRV_CPU_FR400: strcat (new_opt, " -mcpu=fr400"); break;
case EF_FRV_CPU_FR300: strcat (new_opt, " -mcpu=fr300"); break;
case EF_FRV_CPU_TOMCAT: strcat (new_opt, " -mcpu=tomcat"); break;
@ -4296,6 +4324,8 @@ frv_elf_merge_private_bfd_data (ibfd, obfd)
case EF_FRV_CPU_SIMPLE: strcat (old_opt, " -mcpu=simple"); break;
case EF_FRV_CPU_FR550: strcat (old_opt, " -mcpu=fr550"); break;
case EF_FRV_CPU_FR500: strcat (old_opt, " -mcpu=fr500"); break;
case EF_FRV_CPU_FR450: strcat (old_opt, " -mcpu=fr450"); break;
case EF_FRV_CPU_FR405: strcat (old_opt, " -mcpu=fr405"); break;
case EF_FRV_CPU_FR400: strcat (old_opt, " -mcpu=fr400"); break;
case EF_FRV_CPU_FR300: strcat (old_opt, " -mcpu=fr300"); break;
case EF_FRV_CPU_TOMCAT: strcat (old_opt, " -mcpu=tomcat"); break;
@ -4363,6 +4393,8 @@ frv_elf_print_private_bfd_data (abfd, ptr)
case EF_FRV_CPU_SIMPLE: fprintf (file, " -mcpu=simple"); break;
case EF_FRV_CPU_FR550: fprintf (file, " -mcpu=fr550"); break;
case EF_FRV_CPU_FR500: fprintf (file, " -mcpu=fr500"); break;
case EF_FRV_CPU_FR450: fprintf (file, " -mcpu=fr450"); break;
case EF_FRV_CPU_FR405: fprintf (file, " -mcpu=fr405"); break;
case EF_FRV_CPU_FR400: fprintf (file, " -mcpu=fr400"); break;
case EF_FRV_CPU_FR300: fprintf (file, " -mcpu=fr300"); break;
case EF_FRV_CPU_TOMCAT: fprintf (file, " -mcpu=tomcat"); break;

32
cpu/ChangeLog
View file

@ -1,3 +1,35 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (define-arch frv): Add fr450 mach.
(define-mach fr450): New.
(define-model fr450): New. Add profile units to every fr450 insn.
(define-attr UNIT): Add MDCUTSSI.
(define-attr FR450-MAJOR): New enum. Add to every fr450 insn.
(define-attr AUDIO): New boolean.
(f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
(f-LRA-null, f-TLBPR-null): New fields.
(scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
(tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
(LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
(LRA-null, TLBPR-null): New macros.
(iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
(load-real-address): New macro.
(lrai, lrad, tlbpr): New instructions.
(media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
(mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
(mdcutssi): Change UNIT attribute to MDCUTSSI.
(media-low-clear-semantics, media-scope-limit-semantics)
(media-quad-limit, media-quad-shift): New macros.
(mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
* frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
(frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
(frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
(fr450_unit_mapping): New array.
(fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
for new MDCUTSSI unit.
(fr450_check_insn_major_constraints): New function.
(check_insn_major_constraints): Use it.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.

1864
cpu/frv.cpu
View file

File diff suppressed because it is too large Load diff

105
cpu/frv.opc
View file

@ -90,6 +90,8 @@ static int find_major_in_vliw
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr400_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr450_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr500_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr550_check_insn_major_constraints
@ -106,6 +108,10 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
return 1; /* is a branch */
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
return 1; /* is a branch */
break;
default:
if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
return 1; /* is a branch */
@ -121,6 +127,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
switch (mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
return 0; /* No float insns */
default:
if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
@ -140,6 +147,10 @@ frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
return 1; /* is a media insn */
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
return 1; /* is a media insn */
break;
default:
if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
return 1; /* is a media insn */
@ -155,6 +166,9 @@ frv_is_branch_insn (const CGEN_INSN *insn)
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
@ -168,6 +182,9 @@ frv_is_float_insn (const CGEN_INSN *insn)
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
@ -181,6 +198,9 @@ frv_is_media_insn (const CGEN_INSN *insn)
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
@ -291,6 +311,42 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
};
/* Some insns are assigned specialized implementation units which map to
different actual implementation units on different machines. These
tables perform that mapping. */
static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
{
/* unit in insn actual unit */
/* NIL */ UNIT_NIL,
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* I2 */ UNIT_NIL, /* no I2 or I3 unit */
/* I3 */ UNIT_NIL,
/* IALL */ UNIT_I01, /* only I0 and I1 units */
/* FM0 */ UNIT_FM0,
/* FM1 */ UNIT_FM1,
/* FM01 */ UNIT_FM01,
/* FM2 */ UNIT_NIL, /* no F2 or M2 units */
/* FM3 */ UNIT_NIL, /* no F3 or M3 units */
/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
/* B0 */ UNIT_B0, /* branches only in B0 unit. */
/* B1 */ UNIT_B0,
/* B01 */ UNIT_B0,
/* C */ UNIT_C,
/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */
/* LOAD */ UNIT_I0, /* load only in I0 unit. */
/* STORE */ UNIT_I0, /* store only in I0 unit. */
/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */
/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
};
@ -322,6 +378,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
@ -353,6 +410,7 @@ static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
/* SCAN */ UNIT_IALL, /* scan in any integer unit. */
/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
/* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */
/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
@ -370,6 +428,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
vliw->current_vliw = fr400_allowed_vliw;
vliw->unit_mapping = fr400_unit_mapping;
break;
case bfd_mach_fr450:
vliw->current_vliw = fr400_allowed_vliw;
vliw->unit_mapping = fr450_unit_mapping;
break;
case bfd_mach_fr550:
vliw->current_vliw = fr550_allowed_vliw;
vliw->unit_mapping = fr550_unit_mapping;
@ -507,6 +569,43 @@ fr400_check_insn_major_constraints (
return 1;
}
static int
fr450_check_insn_major_constraints (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
)
{
CGEN_ATTR_VALUE_TYPE other_major;
/* Our caller guarantees there's at least one other instruction. */
other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
/* (M4, M5) and (M4, M6) are allowed. */
if (other_major == FR450_MAJOR_M_4)
if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
return 1;
/* Otherwise, instructions in even-numbered media categories cannot be
executed in parallel with other media instructions. */
switch (major)
{
case FR450_MAJOR_M_2:
case FR450_MAJOR_M_4:
case FR450_MAJOR_M_6:
return !(other_major >= FR450_MAJOR_M_1
&& other_major <= FR450_MAJOR_M_6);
case FR450_MAJOR_M_1:
case FR450_MAJOR_M_3:
case FR450_MAJOR_M_5:
return !(other_major == FR450_MAJOR_M_2
|| other_major == FR450_MAJOR_M_4
|| other_major == FR450_MAJOR_M_6);
default:
return 1;
}
}
static int
find_unit_in_vliw (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
@ -744,6 +843,9 @@ check_insn_major_constraints (
case bfd_mach_fr400:
rc = fr400_check_insn_major_constraints (vliw, major);
break;
case bfd_mach_fr450:
rc = fr450_check_insn_major_constraints (vliw, major);
break;
case bfd_mach_fr550:
rc = fr550_check_insn_major_constraints (vliw, major, insn);
break;
@ -784,6 +886,9 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
case bfd_mach_fr400:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
break;
case bfd_mach_fr450:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR);
break;
case bfd_mach_fr550:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR);
break;

9
gas/ChangeLog
View file

@ -1,3 +1,12 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* config/tc-frv.c (fr400_audio): New variable.
(md_parse_option, md_show_usage): Add -mcpu=fr405 and -mcpu=fr450.
(md_parse_option): Set fr400_audio for -mcpu=fr400 and -mcpu=fr405.
(target_implements_insn_p): New function.
(md_assemble): Report an error if the processor doesn't implement
the instruction.
2004-02-27 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* config/tc-m32r.c (md_longopts): Added -no-bitinst option.

52
gas/config/tc-frv.c
View file

@ -163,6 +163,7 @@ static FRV_VLIW vliw;
#endif
static unsigned long frv_mach = bfd_mach_frv;
static bfd_boolean fr400_audio;
/* Flags to set in the elf header */
static flagword frv_flags = DEFAULT_FLAGS;
@ -354,10 +355,24 @@ md_parse_option (c, arg)
frv_mach = bfd_mach_fr550;
}
else if (strcmp (p, "fr450") == 0)
{
cpu_flags = EF_FRV_CPU_FR450;
frv_mach = bfd_mach_fr450;
}
else if (strcmp (p, "fr405") == 0)
{
cpu_flags = EF_FRV_CPU_FR405;
frv_mach = bfd_mach_fr400;
fr400_audio = TRUE;
}
else if (strcmp (p, "fr400") == 0)
{
cpu_flags = EF_FRV_CPU_FR400;
frv_mach = bfd_mach_fr400;
fr400_audio = FALSE;
}
else if (strcmp (p, "fr300") == 0)
@ -446,7 +461,7 @@ md_show_usage (stream)
fprintf (stream, _("-mpic Note small position independent code\n"));
fprintf (stream, _("-mPIC Note large position independent code\n"));
fprintf (stream, _("-mlibrary-pic Compile library for large position indepedent code\n"));
fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr300|frv|simple|tomcat}\n"));
fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"));
fprintf (stream, _(" Record the cpu type\n"));
fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n"));
fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n"));
@ -1042,6 +1057,36 @@ fr550_check_acc_range (FRV_VLIW *vliw, frv_insn *insn)
return 0; /* all is ok */
}
/* Return true if the target implements instruction INSN. */
static bfd_boolean
target_implements_insn_p (const CGEN_INSN *insn)
{
switch (frv_mach)
{
default:
/* bfd_mach_frv or generic. */
return TRUE;
case bfd_mach_fr300:
case bfd_mach_frvsimple:
return CGEN_INSN_MACH_HAS_P (insn, MACH_SIMPLE);
case bfd_mach_fr400:
return ((fr400_audio || !CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_AUDIO))
&& CGEN_INSN_MACH_HAS_P (insn, MACH_FR400));
case bfd_mach_fr450:
return CGEN_INSN_MACH_HAS_P (insn, MACH_FR450);
case bfd_mach_fr500:
return CGEN_INSN_MACH_HAS_P (insn, MACH_FR500);
case bfd_mach_fr550:
return CGEN_INSN_MACH_HAS_P (insn, MACH_FR550);
}
}
void
md_assemble (str)
char * str;
@ -1125,6 +1170,11 @@ md_assemble (str)
instructions, don't do vliw checking. */
else if (frv_mach != bfd_mach_frv)
{
if (!target_implements_insn_p (insn.insn))
{
as_bad (_("Instruction not supported by this architecture"));
return;
}
packing_constraint = frv_vliw_add_insn (& vliw, insn.insn);
if (frv_mach == bfd_mach_fr550 && ! packing_constraint)
packing_constraint = fr550_check_acc_range (& vliw, & insn);

11
gas/testsuite/ChangeLog
View file

@ -1,3 +1,14 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* gas/frv/fr405-insn.[sdl]: New test.
* gas/frv/fr450-spr.[sd]: New test.
* gas/frv/fr450-insn.[sdl]: New test.
* gas/frv/fr450-media-issue.[sl]: New test.
* gas/frv/allinsn.exp: Run new tests. Ensure fr405 instructions
aren't accepted for -mcpu=fr400 or -mcpu=fr500. Ensure fr450
instructions aren't accepted for -mcpu=fr400, -mcpu=fr405 or
-mcpu=fr500.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.

22
gas/testsuite/gas/frv/allinsn.exp
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@ -1,8 +1,30 @@
# FRV assembler testsuite.
proc run_list_test { name opts } {
global srcdir subdir
set testname "$name error test ($opts)"
gas_run $name.s $opts >&dump.out
if {[regexp_diff dump.out $srcdir/$subdir/$name.l]} {
fail $testname
verbose "output is [file_contents dump.out]" 2
return
}
pass $testname
}
if [istarget frv*-*-*] {
run_dump_test "allinsn"
run_dump_test "fdpic"
run_dump_test "reloc1"
run_dump_test "fr405-insn"
run_list_test "fr405-insn" "-mcpu=fr400"
run_list_test "fr405-insn" "-mcpu=fr500"
run_dump_test "fr450-spr"
run_dump_test "fr450-insn"
run_list_test "fr450-insn" "-mcpu=fr405"
run_list_test "fr450-insn" "-mcpu=fr400"
run_list_test "fr450-insn" "-mcpu=fr500"
run_list_test "fr450-media-issue" "-mcpu=fr450"
}

15
gas/testsuite/gas/frv/fr405-insn.d Normal file
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@ -0,0 +1,15 @@
#as: -mcpu=fr405
#objdump: -dr
.*: file format elf32-frv
Disassembly of section \.text:
00000000 <.*>:
.*: 81 18 41 45 smu gr4,gr5
.*: 81 18 41 85 smass gr4,gr5
.*: 81 18 41 c5 smsss gr4,gr5
.*: 8d 18 40 85 slass gr4,gr5,gr6
.*: 8b 18 01 04 scutss gr4,gr5
.*: 8d 18 40 05 addss gr4,gr5,gr6
.*: 8d 18 40 45 subss gr4,gr5,gr6

8
gas/testsuite/gas/frv/fr405-insn.l Normal file
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@ -0,0 +1,8 @@
.*: Assembler messages:
.*:1: Error: Instruction not supported by this architecture
.*:2: Error: Instruction not supported by this architecture
.*:3: Error: Instruction not supported by this architecture
.*:4: Error: Instruction not supported by this architecture
.*:5: Error: Instruction not supported by this architecture
.*:6: Error: Instruction not supported by this architecture
.*:7: Error: Instruction not supported by this architecture

7
gas/testsuite/gas/frv/fr405-insn.s Normal file
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@ -0,0 +1,7 @@
smu gr4,gr5
smass gr4,gr5
smsss gr4,gr5
slass gr4,gr5,gr6
scutss gr4,gr5
addss gr4,gr5,gr6
subss gr4,gr5,gr6

41
gas/testsuite/gas/frv/fr450-insn.d Normal file
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@ -0,0 +1,41 @@
#as: -mcpu=fr450
#objdump: -dr
.*: file format elf32-frv
Disassembly of section \.text:
00000000 <.*>:
#
.*: 80 0d f8 00 lrai gr31,gr0,0x0,0x0,0x0
.*: be 0c 08 00 lrai gr0,gr31,0x0,0x0,0x0
.*: 80 0c 08 20 lrai gr0,gr0,0x1,0x0,0x0
.*: 80 0c 08 10 lrai gr0,gr0,0x0,0x1,0x0
.*: 80 0c 08 08 lrai gr0,gr0,0x0,0x0,0x1
#
.*: 80 0d f8 40 lrad gr31,gr0,0x0,0x0,0x0
.*: be 0c 08 40 lrad gr0,gr31,0x0,0x0,0x0
.*: 80 0c 08 60 lrad gr0,gr0,0x1,0x0,0x0
.*: 80 0c 08 50 lrad gr0,gr0,0x0,0x1,0x0
.*: 80 0c 08 48 lrad gr0,gr0,0x0,0x0,0x1
#
.*: 80 0d f9 00 tlbpr gr31,gr0,0x0,0x0
.*: 80 0c 09 1f tlbpr gr0,gr31,0x0,0x0
.*: 9c 0c 09 00 tlbpr gr0,gr0,0x7,0x0
.*: 82 0c 09 00 tlbpr gr0,gr0,0x0,0x1
#
.*: 81 e1 e4 00 mqlclrhs fr30,fr0,fr0
.*: 81 e0 04 1e mqlclrhs fr0,fr30,fr0
.*: bd e0 04 00 mqlclrhs fr0,fr0,fr30
#
.*: 81 e1 e5 00 mqlmths fr30,fr0,fr0
.*: 81 e0 05 1e mqlmths fr0,fr30,fr0
.*: bd e0 05 00 mqlmths fr0,fr0,fr30
#
.*: 81 e1 e4 40 mqsllhi fr30,0x0,fr0
.*: 81 e0 04 7f mqsllhi fr0,0x3f,fr0
.*: bd e0 04 40 mqsllhi fr0,0x0,fr30
#
.*: 81 e1 e4 c0 mqsrahi fr30,0x0,fr0
.*: 81 e0 04 ff mqsrahi fr0,0x3f,fr0
.*: bd e0 04 c0 mqsrahi fr0,0x0,fr30

33
gas/testsuite/gas/frv/fr450-insn.l Normal file
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@ -0,0 +1,33 @@
.*: Assembler messages:
.*:1: Error: Instruction not supported by this architecture
.*:2: Error: Instruction not supported by this architecture
.*:3: Error: Instruction not supported by this architecture
.*:4: Error: Instruction not supported by this architecture
.*:5: Error: Instruction not supported by this architecture
#
.*:7: Error: Instruction not supported by this architecture
.*:8: Error: Instruction not supported by this architecture
.*:9: Error: Instruction not supported by this architecture
.*:10: Error: Instruction not supported by this architecture
.*:11: Error: Instruction not supported by this architecture
#
.*:13: Error: Instruction not supported by this architecture
.*:14: Error: Instruction not supported by this architecture
.*:15: Error: Instruction not supported by this architecture
.*:16: Error: Instruction not supported by this architecture
#
.*:18: Error: Instruction not supported by this architecture
.*:19: Error: Instruction not supported by this architecture
.*:20: Error: Instruction not supported by this architecture
#
.*:22: Error: Instruction not supported by this architecture
.*:23: Error: Instruction not supported by this architecture
.*:24: Error: Instruction not supported by this architecture
#
.*:26: Error: Instruction not supported by this architecture
.*:27: Error: Instruction not supported by this architecture
.*:28: Error: Instruction not supported by this architecture
#
.*:30: Error: Instruction not supported by this architecture
.*:31: Error: Instruction not supported by this architecture
.*:32: Error: Instruction not supported by this architecture

32
gas/testsuite/gas/frv/fr450-insn.s Normal file
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@ -0,0 +1,32 @@
lrai gr31,gr0,#0,#0,#0
lrai gr0,gr31,#0,#0,#0
lrai gr0,gr0,#1,#0,#0
lrai gr0,gr0,#0,#1,#0
lrai gr0,gr0,#0,#0,#1
lrad gr31,gr0,#0,#0,#0
lrad gr0,gr31,#0,#0,#0
lrad gr0,gr0,#1,#0,#0
lrad gr0,gr0,#0,#1,#0
lrad gr0,gr0,#0,#0,#1
tlbpr gr31,gr0,#0,#0
tlbpr gr0,gr31,#0,#0
tlbpr gr0,gr0,#7,#0
tlbpr gr0,gr0,#0,#1
mqlclrhs fr30,fr0,fr0
mqlclrhs fr0,fr30,fr0
mqlclrhs fr0,fr0,fr30
mqlmths fr30,fr0,fr0
mqlmths fr0,fr30,fr0
mqlmths fr0,fr0,fr30
mqsllhi fr30,#0,fr0
mqsllhi fr0,#63,fr0
mqsllhi fr0,#0,fr30
mqsrahi fr30,#0,fr0
mqsrahi fr0,#63,fr0
mqsrahi fr0,#0,fr30

31
gas/testsuite/gas/frv/fr450-media-issue.l Normal file
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@ -0,0 +1,31 @@
.*: Assembler messages:
.*:5: Error: VLIW packing constraint violation
.*:9: Error: VLIW packing constraint violation
.*:13: Error: VLIW packing constraint violation
#
.*:17: Error: VLIW packing constraint violation
.*:19: Error: VLIW packing constraint violation
.*:21: Error: VLIW packing constraint violation
.*:23: Error: VLIW packing constraint violation
.*:25: Error: VLIW packing constraint violation
.*:27: Error: VLIW packing constraint violation
#
.*:33: Error: VLIW packing constraint violation
.*:37: Error: VLIW packing constraint violation
.*:41: Error: VLIW packing constraint violation
#
.*:45: Error: VLIW packing constraint violation
.*:47: Error: VLIW packing constraint violation
.*:49: Error: VLIW packing constraint violation
.*:51: Error: VLIW packing constraint violation
#
.*:61: Error: VLIW packing constraint violation
.*:65: Error: VLIW packing constraint violation
.*:69: Error: VLIW packing constraint violation
#
.*:73: Error: VLIW packing constraint violation
.*:75: Error: VLIW packing constraint violation
.*:77: Error: VLIW packing constraint violation
.*:79: Error: VLIW packing constraint violation
.*:81: Error: VLIW packing constraint violation
.*:83: Error: VLIW packing constraint violation

83
gas/testsuite/gas/frv/fr450-media-issue.s Normal file
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@ -0,0 +1,83 @@
; M-1 first
mand.p fr0,fr1,fr2 ; M1
mpackh fr4,fr5,fr6 ; M1 -- ok
mand.p fr0,fr1,fr2 ; M1
mcpli fr4,#1,fr6 ; M2 -- error
mand.p fr0,fr1,fr2 ; M1
mmulhu fr4,fr6,acc8 ; M3 -- ok
mand.p fr0,fr1,fr2 ; M1
mqmulhu fr4,fr6,acc8 ; M4 -- error
mand.p fr0,fr1,fr2 ; M1
mcuti acc8,#2,fr8 ; M5 -- ok
mand.p fr0,fr1,fr2 ; M1
mdcutssi acc8,#2,fr8 ; M6 -- error
; M-2 first
mqaddhss.p fr0,fr2,fr2 ; M2
mpackh fr4,fr5,fr6 ; M1 -- error
mqaddhss.p fr0,fr2,fr2 ; M2
mcpli fr4,#1,fr6 ; M2 -- error
mqaddhss.p fr0,fr2,fr2 ; M2
mmulhu fr4,fr6,acc8 ; M3 -- error
mqaddhss.p fr0,fr2,fr2 ; M2
mqmulhu fr4,fr6,acc8 ; M4 -- error
mqaddhss.p fr0,fr2,fr2 ; M2
mcuti acc8,#2,fr8 ; M5 -- error
mqaddhss.p fr0,fr2,fr2 ; M2
mdcutssi acc8,#2,fr8 ; M6 -- error
; M-3 first
mwtacc.p fr0,acc0 ; M3
mpackh fr4,fr5,fr6 ; M1 -- ok
mwtacc.p fr0,acc0 ; M3
mcpli fr4,#1,fr6 ; M2 -- error
mwtacc.p fr0,acc0 ; M3
mmulhu fr4,fr6,acc8 ; M3 -- ok
mwtacc.p fr0,acc0 ; M3
mqmulhu fr4,fr6,acc8 ; M4 -- error
mwtacc.p fr0,acc0 ; M3
mcuti acc8,#2,fr8 ; M5 -- ok
mwtacc.p fr0,acc0 ; M3
mdcutssi acc8,#2,fr8 ; M6 -- error
; M-4 first
mqcpxrs.p fr0,fr2,acc0 ; M4
mpackh fr4,fr5,fr6 ; M1 -- error
mqcpxrs.p fr0,fr2,acc0 ; M4
mcpli fr4,#1,fr6 ; M2 -- error
mqcpxrs.p fr0,fr2,acc0 ; M4
mmulhu fr4,fr6,acc8 ; M3 -- error
mqcpxrs.p fr0,fr2,acc0 ; M4
mqmulhu fr4,fr6,acc8 ; M4 -- error
mqcpxrs.p fr0,fr2,acc0 ; M4
mcuti acc8,#2,fr8 ; M5 -- ok
mqcpxrs.p fr0,fr2,acc0 ; M4
mdcutssi acc8,#2,fr8 ; M6 -- ok
; M-5 first
mrdacc.p acc0,fr0 ; M5
mpackh fr4,fr5,fr6 ; M1 -- ok
mrdacc.p acc0,fr0 ; M5
mcpli fr4,#1,fr6 ; M2 -- error
mrdacc.p acc0,fr0 ; M5
mmulhu fr4,fr6,acc8 ; M3 -- ok
mrdacc.p acc0,fr0 ; M5
mqmulhu fr4,fr6,acc8 ; M4 -- error
mrdacc.p acc0,fr0 ; M5
mcuti acc8,#2,fr8 ; M5 -- ok
mrdacc.p acc0,fr0 ; M5
mdcutssi acc8,#2,fr8 ; M6 -- error
; M-6 first
mdcutssi.p acc0,#3,fr0 ; M6
mpackh fr4,fr5,fr6 ; M1 -- error
mdcutssi.p acc0,#3,fr0 ; M6
mcpli fr4,#1,fr6 ; M2 -- error
mdcutssi.p acc0,#3,fr0 ; M6
mmulhu fr4,fr6,acc8 ; M3 -- error
mdcutssi.p acc0,#3,fr0 ; M6
mqmulhu fr4,fr6,acc8 ; M4 -- error
mdcutssi.p acc0,#3,fr0 ; M6
mcuti acc8,#2,fr8 ; M5 -- error
mdcutssi.p acc0,#3,fr0 ; M6
mdcutssi acc8,#2,fr8 ; M6 -- error

107
gas/testsuite/gas/frv/fr450-spr.d Normal file
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@ -0,0 +1,107 @@
#as: -mcpu=fr450
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
.* <\.text>:
.*: 80 0c 01 84 movgs gr4,psr
.*: 80 0c 11 84 movgs gr4,pcsr
.*: 80 0c 21 84 movgs gr4,bpcsr
.*: 80 0c 31 84 movgs gr4,tbr
.*: 80 0c 41 84 movgs gr4,bpsr
.*: 80 0d 01 84 movgs gr4,hsr0
.*: 88 0c 01 84 movgs gr4,ccr
.*: 88 0c 71 84 movgs gr4,cccr
.*: 88 0d 01 84 movgs gr4,lr
.*: 88 0d 11 84 movgs gr4,lcr
.*: 88 0d 81 84 movgs gr4,iacc0h
.*: 88 0d 91 84 movgs gr4,iacc0l
.*: 88 0e 01 84 movgs gr4,isr
.*: 90 0c 01 84 movgs gr4,epcr0
.*: 92 0c 01 84 movgs gr4,esr0
.*: 92 0c e1 84 movgs gr4,esr14
.*: 92 0c f1 84 movgs gr4,esr15
.*: 94 0e 11 84 movgs gr4,esfr1
.*: 9a 0c 01 84 movgs gr4,scr0
.*: 9a 0c 11 84 movgs gr4,scr1
.*: 9a 0c 21 84 movgs gr4,scr2
.*: 9a 0c 31 84 movgs gr4,scr3
.*: a8 0c 01 84 movgs gr4,msr0
.*: a8 0c 11 84 movgs gr4,msr1
.*: b0 0c 01 84 movgs gr4,ear0
.*: b0 0c f1 84 movgs gr4,ear15
.*: b4 0c 01 84 movgs gr4,iamlr0
.*: b4 0c 11 84 movgs gr4,iamlr1
.*: b4 0c 21 84 movgs gr4,iamlr2
.*: b4 0c 31 84 movgs gr4,iamlr3
.*: b4 0c 41 84 movgs gr4,iamlr4
.*: b4 0c 51 84 movgs gr4,iamlr5
.*: b4 0c 61 84 movgs gr4,iamlr6
.*: b4 0c 71 84 movgs gr4,iamlr7
.*: b6 0c 01 84 movgs gr4,iampr0
.*: b6 0c 11 84 movgs gr4,iampr1
.*: b6 0c 21 84 movgs gr4,iampr2
.*: b6 0c 31 84 movgs gr4,iampr3
.*: b6 0c 41 84 movgs gr4,iampr4
.*: b6 0c 51 84 movgs gr4,iampr5
.*: b6 0c 61 84 movgs gr4,iampr6
.*: b6 0c 71 84 movgs gr4,iampr7
.*: b8 0c 01 84 movgs gr4,damlr0
.*: b8 0c 11 84 movgs gr4,damlr1
.*: b8 0c 21 84 movgs gr4,damlr2
.*: b8 0c 31 84 movgs gr4,damlr3
.*: b8 0c 41 84 movgs gr4,damlr4
.*: b8 0c 51 84 movgs gr4,damlr5
.*: b8 0c 61 84 movgs gr4,damlr6
.*: b8 0c 71 84 movgs gr4,damlr7
.*: b8 0c 81 84 movgs gr4,damlr8
.*: b8 0c 91 84 movgs gr4,damlr9
.*: b8 0c a1 84 movgs gr4,damlr10
.*: b8 0c b1 84 movgs gr4,damlr11
.*: ba 0c 01 84 movgs gr4,dampr0
.*: ba 0c 11 84 movgs gr4,dampr1
.*: ba 0c 21 84 movgs gr4,dampr2
.*: ba 0c 31 84 movgs gr4,dampr3
.*: ba 0c 41 84 movgs gr4,dampr4
.*: ba 0c 51 84 movgs gr4,dampr5
.*: ba 0c 61 84 movgs gr4,dampr6
.*: ba 0c 71 84 movgs gr4,dampr7
.*: ba 0c 81 84 movgs gr4,dampr8
.*: ba 0c 91 84 movgs gr4,dampr9
.*: ba 0c a1 84 movgs gr4,dampr10
.*: ba 0c b1 84 movgs gr4,dampr11
.*: bc 0c 01 84 movgs gr4,amcr
.*: bc 0c 51 84 movgs gr4,iamvr1
.*: bc 0c 71 84 movgs gr4,damvr1
.*: bc 0d 01 84 movgs gr4,cxnr
.*: bc 0d 11 84 movgs gr4,ttbr
.*: bc 0d 21 84 movgs gr4,tplr
.*: bc 0d 31 84 movgs gr4,tppr
.*: bc 0d 41 84 movgs gr4,tpxr
.*: bc 0e 01 84 movgs gr4,timerh
.*: bc 0e 11 84 movgs gr4,timerl
.*: bc 0e 21 84 movgs gr4,timerd
.*: c0 0c 01 84 movgs gr4,dcr
.*: c0 0c 11 84 movgs gr4,brr
.*: c0 0c 21 84 movgs gr4,nmar
.*: c0 0c 31 84 movgs gr4,btbr
.*: c0 0c 41 84 movgs gr4,ibar0
.*: c0 0c 51 84 movgs gr4,ibar1
.*: c0 0c 61 84 movgs gr4,ibar2
.*: c0 0c 71 84 movgs gr4,ibar3
.*: c0 0c 81 84 movgs gr4,dbar0
.*: c0 0c 91 84 movgs gr4,dbar1
.*: c0 0c a1 84 movgs gr4,dbar2
.*: c0 0c b1 84 movgs gr4,dbar3
.*: c0 0c c1 84 movgs gr4,dbdr00
.*: c0 0c d1 84 movgs gr4,dbdr01
.*: c0 0c e1 84 movgs gr4,dbdr02
.*: c0 0c f1 84 movgs gr4,dbdr03
.*: c0 0d 01 84 movgs gr4,dbdr10
.*: c0 0d 11 84 movgs gr4,dbdr11
.*: c0 0d c1 84 movgs gr4,dbmr00
.*: c0 0d d1 84 movgs gr4,dbmr01
.*: c0 0e 01 84 movgs gr4,dbmr10
.*: c0 0e 11 84 movgs gr4,dbmr11

99
gas/testsuite/gas/frv/fr450-spr.s Normal file
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@ -0,0 +1,99 @@
movgs gr4, psr ; 0x000 00000
movgs gr4, pcsr ; 0x001 00001
movgs gr4, bpcsr ; 0x002 00002
movgs gr4, tbr ; 0x003 00003
movgs gr4, bpsr ; 0x004 00004
movgs gr4, hsr0 ; 0x010 00020
movgs gr4, ccr ; 0x100 00400
movgs gr4, cccr ; 0x107 00407
movgs gr4, lr ; 0x110 00420
movgs gr4, lcr ; 0x111 00421
movgs gr4, iacc0h ; 0x118 00430
movgs gr4, iacc0l ; 0x119 00431
movgs gr4, isr ; 0x120 00440
movgs gr4, epcr0 ; 0x200 01000
movgs gr4, esr0 ; 0x240 01100
movgs gr4, esr14 ; 0x24e 01116
movgs gr4, esr15 ; 0x24f 01117
movgs gr4, esfr1 ; 0x2a1 01241
movgs gr4, scr0 ; 0x340 01500
movgs gr4, scr1 ; 0x341 01501
movgs gr4, scr2 ; 0x342 01502
movgs gr4, scr3 ; 0x343 01503
movgs gr4, msr0 ; 0x500 02400
movgs gr4, msr1 ; 0x501 02401
movgs gr4, ear0 ; 0x600 03000
movgs gr4, ear15 ; 0x60f 03017
movgs gr4, iamlr0 ; 0x680 03200
movgs gr4, iamlr1 ; 0x681 03201
movgs gr4, iamlr2 ; 0x682 03202
movgs gr4, iamlr3 ; 0x683 03203
movgs gr4, iamlr4 ; 0x684 03204
movgs gr4, iamlr5 ; 0x685 03205
movgs gr4, iamlr6 ; 0x686 03206
movgs gr4, iamlr7 ; 0x687 03207
movgs gr4, iampr0 ; 0x6c0 03300
movgs gr4, iampr1 ; 0x6c1 03301
movgs gr4, iampr2 ; 0x6c2 03302
movgs gr4, iampr3 ; 0x6c3 03303
movgs gr4, iampr4 ; 0x6c4 03304
movgs gr4, iampr5 ; 0x6c5 03305
movgs gr4, iampr6 ; 0x6c6 03306
movgs gr4, iampr7 ; 0x6c7 03307
movgs gr4, damlr0 ; 0x700 03400
movgs gr4, damlr1 ; 0x701 03401
movgs gr4, damlr2 ; 0x702 03402
movgs gr4, damlr3 ; 0x703 03403
movgs gr4, damlr4 ; 0x704 03404
movgs gr4, damlr5 ; 0x705 03405
movgs gr4, damlr6 ; 0x706 03406
movgs gr4, damlr7 ; 0x707 03407
movgs gr4, damlr8 ; 0x708 03410
movgs gr4, damlr9 ; 0x709 03411
movgs gr4, damlr10 ; 0x70a 03412
movgs gr4, damlr11 ; 0x70b 03413
movgs gr4, dampr0 ; 0x740 03500
movgs gr4, dampr1 ; 0x741 03501
movgs gr4, dampr2 ; 0x742 03502
movgs gr4, dampr3 ; 0x743 03503
movgs gr4, dampr4 ; 0x744 03504
movgs gr4, dampr5 ; 0x745 03505
movgs gr4, dampr6 ; 0x746 03506
movgs gr4, dampr7 ; 0x747 03507
movgs gr4, dampr8 ; 0x748 03510
movgs gr4, dampr9 ; 0x749 03511
movgs gr4, dampr10 ; 0x74a 03512
movgs gr4, dampr11 ; 0x74b 03513
movgs gr4, amcr ; 0x780 03600
movgs gr4, iamvr1 ; 0x785 03605
movgs gr4, damvr1 ; 0x787 03607
movgs gr4, cxnr ; 0x790 03620
movgs gr4, ttbr ; 0x791 03621
movgs gr4, tplr ; 0x792 03622
movgs gr4, tppr ; 0x793 03623
movgs gr4, tpxr ; 0x794 03624
movgs gr4, timerh ; 0x7a0 03640
movgs gr4, timerl ; 0x7a1 03641
movgs gr4, timerd ; 0x7a2 03642
movgs gr4, dcr ; 0x800 04000
movgs gr4, brr ; 0x801 04001
movgs gr4, nmar ; 0x802 04002
movgs gr4, btbr ; 0x803 04003
movgs gr4, ibar0 ; 0x804 04004
movgs gr4, ibar1 ; 0x805 04005
movgs gr4, ibar2 ; 0x806 04006
movgs gr4, ibar3 ; 0x807 04007
movgs gr4, dbar0 ; 0x808 04010
movgs gr4, dbar1 ; 0x809 04011
movgs gr4, dbar2 ; 0x80A 04012
movgs gr4, dbar3 ; 0x80B 04013
movgs gr4, dbdr00 ; 0x80C 04014
movgs gr4, dbdr01 ; 0x80D 04015
movgs gr4, dbdr02 ; 0x80E 04016
movgs gr4, dbdr03 ; 0x80F 04017
movgs gr4, dbdr10 ; 0x810 04020
movgs gr4, dbdr11 ; 0x811 04021
movgs gr4, dbmr00 ; 0x81C 04034
movgs gr4, dbmr01 ; 0x81D 04035
movgs gr4, dbmr10 ; 0x820 04040
movgs gr4, dbmr11 ; 0x821 04041

4
include/elf/ChangeLog
View file

@ -1,3 +1,7 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define.
2004-01-28 Roland McGrath <roland@redhat.com>
* common.h (AT_SECURE): New macro.

2
include/elf/frv.h
View file

@ -91,6 +91,8 @@ END_RELOC_NUMBERS(R_FRV_max)
#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */
#define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */
#define EF_FRV_CPU_FR550 0x06000000 /* FRV550 */
#define EF_FRV_CPU_FR405 0x07000000
#define EF_FRV_CPU_FR450 0x08000000
/* Mask of PIC related bits */
#define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC \

5
ld/testsuite/ChangeLog
View file

@ -1,3 +1,8 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* ld-frv/fr450-link[abc].s, fr450-link.d: New test.
* ld-frv/frv.exp: New harness.
2004-02-24 Alexandre Oliva <aoliva@redhat.com>
* ld-frv/fdpic-pie-2.d: Adjust for decay of FUNCDESC relocs that

11
ld/testsuite/ld-frv/fr450-link.d Normal file
View file

@ -0,0 +1,11 @@
#source: fr450-linka.s -mcpu=fr400
#source: fr450-linkb.s -mcpu=fr405
#source: fr450-linkc.s -mcpu=fr450
#source: fr450-linkb.s -mcpu=fr405
#source: fr450-linka.s -mcpu=fr400
#ld: -r
#objdump: -p
.*: file format elf32-frv
private flags = 0x8000000: -mcpu=fr450

1
ld/testsuite/ld-frv/fr450-linka.s Normal file
View file

@ -0,0 +1 @@
nop

1
ld/testsuite/ld-frv/fr450-linkb.s Normal file
View file

@ -0,0 +1 @@
nop

1
ld/testsuite/ld-frv/fr450-linkc.s Normal file
View file

@ -0,0 +1 @@
nop

3
ld/testsuite/ld-frv/frv-elf.exp Normal file
View file

@ -0,0 +1,3 @@
if [istarget frv*-*-*] {
run_dump_test "fr450-link"
}

10
opcodes/ChangeLog
View file

@ -1,3 +1,13 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv-asm.c: Regenerate.
* frv-desc.c: Regenerate.
* frv-desc.h: Regenerate.
* frv-dis.c: Regenerate.
* frv-ibld.c: Regenerate.
* frv-opc.c: Regenerate.
* frv-opc.h: Regenerate.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* frv-desc.c, frv-opc.c: Regenerate.

15
opcodes/frv-asm.c
View file

@ -860,6 +860,21 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
case FRV_OPERAND_LI :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, &fields->f_LI);
break;
case FRV_OPERAND_LRAD :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAD, &fields->f_LRAD);
break;
case FRV_OPERAND_LRAE :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAE, &fields->f_LRAE);
break;
case FRV_OPERAND_LRAS :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAS, &fields->f_LRAS);
break;
case FRV_OPERAND_TLBPRL :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPRL, &fields->f_TLBPRL);
break;
case FRV_OPERAND_TLBPROPX :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPROPX, &fields->f_TLBPRopx);
break;
case FRV_OPERAND_AE :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, &fields->f_ae);
break;

1583
opcodes/frv-desc.c
View file

File diff suppressed because it is too large Load diff

88
opcodes/frv-desc.h
View file

@ -292,7 +292,8 @@ typedef enum spr_names {
, H_SPR_EIR23 = 663, H_SPR_EIR24 = 664, H_SPR_EIR25 = 665, H_SPR_EIR26 = 666
, H_SPR_EIR27 = 667, H_SPR_EIR28 = 668, H_SPR_EIR29 = 669, H_SPR_EIR30 = 670
, H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672, H_SPR_ESFR1 = 673, H_SPR_SR0 = 768
, H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_FSR0 = 1024
, H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_SCR0 = 832
, H_SPR_SCR1 = 833, H_SPR_SCR2 = 834, H_SPR_SCR3 = 835, H_SPR_FSR0 = 1024
, H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026, H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028
, H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030, H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032
, H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034, H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036
@ -454,19 +455,22 @@ typedef enum spr_names {
, H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912, H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914
, H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916, H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918
, H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920, H_SPR_STBAR = 1921, H_SPR_MMCR = 1922
, H_SPR_DCR = 2048, H_SPR_BRR = 2049, H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052
, H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056
, H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060
, H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064
, H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068
, H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072
, H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076
, H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080
, H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084
, H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088
, H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092
, H_SPR_CPCR = 2093, H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097
, H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
, H_SPR_IAMVR1 = 1925, H_SPR_DAMVR1 = 1927, H_SPR_CXNR = 1936, H_SPR_TTBR = 1937
, H_SPR_TPLR = 1938, H_SPR_TPPR = 1939, H_SPR_TPXR = 1940, H_SPR_TIMERH = 1952
, H_SPR_TIMERL = 1953, H_SPR_TIMERD = 1954, H_SPR_DCR = 2048, H_SPR_BRR = 2049
, H_SPR_NMAR = 2050, H_SPR_BTBR = 2051, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053
, H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057
, H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061
, H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065
, H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069
, H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073
, H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077
, H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081
, H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085
, H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089
, H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093
, H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098
, H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
} SPR_NAMES;
/* Enum declaration for . */
@ -535,7 +539,8 @@ typedef enum cccr_names {
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
MACH_BASE, MACH_FRV, MACH_FR550, MACH_FR500
, MACH_FR400, MACH_TOMCAT, MACH_SIMPLE, MACH_MAX
, MACH_FR450, MACH_FR400, MACH_TOMCAT, MACH_SIMPLE
, MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
@ -551,7 +556,7 @@ typedef enum unit_attr {
, UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1
, UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_IACC
, UNIT_LOAD, UNIT_STORE, UNIT_SCAN, UNIT_DCPL
, UNIT_MDUALACC, UNIT_MCLRACC_1, UNIT_NUM_UNITS
, UNIT_MDUALACC, UNIT_MDCUTSSI, UNIT_MCLRACC_1, UNIT_NUM_UNITS
} UNIT_ATTR;
/* Enum declaration for fr400 major insn categories. */
@ -562,6 +567,15 @@ typedef enum fr400_major_attr {
, FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2
} FR400_MAJOR_ATTR;
/* Enum declaration for fr450 major insn categories. */
typedef enum fr450_major_attr {
FR450_MAJOR_NONE, FR450_MAJOR_I_1, FR450_MAJOR_I_2, FR450_MAJOR_I_3
, FR450_MAJOR_I_4, FR450_MAJOR_I_5, FR450_MAJOR_B_1, FR450_MAJOR_B_2
, FR450_MAJOR_B_3, FR450_MAJOR_B_4, FR450_MAJOR_B_5, FR450_MAJOR_B_6
, FR450_MAJOR_C_1, FR450_MAJOR_C_2, FR450_MAJOR_M_1, FR450_MAJOR_M_2
, FR450_MAJOR_M_3, FR450_MAJOR_M_4, FR450_MAJOR_M_5, FR450_MAJOR_M_6
} FR450_MAJOR_ATTR;
/* Enum declaration for fr500 major insn categories. */
typedef enum fr500_major_attr {
FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3
@ -623,15 +637,17 @@ typedef enum ifield_type {
, FRV_F_CCOND, FRV_F_HINT, FRV_F_LI, FRV_F_LOCK
, FRV_F_DEBUG, FRV_F_A, FRV_F_AE, FRV_F_SPR_H
, FRV_F_SPR_L, FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6
, FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL
, FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL
, FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL
, FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL
, FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL
, FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4
, FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8
, FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LI_OFF
, FRV_F_LI_ON, FRV_F_MAX
, FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_LRAE, FRV_F_LRAD
, FRV_F_LRAS, FRV_F_TLBPROPX, FRV_F_TLBPRL, FRV_F_ICCI_1_NULL
, FRV_F_ICCI_2_NULL, FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL
, FRV_F_FCCI_3_NULL, FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL
, FRV_F_GRK_NULL, FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL
, FRV_F_RD_NULL, FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL
, FRV_F_LABEL16_NULL, FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3
, FRV_F_MISC_NULL_4, FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7
, FRV_F_MISC_NULL_8, FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11
, FRV_F_LRA_NULL, FRV_F_TLBPR_NULL, FRV_F_LI_OFF, FRV_F_LI_ON
, FRV_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) FRV_F_MAX)
@ -696,16 +712,17 @@ typedef enum cgen_operand_type {
, FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND
, FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI
, FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16
, FRV_OPERAND_LABEL24, FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN
, FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12
, FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16
, FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS
, FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA
, FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
, FRV_OPERAND_LABEL24, FRV_OPERAND_LRAE, FRV_OPERAND_LRAD, FRV_OPERAND_LRAS
, FRV_OPERAND_TLBPROPX, FRV_OPERAND_TLBPRL, FRV_OPERAND_A0, FRV_OPERAND_A1
, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12
, FRV_OPERAND_S12, FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16
, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S
, FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET
, FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 81
#define MAX_OPERANDS 86
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
@ -717,9 +734,10 @@ typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING
, CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS
, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR
, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR, CGEN_INSN_END_NBOOLS
, CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_AUDIO
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT
, CGEN_INSN_FR400_MAJOR, CGEN_INSN_FR450_MAJOR, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR
, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */

15
opcodes/frv-dis.c
View file

@ -289,6 +289,21 @@ frv_cgen_print_operand (cd, opindex, xinfo, fields, attrs, pc, length)
case FRV_OPERAND_LI :
print_normal (cd, info, fields->f_LI, 0, pc, length);
break;
case FRV_OPERAND_LRAD :
print_normal (cd, info, fields->f_LRAD, 0, pc, length);
break;
case FRV_OPERAND_LRAE :
print_normal (cd, info, fields->f_LRAE, 0, pc, length);
break;
case FRV_OPERAND_LRAS :
print_normal (cd, info, fields->f_LRAS, 0, pc, length);
break;
case FRV_OPERAND_TLBPRL :
print_normal (cd, info, fields->f_TLBPRL, 0, pc, length);
break;
case FRV_OPERAND_TLBPROPX :
print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length);
break;
case FRV_OPERAND_AE :
print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;

90
opcodes/frv-ibld.c
View file

@ -713,6 +713,21 @@ frv_cgen_insert_operand (cd, opindex, fields, buffer, pc)
case FRV_OPERAND_LI :
errmsg = insert_normal (cd, fields->f_LI, 0, 0, 25, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_LRAD :
errmsg = insert_normal (cd, fields->f_LRAD, 0, 0, 4, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_LRAE :
errmsg = insert_normal (cd, fields->f_LRAE, 0, 0, 5, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_LRAS :
errmsg = insert_normal (cd, fields->f_LRAS, 0, 0, 3, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_TLBPRL :
errmsg = insert_normal (cd, fields->f_TLBPRL, 0, 0, 25, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_TLBPROPX :
errmsg = insert_normal (cd, fields->f_TLBPRopx, 0, 0, 28, 3, 32, total_length, buffer);
break;
case FRV_OPERAND_AE :
errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer);
break;
@ -1016,6 +1031,21 @@ frv_cgen_extract_operand (cd, opindex, ex_info, insn_value, fields, pc)
case FRV_OPERAND_LI :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI);
break;
case FRV_OPERAND_LRAD :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_LRAD);
break;
case FRV_OPERAND_LRAE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_LRAE);
break;
case FRV_OPERAND_LRAS :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 3, 1, 32, total_length, pc, & fields->f_LRAS);
break;
case FRV_OPERAND_TLBPRL :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_TLBPRL);
break;
case FRV_OPERAND_TLBPROPX :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_TLBPRopx);
break;
case FRV_OPERAND_AE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae);
break;
@ -1302,6 +1332,21 @@ frv_cgen_get_int_operand (cd, opindex, fields)
case FRV_OPERAND_LI :
value = fields->f_LI;
break;
case FRV_OPERAND_LRAD :
value = fields->f_LRAD;
break;
case FRV_OPERAND_LRAE :
value = fields->f_LRAE;
break;
case FRV_OPERAND_LRAS :
value = fields->f_LRAS;
break;
case FRV_OPERAND_TLBPRL :
value = fields->f_TLBPRL;
break;
case FRV_OPERAND_TLBPROPX :
value = fields->f_TLBPRopx;
break;
case FRV_OPERAND_AE :
value = fields->f_ae;
break;
@ -1539,6 +1584,21 @@ frv_cgen_get_vma_operand (cd, opindex, fields)
case FRV_OPERAND_LI :
value = fields->f_LI;
break;
case FRV_OPERAND_LRAD :
value = fields->f_LRAD;
break;
case FRV_OPERAND_LRAE :
value = fields->f_LRAE;
break;
case FRV_OPERAND_LRAS :
value = fields->f_LRAS;
break;
case FRV_OPERAND_TLBPRL :
value = fields->f_TLBPRL;
break;
case FRV_OPERAND_TLBPROPX :
value = fields->f_TLBPRopx;
break;
case FRV_OPERAND_AE :
value = fields->f_ae;
break;
@ -1785,6 +1845,21 @@ frv_cgen_set_int_operand (cd, opindex, fields, value)
case FRV_OPERAND_LI :
fields->f_LI = value;
break;
case FRV_OPERAND_LRAD :
fields->f_LRAD = value;
break;
case FRV_OPERAND_LRAE :
fields->f_LRAE = value;
break;
case FRV_OPERAND_LRAS :
fields->f_LRAS = value;
break;
case FRV_OPERAND_TLBPRL :
fields->f_TLBPRL = value;
break;
case FRV_OPERAND_TLBPROPX :
fields->f_TLBPRopx = value;
break;
case FRV_OPERAND_AE :
fields->f_ae = value;
break;
@ -2019,6 +2094,21 @@ frv_cgen_set_vma_operand (cd, opindex, fields, value)
case FRV_OPERAND_LI :
fields->f_LI = value;
break;
case FRV_OPERAND_LRAD :
fields->f_LRAD = value;
break;
case FRV_OPERAND_LRAE :
fields->f_LRAE = value;
break;
case FRV_OPERAND_LRAS :
fields->f_LRAS = value;
break;
case FRV_OPERAND_TLBPRL :
fields->f_TLBPRL = value;
break;
case FRV_OPERAND_TLBPROPX :
fields->f_TLBPRopx = value;
break;
case FRV_OPERAND_AE :
fields->f_ae = value;
break;

173
opcodes/frv-opc.c
View file

@ -44,6 +44,8 @@ static int find_major_in_vliw
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr400_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr450_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr500_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr550_check_insn_major_constraints
@ -60,6 +62,10 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
return 1; /* is a branch */
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
return 1; /* is a branch */
break;
default:
if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
return 1; /* is a branch */
@ -75,6 +81,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
switch (mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
return 0; /* No float insns */
default:
if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
@ -94,6 +101,10 @@ frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach)
if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
return 1; /* is a media insn */
break;
case bfd_mach_fr450:
if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
return 1; /* is a media insn */
break;
default:
if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
return 1; /* is a media insn */
@ -109,6 +120,9 @@ frv_is_branch_insn (const CGEN_INSN *insn)
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
@ -122,6 +136,9 @@ frv_is_float_insn (const CGEN_INSN *insn)
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
@ -135,6 +152,9 @@ frv_is_media_insn (const CGEN_INSN *insn)
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
bfd_mach_fr450))
return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
@ -245,6 +265,42 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] =
/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
};
/* Some insns are assigned specialized implementation units which map to
different actual implementation units on different machines. These
tables perform that mapping. */
static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
{
/* unit in insn actual unit */
/* NIL */ UNIT_NIL,
/* I0 */ UNIT_I0,
/* I1 */ UNIT_I1,
/* I01 */ UNIT_I01,
/* I2 */ UNIT_NIL, /* no I2 or I3 unit */
/* I3 */ UNIT_NIL,
/* IALL */ UNIT_I01, /* only I0 and I1 units */
/* FM0 */ UNIT_FM0,
/* FM1 */ UNIT_FM1,
/* FM01 */ UNIT_FM01,
/* FM2 */ UNIT_NIL, /* no F2 or M2 units */
/* FM3 */ UNIT_NIL, /* no F3 or M3 units */
/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
/* B0 */ UNIT_B0, /* branches only in B0 unit. */
/* B1 */ UNIT_B0,
/* B01 */ UNIT_B0,
/* C */ UNIT_C,
/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */
/* LOAD */ UNIT_I0, /* load only in I0 unit. */
/* STORE */ UNIT_I0, /* store only in I0 unit. */
/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */
/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
};
@ -276,6 +332,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] =
/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
@ -307,6 +364,7 @@ static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] =
/* SCAN */ UNIT_IALL, /* scan in any integer unit. */
/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
/* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */
/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
@ -324,6 +382,10 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags)
vliw->current_vliw = fr400_allowed_vliw;
vliw->unit_mapping = fr400_unit_mapping;
break;
case bfd_mach_fr450:
vliw->current_vliw = fr400_allowed_vliw;
vliw->unit_mapping = fr450_unit_mapping;
break;
case bfd_mach_fr550:
vliw->current_vliw = fr550_allowed_vliw;
vliw->unit_mapping = fr550_unit_mapping;
@ -461,6 +523,43 @@ fr400_check_insn_major_constraints (
return 1;
}
static int
fr450_check_insn_major_constraints (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
)
{
CGEN_ATTR_VALUE_TYPE other_major;
/* Our caller guarantees there's at least one other instruction. */
other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
/* (M4, M5) and (M4, M6) are allowed. */
if (other_major == FR450_MAJOR_M_4)
if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
return 1;
/* Otherwise, instructions in even-numbered media categories cannot be
executed in parallel with other media instructions. */
switch (major)
{
case FR450_MAJOR_M_2:
case FR450_MAJOR_M_4:
case FR450_MAJOR_M_6:
return !(other_major >= FR450_MAJOR_M_1
&& other_major <= FR450_MAJOR_M_6);
case FR450_MAJOR_M_1:
case FR450_MAJOR_M_3:
case FR450_MAJOR_M_5:
return !(other_major == FR450_MAJOR_M_2
|| other_major == FR450_MAJOR_M_4
|| other_major == FR450_MAJOR_M_6);
default:
return 1;
}
}
static int
find_unit_in_vliw (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
@ -698,6 +797,9 @@ check_insn_major_constraints (
case bfd_mach_fr400:
rc = fr400_check_insn_major_constraints (vliw, major);
break;
case bfd_mach_fr450:
rc = fr450_check_insn_major_constraints (vliw, major);
break;
case bfd_mach_fr550:
rc = fr550_check_insn_major_constraints (vliw, major, insn);
break;
@ -738,6 +840,9 @@ frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn)
case bfd_mach_fr400:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
break;
case bfd_mach_fr450:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR);
break;
case bfd_mach_fr550:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR);
break;
@ -1151,6 +1256,14 @@ static const CGEN_IFMT ifmt_bar = {
32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } }
};
static const CGEN_IFMT ifmt_lrai = {
32, 32, 0x1fc0fc7, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_LRAE) }, { F (F_LRAD) }, { F (F_LRAS) }, { F (F_LRA_NULL) }, { 0 } }
};
static const CGEN_IFMT ifmt_tlbpr = {
32, 32, 0x61fc0fc0, { { F (F_PACK) }, { F (F_TLBPR_NULL) }, { F (F_TLBPROPX) }, { F (F_TLBPRL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
};
static const CGEN_IFMT ifmt_cop1 = {
32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } }
};
@ -1299,6 +1412,10 @@ static const CGEN_IFMT ifmt_cmqaddhss = {
32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
};
static const CGEN_IFMT ifmt_mqsllhi = {
32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } }
};
static const CGEN_IFMT ifmt_maddaccs = {
32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } }
};
@ -4558,6 +4675,24 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, OP (PACK), 0 } },
& ifmt_bar, { 0xc0fc0 }
},
/* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } },
& ifmt_lrai, { 0xc0800 }
},
/* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } },
& ifmt_lrai, { 0xc0840 }
},
/* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (TLBPROPX), ',', OP (TLBPRL), 0 } },
& ifmt_tlbpr, { 0xc0900 }
},
/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
{
{ 0, 0, 0, 0 },
@ -5440,6 +5575,30 @@ static const CGEN_OPCODE frv_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
& ifmt_cmqaddhss, { 0x1cc00c0 }
},
/* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
& ifmt_mqsaths, { 0x1e00400 }
},
/* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
& ifmt_mqsaths, { 0x1e00500 }
},
/* mqsllhi$pack $FRintieven,$u6,$FRintkeven */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } },
& ifmt_mqsllhi, { 0x1e00440 }
},
/* mqsrahi$pack $FRintieven,$u6,$FRintkeven */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } },
& ifmt_mqsllhi, { 0x1e004c0 }
},
/* maddaccs$pack $ACC40Si,$ACC40Sk */
{
{ 0, 0, 0, 0 },
@ -5908,37 +6067,37 @@ static const CGEN_IBASE frv_cgen_macro_insn_table[] =
/* nop$pack */
{
-1, "nop", "nop", 32,
{ 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
{ 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* ret$pack */
{
-1, "ret", "ret", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
},
/* cmp$pack $GRi,$GRj,$ICCi_1 */
{
-1, "cmp", "cmp", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* cmpi$pack $GRi,$s10,$ICCi_1 */
{
-1, "cmpi", "cmpi", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* ccmp$pack $GRi,$GRj,$CCi,$cond */
{
-1, "ccmp", "ccmp", 32,
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* mov$pack $GRi,$GRk */
{
-1, "mov", "mov", 32,
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* cmov$pack $GRi,$GRk,$CCi,$cond */
{
-1, "cmov", "cmov", 32,
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
{ 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
};

118
opcodes/frv-opc.h
View file

@ -194,61 +194,62 @@ typedef enum cgen_insn_type {
, FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF
, FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI
, FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL
, FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1
, FRV_INSN_COP2, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA
, FRV_INSN_CLRFA, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA
, FRV_INSN_COMMITFA, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD
, FRV_INSN_FDTOI, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS
, FRV_INSN_NFDSTOI, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS
, FRV_INSN_NFSTOI, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS
, FRV_INSN_CFMOVS, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS
, FRV_INSN_CFNEGS, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS
, FRV_INSN_CFABSS, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS
, FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS
, FRV_INSN_FSUBS, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD
, FRV_INSN_FSUBD, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS
, FRV_INSN_CFSUBS, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS
, FRV_INSN_NFSUBS, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS
, FRV_INSN_FCMPD, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS
, FRV_INSN_FMSUBS, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS
, FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS
, FRV_INSN_NFMSUBS, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS
, FRV_INSN_FDMSS, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS
, FRV_INSN_CFMSS, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS
, FRV_INSN_NFMSS, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS
, FRV_INSN_FDDIVS, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS
, FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS
, FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS
, FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH
, FRV_INSN_MAND, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND
, FRV_INSN_CMOR, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT
, FRV_INSN_MROTLI, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI
, FRV_INSN_MCUT, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI
, FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI
, FRV_INSN_MSRAHI, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI
, FRV_INSN_MSATHS, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH
, FRV_INSN_MCMPUH, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS
, FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS
, FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS
, FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS
, FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS
, FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS
, FRV_INSN_MMULHS, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU
, FRV_INSN_CMMULHS, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU
, FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU
, FRV_INSN_MMACHS, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU
, FRV_INSN_CMMACHS, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU
, FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS
, FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS
, FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS
, FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS
, FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD
, FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH
, FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB
, FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP
, FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG
, FRV_INSN_MWTACC, FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2
, FRV_INSN_FNOP
, FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_LRAI
, FRV_INSN_LRAD, FRV_INSN_TLBPR, FRV_INSN_COP1, FRV_INSN_COP2
, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA
, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA
, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI
, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI
, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI
, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS
, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS
, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS
, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD
, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS
, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD
, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS
, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS
, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD
, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS
, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS
, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS
, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS
, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS
, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS
, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS
, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS
, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS
, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS
, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND
, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR
, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI
, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT
, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI
, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI
, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS
, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH
, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS
, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS
, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS
, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS
, FRV_INSN_CMQSUBHUS, FRV_INSN_MQLCLRHS, FRV_INSN_MQLMTHS, FRV_INSN_MQSLLHI
, FRV_INSN_MQSRAHI, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS
, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS
, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS
, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS
, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS
, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS
, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS
, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS
, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU
, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU
, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU
, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD
, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH
, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB
, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0
, FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC
, FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
@ -327,6 +328,11 @@ struct cgen_fields
long f_labelH6;
long f_labelL18;
long f_label24;
long f_LRAE;
long f_LRAD;
long f_LRAS;
long f_TLBPRopx;
long f_TLBPRL;
long f_ICCi_1_null;
long f_ICCi_2_null;
long f_ICCi_3_null;
@ -356,6 +362,8 @@ struct cgen_fields
long f_misc_null_9;
long f_misc_null_10;
long f_misc_null_11;
long f_LRA_null;
long f_TLBPR_null;
long f_LI_off;
long f_LI_on;
};

35
sim/frv/ChangeLog
View file

@ -1,3 +1,38 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* Makefile.in (SIM_OBJS): Add profile-fr450.o.
(profile-fr450.o): New dependency.
(stamp-cpu): Add fr450 to the list of machs.
* sim-frv.h (SPR_IS_ACC): New macro.
(H_SPR_ACC4, H_SPR_ACC63, H_SPR_ACCG4, H_SPR_ACCG63): Delete.
* cache.c (frv_cache_init, non_cache_access): Handle bfd_mach_fr450.
* frv.c (check_register_alignment, check_fr_register_alignment)
(check_memory_alignment, do_media_average): Likewise.
(frvbf_clear_accumulators): Likewise. Use a mask of valid registers
rather than a consecutive range.
* interrupts.c (frv_queue_illegal_instruction_interrupt)
(frv_queue_non_implemented_instruction_interrupt): Handle
bfd_mach_fr450.
* memory.c (check_data_read_address, check_readwrite_address)
(check_insn_read_address, check_write_address): Likewise.
* mloop.in (@cpu@_simulate_insn_prefetch): Likewise.
* profile.c (reset_gr_flags, reset_fr_flags, reset_acc_flags)
(frvbf_model_insn_before, frvbf_model_insn_after): Likewise.
* profile-fr450.c: New file.
* registers.c (fr450_spr): New array.
(frv_register_control_init): Check its size. Use it for fr450.
(frv_check_register_access): Handle bfd_mach_fr450.
(frv_check_spr_read_access): Likewise. Generalize accumulator check.
* traps.c (frv_core_signal, frvbf_media_cr_not_aligned): Likewise.
(frvbf_media_acc_not_aligned): Likewise.
(frvbf_media_register_not_aligned): Likewise.
* arch.c: Regenerate.
* arch.h: Regenerate.
* cpu.h: Regenerate.
* cpuall.h: Regenerate.
* decode.h: Regenerate.
* model.c: Regenerate.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* cache.c (frv_cache_init): Change fr400 cache statistics to match

5
sim/frv/Makefile.in
View file

@ -35,7 +35,7 @@ SIM_OBJS = \
sim-if.o arch.o \
$(FRV_OBJS) \
traps.o interrupts.o memory.o cache.o pipeline.o \
profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \
profile.o profile-fr400.o profile-fr450.o profile-fr500.o profile-fr550.o options.o \
devices.o reset.o registers.o \
$(CONFIG_DEVICES)
@ -80,6 +80,7 @@ reset.o: reset.c $(FRVBF_INCLUDE_DEPS)
registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS)
profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
profile-fr450.o: profile-fr450.c $(FRVBF_INCLUDE_DEPS)
profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS)
sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
@ -121,7 +122,7 @@ arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \
cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
EXTRAFILES="$(CGEN_CPU_SEM)"

3
sim/frv/arch.c
View file

@ -42,6 +42,9 @@ const MACH *sim_machs[] =
#ifdef HAVE_CPU_FRVBF
& fr400_mach,
#endif
#ifdef HAVE_CPU_FRVBF
& fr450_mach,
#endif
#ifdef HAVE_CPU_FRVBF
& simple_mach,
#endif

16
sim/frv/arch.h
View file

@ -30,7 +30,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT
, MODEL_FR400, MODEL_SIMPLE, MODEL_MAX
, MODEL_FR400, MODEL_FR450, MODEL_SIMPLE, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
@ -74,7 +74,19 @@ typedef enum unit_type {
, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE
, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP
, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER
, UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX
, UNIT_FR400_U_EXEC, UNIT_FR450_U_DCUL, UNIT_FR450_U_ICUL, UNIT_FR450_U_DCPL
, UNIT_FR450_U_ICPL, UNIT_FR450_U_DCF, UNIT_FR450_U_DCI, UNIT_FR450_U_ICI
, UNIT_FR450_U_MEMBAR, UNIT_FR450_U_BARRIER, UNIT_FR450_U_MEDIA_DUAL_HTOB, UNIT_FR450_U_MEDIA_DUAL_EXPAND
, UNIT_FR450_U_MEDIA_7, UNIT_FR450_U_MEDIA_6, UNIT_FR450_U_MEDIA_4_MCLRACCA, UNIT_FR450_U_MEDIA_4_ACC_DUAL
, UNIT_FR450_U_MEDIA_4_ACCG, UNIT_FR450_U_MEDIA_4, UNIT_FR450_U_MEDIA_3_QUAD, UNIT_FR450_U_MEDIA_3_DUAL
, UNIT_FR450_U_MEDIA_3, UNIT_FR450_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR450_U_MEDIA_2_ADD_SUB, UNIT_FR450_U_MEDIA_2_ACC_DUAL
, UNIT_FR450_U_MEDIA_2_ACC, UNIT_FR450_U_MEDIA_2_QUAD, UNIT_FR450_U_MEDIA_2, UNIT_FR450_U_MEDIA_HILO
, UNIT_FR450_U_MEDIA_1_QUAD, UNIT_FR450_U_MEDIA_1, UNIT_FR450_U_GR2SPR, UNIT_FR450_U_GR2FR
, UNIT_FR450_U_SPR2GR, UNIT_FR450_U_FR2GR, UNIT_FR450_U_SWAP, UNIT_FR450_U_FR_STORE
, UNIT_FR450_U_FR_LOAD, UNIT_FR450_U_GR_STORE, UNIT_FR450_U_GR_LOAD, UNIT_FR450_U_SET_HILO
, UNIT_FR450_U_CHECK, UNIT_FR450_U_TRAP, UNIT_FR450_U_BRANCH, UNIT_FR450_U_IDIV
, UNIT_FR450_U_IMUL, UNIT_FR450_U_INTEGER, UNIT_FR450_U_EXEC, UNIT_SIMPLE_U_EXEC
, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)

2
sim/frv/cache.c
View file

@ -38,6 +38,7 @@ frv_cache_init (SIM_CPU *cpu, FRV_CACHE *cache)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
if (cache->configured_sets == 0)
cache->configured_sets = 512;
if (cache->configured_ways == 0)
@ -205,6 +206,7 @@ non_cache_access (FRV_CACHE *cache, USI address)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
if (address >= 0xff000000
|| address >= 0xfe000000 && address <= 0xfeffffff)
return 1; /* non-cache access */

91
sim/frv/cpu.h
View file

@ -397,6 +397,19 @@ typedef struct {
DI cur_acc_p4;
} MODEL_FR400_DATA;
typedef struct {
DI prev_fp_load;
DI prev_fr_p4;
DI prev_fr_p6;
DI prev_acc_p2;
DI prev_acc_p4;
DI cur_fp_load;
DI cur_fr_p4;
DI cur_fr_p6;
DI cur_acc_p2;
DI cur_acc_p4;
} MODEL_FR450_DATA;
typedef struct {
int empty;
} MODEL_SIMPLE_DATA;
@ -1261,6 +1274,23 @@ union sem_fields {
unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintk_0;
unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintk_0;
} sfmt_cmaddhss;
struct { /* */
UINT f_FRi;
UINT f_FRk;
UINT f_u6;
unsigned char in_FRintieven;
unsigned char in_FRintkeven;
unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
unsigned char out_FRintieven;
unsigned char out_FRintkeven;
unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
} sfmt_mqsllhi;
struct { /* */
UINT f_FRi;
UINT f_FRj;
@ -3149,6 +3179,50 @@ struct scache {
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_LRAI_VARS \
UINT f_pack; \
UINT f_GRk; \
UINT f_op; \
UINT f_GRi; \
UINT f_ope1; \
UINT f_LRAE; \
UINT f_LRAD; \
UINT f_LRAS; \
UINT f_LRA_null; \
unsigned int length;
#define EXTRACT_IFMT_LRAI_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_LRAE = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
f_LRAD = EXTRACT_LSB0_UINT (insn, 32, 4, 1); \
f_LRAS = EXTRACT_LSB0_UINT (insn, 32, 3, 1); \
f_LRA_null = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \
#define EXTRACT_IFMT_TLBPR_VARS \
UINT f_pack; \
UINT f_TLBPR_null; \
UINT f_TLBPRopx; \
UINT f_TLBPRL; \
UINT f_op; \
UINT f_GRi; \
UINT f_ope1; \
UINT f_GRj; \
unsigned int length;
#define EXTRACT_IFMT_TLBPR_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_TLBPR_null = EXTRACT_LSB0_UINT (insn, 32, 30, 2); \
f_TLBPRopx = EXTRACT_LSB0_UINT (insn, 32, 28, 3); \
f_TLBPRL = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_COP1_VARS \
UINT f_pack; \
UINT f_CPRk; \
@ -3836,6 +3910,23 @@ struct scache {
f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_MQSLLHI_VARS \
UINT f_pack; \
UINT f_FRk; \
UINT f_op; \
UINT f_FRi; \
UINT f_ope1; \
UINT f_u6; \
unsigned int length;
#define EXTRACT_IFMT_MQSLLHI_CODE \
length = 4; \
f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
#define EXTRACT_IFMT_MADDACCS_VARS \
UINT f_pack; \
UINT f_ACC40Sk; \

1
sim/frv/cpuall.h
View file

@ -39,6 +39,7 @@ extern const MACH fr550_mach;
extern const MACH fr500_mach;
extern const MACH tomcat_mach;
extern const MACH fr400_mach;
extern const MACH fr450_mach;
extern const MACH simple_mach;
#ifndef WANT_CPU

69
sim/frv/decode.c
View file

@ -568,6 +568,9 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_DCUL, FRVBF_INSN_DCUL, FRVBF_SFMT_ICUL },
{ FRV_INSN_BAR, FRVBF_INSN_BAR, FRVBF_SFMT_REI },
{ FRV_INSN_MEMBAR, FRVBF_INSN_MEMBAR, FRVBF_SFMT_REI },
{ FRV_INSN_LRAI, FRVBF_INSN_LRAI, FRVBF_SFMT_REI },
{ FRV_INSN_LRAD, FRVBF_INSN_LRAD, FRVBF_SFMT_REI },
{ FRV_INSN_TLBPR, FRVBF_INSN_TLBPR, FRVBF_SFMT_REI },
{ FRV_INSN_COP1, FRVBF_INSN_COP1, FRVBF_SFMT_REI },
{ FRV_INSN_COP2, FRVBF_INSN_COP2, FRVBF_SFMT_REI },
{ FRV_INSN_CLRGR, FRVBF_INSN_CLRGR, FRVBF_SFMT_CLRGR },
@ -715,6 +718,10 @@ static const struct insn_sem frvbf_insn_sem[] =
{ FRV_INSN_CMQADDHUS, FRVBF_INSN_CMQADDHUS, FRVBF_SFMT_CMQADDHSS },
{ FRV_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHSS, FRVBF_SFMT_CMQADDHSS },
{ FRV_INSN_CMQSUBHUS, FRVBF_INSN_CMQSUBHUS, FRVBF_SFMT_CMQADDHSS },
{ FRV_INSN_MQLCLRHS, FRVBF_INSN_MQLCLRHS, FRVBF_SFMT_MQSATHS },
{ FRV_INSN_MQLMTHS, FRVBF_INSN_MQLMTHS, FRVBF_SFMT_MQSATHS },
{ FRV_INSN_MQSLLHI, FRVBF_INSN_MQSLLHI, FRVBF_SFMT_MQSLLHI },
{ FRV_INSN_MQSRAHI, FRVBF_INSN_MQSRAHI, FRVBF_SFMT_MQSLLHI },
{ FRV_INSN_MADDACCS, FRVBF_INSN_MADDACCS, FRVBF_SFMT_MADDACCS },
{ FRV_INSN_MSUBACCS, FRVBF_INSN_MSUBACCS, FRVBF_SFMT_MADDACCS },
{ FRV_INSN_MDADDACCS, FRVBF_INSN_MDADDACCS, FRVBF_SFMT_MDADDACCS },
@ -1004,6 +1011,9 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu;
case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu;
case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu;
case 32 : itype = FRVBF_INSN_LRAI; goto extract_sfmt_rei;
case 33 : itype = FRVBF_INSN_LRAD; goto extract_sfmt_rei;
case 36 : itype = FRVBF_INSN_TLBPR; goto extract_sfmt_rei;
case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc;
case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc;
case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc;
@ -1838,7 +1848,7 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 120 :
{
unsigned int val = (((insn >> 7) & (1 << 4)) | ((insn >> 6) & (15 << 0)));
unsigned int val = (((insn >> 6) & (63 << 0)));
switch (val)
{
case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs;
@ -1856,12 +1866,16 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
case 13 : itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli;
case 14 : itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi;
case 15 : itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths;
case 16 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos;
case 17 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh;
case 18 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis;
case 19 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih;
case 20 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets;
case 21 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth;
case 16 : itype = FRVBF_INSN_MQLCLRHS; goto extract_sfmt_mqsaths;
case 17 : itype = FRVBF_INSN_MQSLLHI; goto extract_sfmt_mqsllhi;
case 19 : itype = FRVBF_INSN_MQSRAHI; goto extract_sfmt_mqsllhi;
case 20 : itype = FRVBF_INSN_MQLMTHS; goto extract_sfmt_mqsaths;
case 32 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos;
case 33 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh;
case 34 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis;
case 35 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih;
case 36 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets;
case 37 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth;
default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
@ -9455,6 +9469,47 @@ frvbf_decode (SIM_CPU *current_cpu, IADDR pc,
FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
}
#endif
#undef FLD
return idesc;
}
extract_sfmt_mqsllhi:
{
const IDESC *idesc = &frvbf_insn_data[itype];
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_mqsllhi.f
UINT f_FRk;
UINT f_FRi;
UINT f_u6;
f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
/* Record the fields for the semantic handler. */
FLD (f_FRi) = f_FRi;
FLD (f_FRk) = f_FRk;
FLD (f_u6) = f_u6;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqsllhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0));
#if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */
if (PROFILE_MODEL_P (current_cpu))
{
FLD (in_FRintieven) = f_FRi;
FLD (in_FRintkeven) = f_FRk;
FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
FLD (out_FRintieven) = f_FRi;
FLD (out_FRintkeven) = f_FRk;
FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
}
#endif
#undef FLD
return idesc;
}

177
sim/frv/decode.h
View file

@ -166,60 +166,62 @@ typedef enum frvbf_insn_type {
, FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB
, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL
, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR
, FRVBF_INSN_COP1, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR
, FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR
, FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI
, FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI
, FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI
, FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD
, FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD
, FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD
, FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS
, FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS
, FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS
, FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD
, FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS
, FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS
, FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS
, FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD
, FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS
, FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS
, FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS
, FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD
, FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS
, FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS
, FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS
, FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS
, FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH
, FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR
, FRVBF_INSN_CMAND, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT
, FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT
, FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS
, FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI
, FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI
, FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU
, FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS
, FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS
, FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS
, FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS
, FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS
, FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS
, FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS
, FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS
, FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS
, FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS
, FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS
, FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS
, FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU
, FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU
, FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU
, FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW
, FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH
, FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH
, FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE
, FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC
, FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1
, FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
, FRVBF_INSN_LRAI, FRVBF_INSN_LRAD, FRVBF_INSN_TLBPR, FRVBF_INSN_COP1
, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA
, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA
, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD
, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS
, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS
, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS
, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS
, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS
, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS
, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS
, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD
, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS
, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS
, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS
, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS
, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS
, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS
, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS
, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS
, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS
, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS
, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS
, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS
, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS
, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH
, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND
, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT
, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI
, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI
, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI
, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI
, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH
, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS
, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS
, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS
, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS
, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MQLCLRHS, FRVBF_INSN_MQLMTHS
, FRVBF_INSN_MQSLLHI, FRVBF_INSN_MQSRAHI, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS
, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS
, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU
, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU
, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU
, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU
, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU
, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS
, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS
, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS
, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS
, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD
, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH
, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB
, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP
, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG
, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2
, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
} FRVBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family frvbf. */
@ -279,16 +281,17 @@ typedef enum frvbf_sfmt_type {
, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI
, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI
, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS
, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS
, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS
, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU
, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU
, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS
, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD
, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH
, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB
, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0
, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
, FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MQSLLHI, FRVBF_SFMT_MADDACCS
, FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS
, FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS
, FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS
, FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS
, FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW
, FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH
, FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH
, FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE
, FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC
, FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE;
/* Function unit handlers (user written). */
@ -441,6 +444,52 @@ extern int frvbf_model_fr400_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/,
extern int frvbf_model_fr400_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
extern int frvbf_model_fr400_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
extern int frvbf_model_fr400_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr450_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr450_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr450_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_7 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FCCk*/);
extern int frvbf_model_fr450_u_media_6 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_4_accg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACCGi*/, INT /*FRinti*/, INT /*ACCGk*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_3_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_3 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr450_u_media_2_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
extern int frvbf_model_fr450_u_media_2_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
extern int frvbf_model_fr450_u_media_2 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
extern int frvbf_model_fr450_u_media_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRkhi*/, INT /*FRklo*/);
extern int frvbf_model_fr450_u_media_1_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_media_1 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/);
extern int frvbf_model_fr450_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/);
extern int frvbf_model_fr450_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/);
extern int frvbf_model_fr450_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/);
extern int frvbf_model_fr450_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr450_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
extern int frvbf_model_fr450_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
extern int frvbf_model_fr450_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
extern int frvbf_model_fr450_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/);
extern int frvbf_model_fr450_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/);
extern int frvbf_model_fr450_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
extern int frvbf_model_fr450_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
extern int frvbf_model_fr450_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
extern int frvbf_model_fr450_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
extern int frvbf_model_fr450_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
extern int frvbf_model_fr450_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_simple_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/* Profiling before/after handlers (user written) */

7
sim/frv/frv-sim.h
View file

@ -23,11 +23,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
#include "sim-options.h"
/* Not defined in the cgen cpu file for access restriction purposes. */
#define H_SPR_ACC4 1412
#define H_SPR_ACC63 1471
#define H_SPR_ACCG4 1476
#define H_SPR_ACCG63 1535
/* True if SPR is the number of accumulator or accumulator guard register. */
#define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
/* Initialization of the frv cpu. */
void frv_initialize (SIM_CPU *, SIM_DESC);

34
sim/frv/frv.c
View file

@ -173,7 +173,15 @@ check_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Note: there is a discrepancy between V2.2 of the FR400
instruction manual and the various FR4xx LSI specs.
The former claims that unaligned registers cause a
register_exception while the latter say it's an
illegal_instruction. The LSI specs appear to be
correct; in fact, the FR4xx series is not documented
as having a register_exception. */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
@ -201,7 +209,9 @@ check_fr_register_alignment (SIM_CPU *current_cpu, UINT reg, int align_mask)
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* See comment in check_register_alignment(). */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
@ -233,7 +243,9 @@ check_memory_alignment (SIM_CPU *current_cpu, SI address, int align_mask)
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* See comment in check_register_alignment(). */
case bfd_mach_fr400:
case bfd_mach_fr450:
frv_queue_data_access_error_interrupt (current_cpu, address);
break;
case bfd_mach_frvtomcat:
@ -990,10 +1002,11 @@ void
frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A)
{
SIM_DESC sd = CPU_STATE (current_cpu);
int acc_num =
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 :
int acc_mask =
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 7 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 7 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) ? 11 :
(STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 3 :
63;
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
@ -1003,15 +1016,16 @@ frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A)
{
/* This instruction is a nop if the referenced accumulator is not
implemented. */
if (acc_ix < acc_num)
if ((acc_ix & acc_mask) == acc_ix)
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, acc_ix, 0);
}
else
{
/* Clear all implemented accumulators. */
int i;
for (i = 0; i < acc_num; ++i)
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0);
for (i = 0; i <= acc_mask; ++i)
if ((i & acc_mask) == i)
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0);
}
}
@ -1208,12 +1222,14 @@ do_media_average (SIM_CPU *current_cpu, HI arg1, HI arg2)
HI result = sum >> 1;
int rounding_value;
/* On fr400 and fr550, check the rounding mode. On other machines rounding is always
toward negative infinity and the result is already correctly rounded. */
/* On fr4xx and fr550, check the rounding mode. On other machines
rounding is always toward negative infinity and the result is
already correctly rounded. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Need to check rounding mode. */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
/* Check whether rounding will be required. Rounding will be required
if the sum is an odd number. */

2
sim/frv/interrupts.c
View file

@ -239,6 +239,7 @@ frv_queue_illegal_instruction_interrupt (
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
break;
default:
@ -299,6 +300,7 @@ frv_queue_non_implemented_instruction_interrupt (
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
break;
default:

4
sim/frv/memory.c
View file

@ -73,6 +73,7 @@ check_data_read_address (SIM_CPU *current_cpu, SI address, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
address = fr400_check_data_read_address (current_cpu, address,
align_mask);
break;
@ -149,6 +150,7 @@ check_readwrite_address (SIM_CPU *current_cpu, SI address, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
address = fr400_check_readwrite_address (current_cpu, address,
align_mask);
break;
@ -240,6 +242,7 @@ check_insn_read_address (SIM_CPU *current_cpu, PCADDR address, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
address = fr400_check_insn_read_address (current_cpu, address,
align_mask);
break;
@ -723,6 +726,7 @@ check_write_address (SIM_CPU *current_cpu, SI address, int align_mask)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
address = fr400_check_write_address (current_cpu, address, align_mask);
break;
case bfd_mach_frvtomcat:

1
sim/frv/mloop.in
View file

@ -391,6 +391,7 @@ static void
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
simulate_dual_insn_prefetch (current_cpu, vpc, 8);
break;
case bfd_mach_frvtomcat:

17551
sim/frv/model.c
View file

File diff suppressed because it is too large Load diff

607
sim/frv/profile-fr450.c Normal file
View file

@ -0,0 +1,607 @@
/* frv simulator fr450 dependent profiling code.
Copyright (C) 2001, 2004 Free Software Foundation, Inc.
Contributed by Red Hat
This file is part of the GNU simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define WANT_CPU
#define WANT_CPU_FRVBF
#include "sim-main.h"
#include "bfd.h"
#if WITH_PROFILE_MODEL_P
#include "profile.h"
#include "profile-fr400.h"
int
frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced)
{
return idesc->timing->units[unit_num].done;
}
int
frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj, INT out_GRk,
INT out_ICCi_1)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, out_GRk, out_ICCi_1);
}
int
frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
{
int cycles;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
/* Pass 1 is the same as for fr500. */
return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, out_GRk, out_ICCi_1);
}
/* icc0-icc4 are the upper 4 fields of the CCR. */
if (out_ICCi_1 >= 0)
out_ICCi_1 += 4;
/* GRk and IACCi_1 have a latency of 1 cycle. */
cycles = idesc->timing->units[unit_num].done;
update_GRdouble_latency (cpu, out_GRk, cycles + 1);
update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
return cycles;
}
int
frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
{
int cycles;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
/* Pass 1 is the same as for fr500. */
return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, out_GRk, out_ICCi_1);
}
/* icc0-icc4 are the upper 4 fields of the CCR. */
if (out_ICCi_1 >= 0)
out_ICCi_1 += 4;
/* GRk, ICCi_1 and the divider have a latency of 18 cycles */
cycles = idesc->timing->units[unit_num].done;
update_GR_latency (cpu, out_GRk, cycles + 18);
update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
update_idiv_resource_latency (cpu, 0, cycles + 18);
return cycles;
}
int
frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj,
INT in_ICCi_2, INT in_ICCi_3)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, in_ICCi_2, in_ICCi_3);
}
int
frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj,
INT in_ICCi_2, INT in_FCCi_2)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
}
int
frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ICCi_3, INT in_FCCi_3)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
in_ICCi_3, in_FCCi_3);
}
int
frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT out_GRkhi, INT out_GRklo)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced,
out_GRkhi, out_GRklo);
}
int
frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj,
INT out_GRk, INT out_GRdoublek)
{
int cycles;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
/* Pass 1 is the same as for fr500. */
return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, out_GRk,
out_GRdoublek);
}
cycles = idesc->timing->units[unit_num].done;
/* The latency of GRk for a load will depend on how long it takes to retrieve
the the data from the cache or memory. */
update_GR_latency_for_load (cpu, out_GRk, cycles);
update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
{
/* GNER has a latency of 2 cycles. */
update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
}
return cycles;
}
int
frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj,
INT in_GRk, INT in_GRdoublek)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, in_GRk, in_GRdoublek);
}
int
frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj,
INT out_FRk, INT out_FRdoublek)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, out_FRk, out_FRdoublek);
}
int
frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj,
INT in_FRk, INT in_FRdoublek)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, in_FRk, in_FRdoublek);
}
int
frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj, INT out_GRk)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj, out_GRk);
}
int
frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRk, INT out_GRj)
{
int cycles;
if (model_insn == FRV_INSN_MODEL_PASS_1)
{
/* Pass 1 is the same as for fr400. */
return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced,
in_FRk, out_GRj);
}
/* The latency of GRj is 1 cycle. */
cycles = idesc->timing->units[unit_num].done;
update_GR_latency (cpu, out_GRj, cycles + 1);
return cycles;
}
int
frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_spr, INT out_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
in_spr, out_GRj);
}
int
frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRj, INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced,
in_GRj, out_FRk);
}
int
frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRj, INT out_spr)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced,
in_GRj, out_spr);
}
int
frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT in_FRj,
INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
in_FRi, in_FRj, out_FRk);
}
int
frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT in_FRj,
INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
in_FRi, in_FRj, out_FRk);
}
int
frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT out_FRkhi, INT out_FRklo)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced,
out_FRkhi, out_FRklo);
}
int
frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT in_FRj,
INT out_ACC40Sk, INT out_ACC40Uk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced,
in_FRi, in_FRj, out_ACC40Sk,
out_ACC40Uk);
}
int
frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT in_FRj,
INT out_ACC40Sk, INT out_ACC40Uk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced,
in_FRi, in_FRj, out_ACC40Sk,
out_ACC40Uk);
}
int
frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ACC40Si, INT out_ACC40Sk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced,
in_ACC40Si, out_ACC40Sk);
}
int
frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ACC40Si, INT out_ACC40Sk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num,
referenced, in_ACC40Si,
out_ACC40Sk);
}
int
frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ACC40Si, INT out_ACC40Sk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num,
referenced, in_ACC40Si,
out_ACC40Sk);
}
int
frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ACC40Si, INT out_ACC40Sk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num,
referenced, in_ACC40Si,
out_ACC40Sk);
}
int
frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT in_FRj,
INT out_FRk)
{
/* Modelling is the same as media unit 1. */
return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced,
in_FRi, in_FRj, out_FRk);
}
int
frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced,
in_FRi, out_FRk);
}
int
frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT in_FRj,
INT out_FRk)
{
/* Modelling is the same as media unit 1. */
return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced,
in_FRi, in_FRj, out_FRk);
}
int
frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ACC40Si, INT in_FRj,
INT out_ACC40Sk, INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
in_ACC40Si, in_FRj,
out_ACC40Sk, out_FRk);
}
int
frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ACCGi, INT in_FRinti,
INT out_ACCGk, INT out_FRintk)
{
/* Modelling is the same as media-4 unit except use accumulator guards
as input instead of accumulators. */
return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced,
in_ACCGi, in_FRinti,
out_ACCGk, out_FRintk);
}
int
frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_ACC40Si, INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num,
referenced, in_ACC40Si,
out_FRk);
}
int
frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced)
{
int cycles;
int acc;
FRV_PROFILE_STATE *ps;
if (model_insn == FRV_INSN_MODEL_PASS_1)
return 0;
/* The preprocessing can execute right away. */
cycles = idesc->timing->units[unit_num].done;
ps = CPU_PROFILE_STATE (cpu);
/* The post processing must wait for any pending ACC writes. */
ps->post_wait = cycles;
for (acc = 0; acc < 4; acc++)
post_wait_for_ACC (cpu, acc);
for (acc = 8; acc < 12; acc++)
post_wait_for_ACC (cpu, acc);
for (acc = 0; acc < 4; acc++)
{
update_ACC_latency (cpu, acc, ps->post_wait);
update_ACC_ptime (cpu, acc, 2);
}
for (acc = 8; acc < 12; acc++)
{
update_ACC_latency (cpu, acc, ps->post_wait);
update_ACC_ptime (cpu, acc, 2);
}
return cycles;
}
int
frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi, INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced,
in_FRi, out_FRk);
}
int
frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRinti, INT in_FRintj,
INT out_FCCk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced,
in_FRinti, in_FRintj, out_FCCk);
}
int
frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRi,
INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num,
referenced, in_FRi, out_FRk);
}
int
frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_FRj,
INT out_FRk)
{
/* Modelling for this unit is the same as for fr400. */
return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num,
referenced, in_FRj, out_FRk);
}
int
frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj);
}
int
frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj);
}
int
frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj);
}
int
frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj);
}
int
frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj);
}
int
frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj);
}
int
frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced,
INT in_GRi, INT in_GRj)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
in_GRi, in_GRj);
}
int
frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
}
int
frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced)
{
/* Modelling for this unit is the same as for fr500. */
return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
}
#endif /* WITH_PROFILE_MODEL_P */

11
sim/frv/profile.c
View file

@ -37,7 +37,8 @@ static void
reset_gr_flags (SIM_CPU *cpu, INT gr)
{
SIM_DESC sd = CPU_STATE (cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
fr400_reset_gr_flags (cpu, gr);
/* Other machines have no gr flags right now. */
}
@ -46,7 +47,8 @@ static void
reset_fr_flags (SIM_CPU *cpu, INT fr)
{
SIM_DESC sd = CPU_STATE (cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
fr400_reset_fr_flags (cpu, fr);
else if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500)
fr500_reset_fr_flags (cpu, fr);
@ -56,7 +58,8 @@ static void
reset_acc_flags (SIM_CPU *cpu, INT acc)
{
SIM_DESC sd = CPU_STATE (cpu);
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
fr400_reset_acc_flags (cpu, acc);
/* Other machines have no acc flags right now. */
}
@ -926,6 +929,7 @@ frvbf_model_insn_before (SIM_CPU *cpu, int first_p)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
fr400_model_insn_before (cpu, first_p);
break;
case bfd_mach_fr500:
@ -992,6 +996,7 @@ frvbf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
case bfd_mach_fr450:
fr400_model_insn_after (cpu, last_p, cycles);
break;
case bfd_mach_fr500:

1059
sim/frv/registers.c
View file

File diff suppressed because it is too large Load diff

322
sim/frv/sem.c
View file

@ -16404,6 +16404,57 @@ SEM_FN_NAME (frvbf,membar) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
/* lrai: lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
static SEM_PC
SEM_FN_NAME (frvbf,lrai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
return vpc;
#undef FLD
}
/* lrad: lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
static SEM_PC
SEM_FN_NAME (frvbf,lrad) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
return vpc;
#undef FLD
}
/* tlbpr: tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
static SEM_PC
SEM_FN_NAME (frvbf,tlbpr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
((void) 0); /*nop*/
return vpc;
#undef FLD
}
/* cop1: cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
static SEM_PC
@ -22608,6 +22659,270 @@ frvbf_media_overflow (current_cpu, 1);
#undef FLD
}
/* mqlclrhs: mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
static SEM_PC
SEM_FN_NAME (frvbf,mqlclrhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
frvbf_media_register_not_aligned (current_cpu);
} else {
{
HI tmp_a1;
HI tmp_a2;
HI tmp_a3;
HI tmp_a4;
HI tmp_b1;
HI tmp_b2;
HI tmp_b3;
HI tmp_b4;
{
SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
written |= (1 << 14);
TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
}
{
tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
}
{
tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
}
{
UHI opval = (LEUHI (ABSHI (tmp_a1), ABSHI (tmp_b1))) ? (0) : (LEHI (0, tmp_b1)) ? (tmp_a1) : (EQHI (tmp_a1, -32768)) ? (32767) : (NEGHI (tmp_a1));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 15);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = (LEUHI (ABSHI (tmp_a2), ABSHI (tmp_b2))) ? (0) : (LEHI (0, tmp_b2)) ? (tmp_a2) : (EQHI (tmp_a2, -32768)) ? (32767) : (NEGHI (tmp_a2));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 17);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
{
UHI opval = (LEUHI (ABSHI (tmp_a3), ABSHI (tmp_b3))) ? (0) : (LEHI (0, tmp_b3)) ? (tmp_a3) : (EQHI (tmp_a3, -32768)) ? (32767) : (NEGHI (tmp_a3));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 16);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = (LEUHI (ABSHI (tmp_a4), ABSHI (tmp_b4))) ? (0) : (LEHI (0, tmp_b4)) ? (tmp_a4) : (EQHI (tmp_a4, -32768)) ? (32767) : (NEGHI (tmp_a4));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 18);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* mqlmths: mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
static SEM_PC
SEM_FN_NAME (frvbf,mqlmths) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
frvbf_media_register_not_aligned (current_cpu);
} else {
{
HI tmp_a1;
HI tmp_a2;
HI tmp_a3;
HI tmp_a4;
HI tmp_b1;
HI tmp_b2;
HI tmp_b3;
HI tmp_b4;
{
SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
written |= (1 << 14);
TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
}
{
tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
}
{
tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
}
{
UHI opval = (ANDIF (GTHI (tmp_b1, -32768), GEHI (tmp_a1, ABSHI (tmp_b1)))) ? (tmp_b1) : (GTHI (tmp_a1, NEGHI (ABSHI (tmp_b1)))) ? (tmp_a1) : (EQHI (tmp_b1, -32768)) ? (32767) : (NEGHI (tmp_b1));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 15);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = (ANDIF (GTHI (tmp_b2, -32768), GEHI (tmp_a2, ABSHI (tmp_b2)))) ? (tmp_b2) : (GTHI (tmp_a2, NEGHI (ABSHI (tmp_b2)))) ? (tmp_a2) : (EQHI (tmp_b2, -32768)) ? (32767) : (NEGHI (tmp_b2));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 17);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
{
UHI opval = (ANDIF (GTHI (tmp_b3, -32768), GEHI (tmp_a3, ABSHI (tmp_b3)))) ? (tmp_b3) : (GTHI (tmp_a3, NEGHI (ABSHI (tmp_b3)))) ? (tmp_a3) : (EQHI (tmp_b3, -32768)) ? (32767) : (NEGHI (tmp_b3));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 16);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = (ANDIF (GTHI (tmp_b4, -32768), GEHI (tmp_a4, ABSHI (tmp_b4)))) ? (tmp_b4) : (GTHI (tmp_a4, NEGHI (ABSHI (tmp_b4)))) ? (tmp_a4) : (EQHI (tmp_b4, -32768)) ? (32767) : (NEGHI (tmp_b4));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 18);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* mqsllhi: mqsllhi$pack $FRintieven,$u6,$FRintkeven */
static SEM_PC
SEM_FN_NAME (frvbf,mqsllhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mqsllhi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) {
frvbf_media_register_not_aligned (current_cpu);
} else {
{
{
SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
}
{
SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
written |= (1 << 10);
TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
}
{
UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
{
UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 12);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 14);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* mqsrahi: mqsrahi$pack $FRintieven,$u6,$FRintkeven */
static SEM_PC
SEM_FN_NAME (frvbf,mqsrahi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mqsllhi.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) {
frvbf_media_register_not_aligned (current_cpu);
} else {
{
{
SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
written |= (1 << 9);
TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
}
{
SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
written |= (1 << 10);
TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
}
{
UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 11);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
written |= (1 << 13);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
{
UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 12);
TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
}
{
UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
written |= (1 << 14);
TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
}
}
}
abuf->written = written;
return vpc;
#undef FLD
}
/* maddaccs: maddaccs$pack $ACC40Si,$ACC40Sk */
static SEM_PC
@ -28381,6 +28696,9 @@ static const struct sem_fn_desc sem_fns[] = {
{ FRVBF_INSN_DCUL, SEM_FN_NAME (frvbf,dcul) },
{ FRVBF_INSN_BAR, SEM_FN_NAME (frvbf,bar) },
{ FRVBF_INSN_MEMBAR, SEM_FN_NAME (frvbf,membar) },
{ FRVBF_INSN_LRAI, SEM_FN_NAME (frvbf,lrai) },
{ FRVBF_INSN_LRAD, SEM_FN_NAME (frvbf,lrad) },
{ FRVBF_INSN_TLBPR, SEM_FN_NAME (frvbf,tlbpr) },
{ FRVBF_INSN_COP1, SEM_FN_NAME (frvbf,cop1) },
{ FRVBF_INSN_COP2, SEM_FN_NAME (frvbf,cop2) },
{ FRVBF_INSN_CLRGR, SEM_FN_NAME (frvbf,clrgr) },
@ -28528,6 +28846,10 @@ static const struct sem_fn_desc sem_fns[] = {
{ FRVBF_INSN_CMQADDHUS, SEM_FN_NAME (frvbf,cmqaddhus) },
{ FRVBF_INSN_CMQSUBHSS, SEM_FN_NAME (frvbf,cmqsubhss) },
{ FRVBF_INSN_CMQSUBHUS, SEM_FN_NAME (frvbf,cmqsubhus) },
{ FRVBF_INSN_MQLCLRHS, SEM_FN_NAME (frvbf,mqlclrhs) },
{ FRVBF_INSN_MQLMTHS, SEM_FN_NAME (frvbf,mqlmths) },
{ FRVBF_INSN_MQSLLHI, SEM_FN_NAME (frvbf,mqsllhi) },
{ FRVBF_INSN_MQSRAHI, SEM_FN_NAME (frvbf,mqsrahi) },
{ FRVBF_INSN_MADDACCS, SEM_FN_NAME (frvbf,maddaccs) },
{ FRVBF_INSN_MSUBACCS, SEM_FN_NAME (frvbf,msubaccs) },
{ FRVBF_INSN_MDADDACCS, SEM_FN_NAME (frvbf,mdaddaccs) },

13
sim/frv/traps.c
View file

@ -50,7 +50,8 @@ frv_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
{
if (sig == sim_core_unaligned_signal)
{
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
|| STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
frv_queue_data_access_error_interrupt (current_cpu, addr);
else
frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr);
@ -591,7 +592,13 @@ frvbf_media_cr_not_aligned (SIM_CPU *current_cpu)
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Note: there is a discrepancy between V2.2 of the FR400
instruction manual and the various FR4xx LSI specs. The former
claims that unaligned registers cause an mp_exception while the
latter say it's an illegal_instruction. The LSI specs appear
to be correct since MTT is fixed at 1. */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
@ -610,7 +617,9 @@ frvbf_media_acc_not_aligned (SIM_CPU *current_cpu)
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* See comment in frvbf_cr_not_aligned(). */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
@ -629,7 +638,9 @@ frvbf_media_register_not_aligned (SIM_CPU *current_cpu)
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* See comment in frvbf_cr_not_aligned(). */
case bfd_mach_fr400:
case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;

18
sim/testsuite/ChangeLog
View file

@ -1,3 +1,21 @@
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* sim/frv/allinsn.exp (all_machs): Add fr405 and fr450.
* sim/fr400/allinsn.exp (all_machs): Likewise.
* sim/fr400/addss.cgs (mach): Change to "fr405 fr450".
* sim/fr400/scutss.cgs (mach): Likewise.
* sim/fr400/slass.cgs (mach): Likewise.
* sim/fr400/smass.cgs (mach): Likewise.
* sim/fr400/smsss.cgs (mach): Likewise.
* sim/fr400/smu.cgs (mach): Likewise.
* sim/fr400/subss.cgs (mach): Likewise.
* sim/interrupts/fp_exception.cgs: Replace fmadds with .word.
* sim/interrupts/fp_exception-fr550.cgs: Likewise.
* sim/frv/mqlclrhs.cgs: New test.
* sim/frv/mqlmths.cgs: New test.
* sim/frv/mqsllhi.cgs: New test.
* sim/frv/mqsrahi.cgs: New test.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
* sim/frv/fr400/scutss.cgs: Fix tests to account for rounding.

2
sim/testsuite/sim/frv/allinsn.exp
View file

@ -4,7 +4,7 @@ if [istarget frv*-*] {
# load support procs (none yet)
# load_lib cgen.exp
# all machines
set all_machs "frv fr500 fr550 fr400"
set all_machs "frv fr500 fr550 fr400 fr405 fr450"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".

2
sim/testsuite/sim/frv/fr400/addss.cgs
View file

@ -1,5 +1,5 @@
# frv testcase for addss $GRi,$GRj,$GRk
# mach: fr400
# mach: fr405 fr450
.include "../testutils.inc"

2
sim/testsuite/sim/frv/fr400/allinsn.exp
View file

@ -4,7 +4,7 @@ if [istarget frv*-*] {
# load support procs (none yet)
# load_lib cgen.exp
# all machines
set all_machs "fr400 fr550"
set all_machs "fr400 fr405 fr450 fr550"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".

2
sim/testsuite/sim/frv/fr400/scutss.cgs
View file

@ -1,5 +1,5 @@
# frv testcase for scutss $FRj,$FRk
# mach: fr400
# mach: fr405 fr450
.include "../testutils.inc"

2
sim/testsuite/sim/frv/fr400/slass.cgs
View file

@ -1,5 +1,5 @@
# frv testcase for slass $GRi,$GRj,$GRk
# mach: fr400
# mach: fr405 fr450
.include "../testutils.inc"

2
sim/testsuite/sim/frv/fr400/smass.cgs
View file

@ -1,5 +1,5 @@
# frv testcase for smass $GRi,$GRj
# mach: fr400
# mach: fr405 fr450
.include "../testutils.inc"

2
sim/testsuite/sim/frv/fr400/smsss.cgs
View file

@ -1,5 +1,5 @@
# frv testcase for smsss $GRi,$GRj
# mach: fr400
# mach: fr405 fr450
.include "../testutils.inc"

2
sim/testsuite/sim/frv/fr400/smu.cgs
View file

@ -1,5 +1,5 @@
# frv testcase for smu $GRi,$GRj
# mach: fr400
# mach: fr405 fr450
.include "../testutils.inc"

2
sim/testsuite/sim/frv/fr400/subss.cgs
View file

@ -1,5 +1,5 @@
# frv testcase for subss $GRi,$GRj,$GRk
# mach: fr400
# mach: fr405 fr450
.include "../testutils.inc"

2
sim/testsuite/sim/frv/interrupts/fp_exception-fr550.cgs
View file

@ -70,7 +70,7 @@ pack: fnegs fr10,fr12
set_spr_addr ok1,lr
set_gr_immed 4,gr20 ; PC increment
bad: fmadds fr16,fr4,fr1 ; unimplemented
bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented)
test_gr_immed 4,gr15
and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception

2
sim/testsuite/sim/frv/interrupts/fp_exception.cgs
View file

@ -65,7 +65,7 @@ pack: fnegs fr10,fr10
set_spr_addr ok1,lr
set_gr_immed 4,gr20 ; PC increment
bad: fmadds fr16,fr4,fr1 ; unimplemented
bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented)
test_gr_immed 4,gr15
and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception

74
sim/testsuite/sim/frv/mqlclrhs.cgs Normal file
View file

@ -0,0 +1,74 @@
# frv testcase for mqlclrhs $FRi,$FRj,$FRj
# mach: fr450
.include "testutils.inc"
start
.global mqlclrhs
mqlclrhs:
set_fr_iimmed 0x1000,0x2000,fr4
set_fr_iimmed 0xe800,0xd800,fr5
set_fr_iimmed 0x0800,0x0800,fr6
set_fr_iimmed 0x0800,0x0800,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0x1000,0x2000,fr8
test_fr_limmed 0xe800,0xd800,fr9
set_fr_iimmed 0x1000,0x2000,fr4
set_fr_iimmed 0xe800,0xd800,fr5
set_fr_iimmed 0xf800,0xf800,fr6
set_fr_iimmed 0xf800,0xf800,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0xf000,0xe000,fr8
test_fr_limmed 0x1800,0x2800,fr9
set_fr_iimmed 0x1000,0x1000,fr4
set_fr_iimmed 0x1000,0x1000,fr5
set_fr_iimmed 0xf000,0xf800,fr6
set_fr_iimmed 0x0800,0x1000,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0x0000,0xf000,fr8
test_fr_limmed 0x1000,0x0000,fr9
set_fr_iimmed 0xf000,0xf000,fr4
set_fr_iimmed 0xf000,0xf000,fr5
set_fr_iimmed 0xf000,0xf800,fr6
set_fr_iimmed 0x0800,0x1000,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0x0000,0x1000,fr8
test_fr_limmed 0xf000,0x0000,fr9
set_fr_iimmed 0x8000,0x8000,fr4
set_fr_iimmed 0x8000,0x8000,fr5
set_fr_iimmed 0x8000,0x7fff,fr6
set_fr_iimmed 0x8001,0x0000,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0x0000,0x8000,fr8
test_fr_limmed 0x7fff,0x8000,fr9
set_fr_iimmed 0x7fff,0x7fff,fr4
set_fr_iimmed 0x7fff,0x7fff,fr5
set_fr_iimmed 0x8000,0x7fff,fr6
set_fr_iimmed 0x8001,0x0000,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0x0000,0x0000,fr8
test_fr_limmed 0x0000,0x7fff,fr9
set_fr_iimmed 0x8001,0x8001,fr4
set_fr_iimmed 0x8001,0x8001,fr5
set_fr_iimmed 0x8000,0x7fff,fr6
set_fr_iimmed 0x8001,0x0000,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0x0000,0x0000,fr8
test_fr_limmed 0x0000,0x8001,fr9
set_fr_iimmed 0x8000,0x8000,fr4
set_fr_iimmed 0x0001,0xffff,fr5
set_fr_iimmed 0x0001,0xffff,fr6
set_fr_iimmed 0x8000,0x8000,fr7
mqlclrhs fr4,fr6,fr8
test_fr_limmed 0x8000,0x7fff,fr8
test_fr_limmed 0x0000,0x0000,fr9
pass

74
sim/testsuite/sim/frv/mqlmths.cgs Normal file
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# frv testcase for mqlmths $FRi,$FRj,$FRj
# mach: fr450
.include "testutils.inc"
start
.global mqlmths
mqlmths:
set_fr_iimmed 0x1000,0x2000,fr4
set_fr_iimmed 0xe800,0xd800,fr5
set_fr_iimmed 0x0800,0x0800,fr6
set_fr_iimmed 0x0800,0x0800,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0x0800,0x0800,fr8
test_fr_limmed 0xf800,0xf800,fr9
set_fr_iimmed 0x1000,0x2000,fr4
set_fr_iimmed 0xe800,0xd800,fr5
set_fr_iimmed 0xf800,0xf800,fr6
set_fr_iimmed 0xf800,0xf800,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0xf800,0xf800,fr8
test_fr_limmed 0x0800,0x0800,fr9
set_fr_iimmed 0x1000,0x1000,fr4
set_fr_iimmed 0x1000,0x1000,fr5
set_fr_iimmed 0xe800,0xf800,fr6
set_fr_iimmed 0x0800,0x1800,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0x1000,0xf800,fr8
test_fr_limmed 0x0800,0x1000,fr9
set_fr_iimmed 0xf000,0xf000,fr4
set_fr_iimmed 0xf000,0xf000,fr5
set_fr_iimmed 0xe800,0xf800,fr6
set_fr_iimmed 0x0800,0x1800,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0xf000,0x0800,fr8
test_fr_limmed 0xf800,0xf000,fr9
set_fr_iimmed 0x8000,0x8000,fr4
set_fr_iimmed 0x8000,0x8000,fr5
set_fr_iimmed 0x8000,0x7fff,fr6
set_fr_iimmed 0x8001,0x0000,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0x7fff,0x8001,fr8
test_fr_limmed 0x7fff,0x0000,fr9
set_fr_iimmed 0x7fff,0x7fff,fr4
set_fr_iimmed 0x7fff,0x7fff,fr5
set_fr_iimmed 0x8000,0x7fff,fr6
set_fr_iimmed 0x8001,0x0000,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0x7fff,0x7fff,fr8
test_fr_limmed 0x8001,0x0000,fr9
set_fr_iimmed 0x8001,0x8001,fr4
set_fr_iimmed 0x8001,0x8001,fr5
set_fr_iimmed 0x8000,0x7fff,fr6
set_fr_iimmed 0x8001,0x0000,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0x8001,0x8001,fr8
test_fr_limmed 0x7fff,0x0000,fr9
set_fr_iimmed 0x8000,0x8000,fr4
set_fr_iimmed 0x0001,0xffff,fr5
set_fr_iimmed 0x0001,0xffff,fr6
set_fr_iimmed 0x8000,0x8000,fr7
mqlmths fr4,fr6,fr8
test_fr_limmed 0xffff,0x0001,fr8
test_fr_limmed 0x0001,0xffff,fr9
pass

40
sim/testsuite/sim/frv/mqsllhi.cgs Normal file
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# frv testcase for mqsllhi $FRi,#u6,$FRj
# mach: fr450
.include "testutils.inc"
start
.global mqsllhi
mqsllhi:
set_fr_iimmed 0x0001,0x0002,fr4
set_fr_iimmed 0x0003,0x0004,fr5
mqsllhi fr4,#1,fr6
test_fr_limmed 0x0002,0x0004,fr6
test_fr_limmed 0x0006,0x0008,fr7
set_fr_iimmed 0xffff,0xfffe,fr4
set_fr_iimmed 0xfffc,0xfff8,fr5
mqsllhi fr4,#1,fr6
test_fr_limmed 0xfffe,0xfffc,fr6
test_fr_limmed 0xfff8,0xfff0,fr7
set_fr_iimmed 0xffff,0xfffe,fr4
set_fr_iimmed 0xfffc,0xfff8,fr5
mqsllhi fr4,#12,fr6
test_fr_limmed 0xf000,0xe000,fr6
test_fr_limmed 0xc000,0x8000,fr7
set_fr_iimmed 0x1234,0x5678,fr4
set_fr_iimmed 0x9abc,0xdef0,fr5
mqsllhi fr4,#12,fr6
test_fr_limmed 0x4000,0x8000,fr6
test_fr_limmed 0xc000,0x0000,fr7
set_fr_iimmed 0x1234,0x5678,fr4
set_fr_iimmed 0x9abc,0xdef0,fr5
mqsllhi fr4,#16,fr6
test_fr_limmed 0x1234,0x5678,fr6
test_fr_limmed 0x9abc,0xdef0,fr7
pass

40
sim/testsuite/sim/frv/mqsrahi.cgs Normal file
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# frv testcase for mqsrahi $FRi,#u6,$FRj
# mach: fr450
.include "testutils.inc"
start
.global mqsrahi
mqsrahi:
set_fr_iimmed 0x0001,0x0002,fr4
set_fr_iimmed 0x0003,0x0004,fr5
mqsrahi fr4,#1,fr6
test_fr_limmed 0x0000,0x0001,fr6
test_fr_limmed 0x0001,0x0002,fr7
set_fr_iimmed 0xffff,0xfffe,fr4
set_fr_iimmed 0xfffc,0xfff8,fr5
mqsrahi fr4,#1,fr6
test_fr_limmed 0xffff,0xffff,fr6
test_fr_limmed 0xfffe,0xfffc,fr7
set_fr_iimmed 0x8000,0xc000,fr4
set_fr_iimmed 0xe000,0xf000,fr5
mqsrahi fr4,#12,fr6
test_fr_limmed 0xfff8,0xfffc,fr6
test_fr_limmed 0xfffe,0xffff,fr7
set_fr_iimmed 0x1234,0x5678,fr4
set_fr_iimmed 0x9abc,0xdef0,fr5
mqsrahi fr4,#12,fr6
test_fr_limmed 0x0001,0x0005,fr6
test_fr_limmed 0xfff9,0xfffd,fr7
set_fr_iimmed 0x1234,0x5678,fr4
set_fr_iimmed 0x9abc,0xdef0,fr5
mqsrahi fr4,#16,fr6
test_fr_limmed 0x1234,0x5678,fr6
test_fr_limmed 0x9abc,0xdef0,fr7
pass