* ppc-dis.c (struct dis_private): New.
(powerpc_dialect): Make static. Accept -Many in addition to existing options. Save dialect in dis_private. (print_insn_big_powerpc): Retrieve dialect from dis_private. (print_insn_little_powerpc): Likewise. (print_insn_powerpc): Call powpc_dialect here. Remove unnecessary efs/altivec check. Try harder to disassemble if given -Many. * ppc-opc.c (insert_fxm): Expand comment. (PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY. (POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise. (POWER4): Remove PPCCOM. (PPCONLY): Don't define. Update all occurrences to PPC.
This commit is contained in:
Alan Modra
parent
f6c4061856
commit
661bd698e4
3 changed files with 88 additions and 59 deletions
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@ -1,3 +1,18 @@
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2003-09-04 Alan Modra <amodra@bigpond.net.au>
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* ppc-dis.c (struct dis_private): New.
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(powerpc_dialect): Make static. Accept -Many in addition to existing
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options. Save dialect in dis_private.
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(print_insn_big_powerpc): Retrieve dialect from dis_private.
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(print_insn_little_powerpc): Likewise.
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(print_insn_powerpc): Call powpc_dialect here. Remove unnecessary
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efs/altivec check. Try harder to disassemble if given -Many.
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* ppc-opc.c (insert_fxm): Expand comment.
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(PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY.
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(POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise.
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(POWER4): Remove PPCCOM.
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(PPCONLY): Don't define. Update all occurrences to PPC.
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2003-09-03 Andrew Cagney <cagney@redhat.com>
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* dis-init.c (init_disassemble_info): New file and function.
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@ -171,7 +186,7 @@
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2003-07-30 Jason Eckhardt <jle@rice.edu>
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* i860-dis.c: Convert to ISO C90. Remove superflous prototypes.
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* i860-dis.c: Convert to ISO C90. Remove superflous prototypes.
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2003-07-30 Nick Clifton <nickc@redhat.com>
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@ -189,8 +204,8 @@
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* arm-dis.c (parse_arm_disassembler_option): Do not expect
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option string to be NUL terminated.
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(parse_disassembler_options): Allow options to be space or
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comma separated.
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(parse_disassembler_options): Allow options to be space or
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comma separated.
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2003-07-17 Nick Clifton <nickc@redhat.com>
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@ -32,11 +32,16 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int);
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struct dis_private {
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/* Stash the result of parsing disassembler_options here. */
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int dialect;
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};
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/* Determine which set of machines to disassemble for. PPC403/601 or
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BookE. For convenience, also disassemble instructions supported
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by the AltiVec vector unit. */
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int
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static int
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powerpc_dialect (struct disassemble_info *info)
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{
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int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC;
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@ -45,40 +50,39 @@ powerpc_dialect (struct disassemble_info *info)
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dialect |= PPC_OPCODE_64;
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if (info->disassembler_options
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&& (strcmp (info->disassembler_options, "booke") == 0
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|| strcmp (info->disassembler_options, "booke32") == 0
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|| strcmp (info->disassembler_options, "booke64") == 0))
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&& strstr (info->disassembler_options, "booke") != NULL)
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dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64;
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else
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if ((info->mach == bfd_mach_ppc_e500)
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|| (info->disassembler_options
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&& ( strcmp (info->disassembler_options, "e500") == 0
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|| strcmp (info->disassembler_options, "e500x2") == 0)))
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{
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dialect |= PPC_OPCODE_BOOKE
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| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
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| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
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| PPC_OPCODE_RFMCI;
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/* efs* and AltiVec conflict. */
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dialect &= ~PPC_OPCODE_ALTIVEC;
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}
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else
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if (info->disassembler_options
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&& (strcmp (info->disassembler_options, "efs") == 0))
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{
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dialect |= PPC_OPCODE_EFS;
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/* efs* and AltiVec conflict. */
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dialect &= ~PPC_OPCODE_ALTIVEC;
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}
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else if ((info->mach == bfd_mach_ppc_e500)
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|| (info->disassembler_options
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&& strstr (info->disassembler_options, "e500") != NULL))
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{
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dialect |= PPC_OPCODE_BOOKE
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| PPC_OPCODE_SPE | PPC_OPCODE_ISEL
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| PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
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| PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK
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| PPC_OPCODE_RFMCI;
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/* efs* and AltiVec conflict. */
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dialect &= ~PPC_OPCODE_ALTIVEC;
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}
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else if (info->disassembler_options
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&& strstr (info->disassembler_options, "efs") != NULL)
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{
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dialect |= PPC_OPCODE_EFS;
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/* efs* and AltiVec conflict. */
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dialect &= ~PPC_OPCODE_ALTIVEC;
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}
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else
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dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC
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| PPC_OPCODE_COMMON);
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if (info->disassembler_options
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&& strcmp (info->disassembler_options, "power4") == 0)
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&& strstr (info->disassembler_options, "power4") != NULL)
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dialect |= PPC_OPCODE_POWER4;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "any") != NULL)
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dialect |= PPC_OPCODE_ANY;
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if (info->disassembler_options)
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{
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if (strstr (info->disassembler_options, "32") != NULL)
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@ -87,6 +91,7 @@ powerpc_dialect (struct disassemble_info *info)
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dialect |= PPC_OPCODE_64;
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}
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((struct dis_private *) &info->private_data)->dialect = dialect;
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return dialect;
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}
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@ -95,7 +100,8 @@ powerpc_dialect (struct disassemble_info *info)
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int
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print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info));
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int dialect = ((struct dis_private *) &info->private_data)->dialect;
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return print_insn_powerpc (memaddr, info, 1, dialect);
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}
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/* Print a little endian PowerPC instruction. */
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@ -103,7 +109,8 @@ print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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int
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print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info)
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{
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return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info));
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int dialect = ((struct dis_private *) &info->private_data)->dialect;
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return print_insn_powerpc (memaddr, info, 0, dialect);
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}
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/* Print a POWER (RS/6000) instruction. */
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@ -129,6 +136,9 @@ print_insn_powerpc (bfd_vma memaddr,
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const struct powerpc_opcode *opcode_end;
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unsigned long op;
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if (dialect == 0)
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dialect = powerpc_dialect (info);
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status = (*info->read_memory_func) (memaddr, buffer, 4, info);
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if (status != 0)
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{
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@ -147,6 +157,7 @@ print_insn_powerpc (bfd_vma memaddr,
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/* Find the first match in the opcode table. We could speed this up
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a bit by doing a binary search on the major opcode. */
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opcode_end = powerpc_opcodes + powerpc_num_opcodes;
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again:
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for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++)
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{
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unsigned long table_op;
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@ -166,9 +177,6 @@ print_insn_powerpc (bfd_vma memaddr,
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|| (opcode->flags & dialect) == 0)
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continue;
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if ((dialect & PPC_OPCODE_EFS) && (opcode->flags & PPC_OPCODE_ALTIVEC))
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continue;
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/* Make two passes over the operands. First see if any of them
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have extraction functions, and, if they do, make sure the
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instruction is valid. */
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@ -277,6 +285,12 @@ print_insn_powerpc (bfd_vma memaddr,
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return 4;
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}
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if ((dialect & PPC_OPCODE_ANY) != 0)
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{
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dialect = ~PPC_OPCODE_ANY;
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goto again;
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}
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/* We could not find a match. */
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(*info->fprintf_func) (info->stream, ".long 0x%lx", insn);
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@ -1001,7 +1001,8 @@ insert_fxm (unsigned long insn,
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;
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/* If only one bit of the FXM field is set, we can use the new form
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of the instruction, which is faster. */
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of the instruction, which is faster. Unlike the Power4 branch hint
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encoding, this is not backward compatible. */
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else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value)
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insn |= 1 << 20;
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@ -1762,27 +1763,26 @@ extract_tbr (unsigned long insn,
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/* Smaller names for the flags so each entry in the opcodes table will
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fit on a single line. */
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#undef PPC
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#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY
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#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
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#define PPC PPC_OPCODE_PPC
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#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
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#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
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#define POWER4 PPC_OPCODE_POWER4 | PPCCOM
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#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
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#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY
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#define PPCONLY PPC_OPCODE_PPC
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#define POWER4 PPC_OPCODE_POWER4
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#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
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#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
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#define PPC403 PPC_OPCODE_403
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#define PPC405 PPC403
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#define PPC440 PPC_OPCODE_440
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#define PPC750 PPC
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#define PPC860 PPC
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#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC
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#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY
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#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
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#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY
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#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32
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#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
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#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32
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#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY
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#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY
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#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_PPC
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#define POWER PPC_OPCODE_POWER
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#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2
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#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
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#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
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#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
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#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
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#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601
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#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
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#define MFDEC1 PPC_OPCODE_POWER
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#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
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#define BOOKE PPC_OPCODE_BOOKE
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@ -2369,12 +2369,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } },
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{ "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } },
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{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } },
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{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } },
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{ "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } },
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{ "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } },
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{ "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } },
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{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } },
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{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } },
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{ "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } },
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{ "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } },
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@ -3158,7 +3158,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
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{ "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
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{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
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{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } },
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{ "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
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{ "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } },
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@ -3264,7 +3264,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } },
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{ "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } },
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{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } },
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{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } },
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{ "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } },
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{ "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } },
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@ -3636,12 +3636,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } },
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{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } },
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{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
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{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } },
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{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
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{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
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{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } },
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{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
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{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } },
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{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } },
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{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } },
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{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } },
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{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } },
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{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } },
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@ -4137,7 +4137,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } },
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{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } },
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{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } },
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{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } },
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{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } },
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{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } },
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{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } },
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Loading…
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