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binutils: support for the SPARC M8 processor

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This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.

New instructions:

- Dictionary Unpack

  + dictunpack

- Partitioned Compare with shifted result

  + Signed variants:   fpcmp{le,gt,eq,ne}{8,16,32}shl
  + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl

- Partitioned Dual-Equal compared, with shifted result

  + fpcmpde{8,16,32}shl

- Partitioned Unsigned Range Compare, with shifted result

  + fpcmpur{8,16,32}shl

- 64-bit shifts on Floating-Point registers

  + fps{ll,ra,rl}64x

- Misaligned loads and stores

  + ldm{sh,uh,sw,uw,x,ux}
  + ldm{sh,uh,sw,uw,x,ux}a
  + ldmf{s,d}
  + ldmf{s,d}a

  + stm{h,w,x}
  + stm{h,w,x}a
  + stmf{s,d}
  + stmf{s,d}a

- Oracle Numbers

  + on{add,sub,mul,div}

- Reverse Bytes/Bits

  + revbitsb
  + revbytes{h,w,x}

- Run-Length instructions

  + rle_burst
  + rle_length

- New crypto instructions

  + sha3

- Instruction to read the new register %entropy

  + rd %entropy

New Alternate Address Identifiers:

- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT

The new assembler command-line options for selecting the M8 architecture
are:

-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.

The corresponding disassembler command-line options are:

-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.

Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux

bfd/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* archures.c (bfd_mach_sparc_v9m8): Define.
	(bfd_mach_sparc_v8plusm8): Likewise.
	(bfd_mach_sparc_v9_p): Adjust to M8.
	(bfd_mach_sparc_64bit_p): Likewise.
	* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
	bfd_mach_sparc_v8plusm8.
	* bfd-in2.h: Regenerated.
	* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
	sparc:v8plusm8.
	* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
	bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
	capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
	SHA3.
	* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
	bfd_mach_sparc_v8plusm8.

binutils/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* NEWS: Mention the SPARC M8 support.

gas/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
	`v9m8' and `v8plusm8'.
	(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
	(get_hwcap_name): Support the M8 hardware capabilities.
	(sparc_ip): Handle new operand types.
	* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
	-Asparc6, and the corresponding -xarch aliases.
	* testsuite/gas/sparc/sparc6.s: New file.
	* testsuite/gas/sparc/sparc6.d: Likewise.
	* testsuite/gas/sparc/sparc6-diag.s: Likewise.
	* testsuite/gas/sparc/sparc6-diag.l: Likewise.
	* testsuite/gas/sparc/fpcmpshl.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl.d: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
	* testsuite/gas/sparc/ldm-stm.s: Likewise.
	* testsuite/gas/sparc/ldm-stm.d: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
	* testsuite/gas/sparc/on.s: Likewise.
	* testsuite/gas/sparc/on.d: Likewise.
	* testsuite/gas/sparc/on-diag.s: Likewise.
	* testsuite/gas/sparc/on-diag.l: Likewise.
	* testsuite/gas/sparc/rle.s: Likewise.
	* testsuite/gas/sparc/rle.d: Likewise.
	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
	* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
	* testsuite/gas/sparc/rdasr.d: Likewise.

include/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
	(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
	(ELF_SPARC_HWCAP2_ONMUL): Likewise.
	(ELF_SPARC_HWCAP2_ONDIV): Likewise.
	(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
	(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
	(ELF_SPARC_HWCAP2_RLE): Likewise.
	(ELF_SPARC_HWCAP2_SHA3): Likewise.
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
	and adjust SPARC_OPCODE_ARCH_MAX.
	(HWCAP2_SPARC6): Define.
	(HWCAP2_ONADDSUB): Likewise.
	(HWCAP2_ONMUL): Likewise.
	(HWCAP2_ONDIV): Likewise.
	(HWCAP2_DICTUNP): Likewise.
	(HWCAP2_FPCMPSHL): Likewise.
	(HWCAP2_RLE): Likewise.
	(HWCAP2_SHA3): Likewise.
	(OPM): Likewise.
	(OPMI): Likewise.
	(ONFCN): Likewise.
	(REVFCN): Likewise.
	(SIMM10): Likewise.

opcodes/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
	(X_IMM2): Define.
	(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
	bfd_mach_sparc_v9m8.
	(print_insn_sparc): Handle new operand types.
	* sparc-opc.c (MASK_M8): Define.
	(v6): Add MASK_M8.
	(v6notlet): Likewise.
	(v7): Likewise.
	(v8): Likewise.
	(v9): Likewise.
	(v9a): Likewise.
	(v9b): Likewise.
	(v9c): Likewise.
	(v9d): Likewise.
	(v9e): Likewise.
	(v9v): Likewise.
	(v9m): Likewise.
	(v9andleon): Likewise.
	(m8): Define.
	(HWS_VM8): Define.
	(HWS2_VM8): Likewise.
	(sparc_opcode_archs): Add entry for "m8".
	(sparc_opcodes): Add OSA2017 and M8 instructions
	dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
	fpx{ll,ra,rl}64x,
	ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
	ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
	revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
	stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
	(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
	ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
	ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
	ASI_CORE_SELECT_COMMIT_NHT.
This commit is contained in:
Jose E. Marchesi 2017-05-19 09:27:08 -07:00
parent 92f7d783c1
commit 6451799480
43 changed files with 931 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

18
bfd/ChangeLog
View file

@ -1,3 +1,21 @@
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v9m8): Define.
(bfd_mach_sparc_v8plusm8): Likewise.
(bfd_mach_sparc_v9_p): Adjust to M8.
(bfd_mach_sparc_64bit_p): Likewise.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
bfd_mach_sparc_v8plusm8.
* bfd-in2.h: Regenerated.
* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
sparc:v8plusm8.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
SHA3.
* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
bfd_mach_sparc_v8plusm8.
2017-05-19 Alan Modra <amodra@gmail.com>
* elflink.c (_bfd_elf_gc_mark_extra_sections): Don't keep

4
bfd/aoutx.h
View file

@ -738,6 +738,7 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
|| machine == bfd_mach_sparc_v8pluse
|| machine == bfd_mach_sparc_v8plusv
|| machine == bfd_mach_sparc_v8plusm
|| machine == bfd_mach_sparc_v8plusm8
|| machine == bfd_mach_sparc_v9
|| machine == bfd_mach_sparc_v9a
|| machine == bfd_mach_sparc_v9b
@ -745,7 +746,8 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
|| machine == bfd_mach_sparc_v9d
|| machine == bfd_mach_sparc_v9e
|| machine == bfd_mach_sparc_v9v
|| machine == bfd_mach_sparc_v9m)
|| machine == bfd_mach_sparc_v9m
|| machine == bfd_mach_sparc_v9m8)
arch_flags = M_SPARC;
else if (machine == bfd_mach_sparc_sparclet)
arch_flags = M_SPARCLET;

7
bfd/archures.c
View file

@ -147,9 +147,11 @@ DESCRIPTION
.#define bfd_mach_sparc_v9v 18 {* with OSA2011 and T4 and IMA and FJMAU add'ns. *}
.#define bfd_mach_sparc_v8plusm 19 {* with OSA2015 and M7 add'ns. *}
.#define bfd_mach_sparc_v9m 20 {* with OSA2015 and M7 add'ns. *}
.#define bfd_mach_sparc_v8plusm8 21 {* with OSA2017 and M8 add'ns. *}
.#define bfd_mach_sparc_v9m8 22 {* with OSA2017 and M8 add'ns. *}
.{* Nonzero if MACH has the v9 instruction set. *}
.#define bfd_mach_sparc_v9_p(mach) \
. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m \
. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m8 \
. && (mach) != bfd_mach_sparc_sparclite_le)
.{* Nonzero if MACH is a 64 bit sparc architecture. *}
.#define bfd_mach_sparc_64bit_p(mach) \
@ -159,7 +161,8 @@ DESCRIPTION
. && (mach) != bfd_mach_sparc_v8plusd \
. && (mach) != bfd_mach_sparc_v8pluse \
. && (mach) != bfd_mach_sparc_v8plusv \
. && (mach) != bfd_mach_sparc_v8plusm)
. && (mach) != bfd_mach_sparc_v8plusm \
. && (mach) != bfd_mach_sparc_v8plusm8)
. bfd_arch_spu, {* PowerPC SPU *}
.#define bfd_mach_spu 256
. bfd_arch_mips, {* MIPS Rxxxx *}

7
bfd/bfd-in2.h
View file

@ -2004,9 +2004,11 @@ enum bfd_architecture
#define bfd_mach_sparc_v9v 18 /* with OSA2011 and T4 and IMA and FJMAU add'ns. */
#define bfd_mach_sparc_v8plusm 19 /* with OSA2015 and M7 add'ns. */
#define bfd_mach_sparc_v9m 20 /* with OSA2015 and M7 add'ns. */
#define bfd_mach_sparc_v8plusm8 21 /* with OSA2017 and M8 add'ns. */
#define bfd_mach_sparc_v9m8 22 /* with OSA2017 and M8 add'ns. */
/* Nonzero if MACH has the v9 instruction set. */
#define bfd_mach_sparc_v9_p(mach) \
((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m \
((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m8 \
&& (mach) != bfd_mach_sparc_sparclite_le)
/* Nonzero if MACH is a 64 bit sparc architecture. */
#define bfd_mach_sparc_64bit_p(mach) \
@ -2016,7 +2018,8 @@ enum bfd_architecture
&& (mach) != bfd_mach_sparc_v8plusd \
&& (mach) != bfd_mach_sparc_v8pluse \
&& (mach) != bfd_mach_sparc_v8plusv \
&& (mach) != bfd_mach_sparc_v8plusm)
&& (mach) != bfd_mach_sparc_v8plusm \
&& (mach) != bfd_mach_sparc_v8plusm8)
bfd_arch_spu, /* PowerPC SPU */
#define bfd_mach_spu 256
bfd_arch_mips, /* MIPS Rxxxx */

30
bfd/cpu-sparc.c
View file

@ -307,6 +307,36 @@ static const bfd_arch_info_type arch_info_struct[] =
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
&arch_info_struct[19],
},
{
32, /* bits in a word */
32, /* bits in an address */
8, /* bits in a byte */
bfd_arch_sparc,
bfd_mach_sparc_v8plusm8,
"sparc",
"sparc:v8plusm8",
3,
FALSE,
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
&arch_info_struct[20],
},
{
64, /* bits in a word */
64, /* bits in an address */
8, /* bits in a byte */
bfd_arch_sparc,
bfd_mach_sparc_v9m8,
"sparc",
"sparc:v9m8",
3,
FALSE,
bfd_default_compatible,
bfd_default_scan,
bfd_arch_default_fill,
0,
}
};

1
bfd/elf32-sparc.c
View file

@ -142,6 +142,7 @@ elf32_sparc_final_write_processing (bfd *abfd,
case bfd_mach_sparc_v8pluse :
case bfd_mach_sparc_v8plusv :
case bfd_mach_sparc_v8plusm :
case bfd_mach_sparc_v8plusm8 :
elf_elfheader (abfd)->e_machine = EM_SPARC32PLUS;
elf_elfheader (abfd)->e_flags &=~ EF_SPARC_32PLUS_MASK;
elf_elfheader (abfd)->e_flags |= EF_SPARC_32PLUS | EF_SPARC_SUN_US1

17
bfd/elfxx-sparc.c
View file

@ -5047,12 +5047,22 @@ _bfd_sparc_elf_object_p (bfd *abfd)
| ELF_SPARC_HWCAP2_MWAIT
| ELF_SPARC_HWCAP2_XMPMUL
| ELF_SPARC_HWCAP2_XMONT);
unsigned int m8_hwcaps2_mask = (ELF_SPARC_HWCAP2_SPARC6
| ELF_SPARC_HWCAP2_ONADDSUB
| ELF_SPARC_HWCAP2_ONMUL
| ELF_SPARC_HWCAP2_ONDIV
| ELF_SPARC_HWCAP2_DICTUNP
| ELF_SPARC_HWCAP2_FPCMPSHL
| ELF_SPARC_HWCAP2_RLE
| ELF_SPARC_HWCAP2_SHA3);
if (ABI_64_P (abfd))
{
unsigned long mach = bfd_mach_sparc_v9;
if (hwcaps2->i & v9m_hwcaps2_mask)
if (hwcaps2->i & m8_hwcaps2_mask)
mach = bfd_mach_sparc_v9m8;
else if (hwcaps2->i & v9m_hwcaps2_mask)
mach = bfd_mach_sparc_v9m;
else if (hwcaps->i & v9v_hwcaps_mask)
mach = bfd_mach_sparc_v9v;
@ -5072,7 +5082,10 @@ _bfd_sparc_elf_object_p (bfd *abfd)
{
if (elf_elfheader (abfd)->e_machine == EM_SPARC32PLUS)
{
if (hwcaps2->i & v9m_hwcaps2_mask)
if (hwcaps2->i & m8_hwcaps2_mask)
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
bfd_mach_sparc_v8plusm8);
else if (hwcaps2->i & v9m_hwcaps2_mask)
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
bfd_mach_sparc_v8plusm);
else if (hwcaps->i & v9v_hwcaps_mask)

4
binutils/ChangeLog
View file

@ -1,3 +1,7 @@
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* NEWS: Mention the SPARC M8 support.
2017-05-19 Maciej W. Rozycki <macro@imgtec.com>
* testsuite/binutils-all/mips/mips.exp: Bail out right away if

3
binutils/NEWS
View file

@ -1,5 +1,8 @@
-*- text -*-
* The SPARC port now supports the SPARC M8 processor, which implements the
Oracle SPARC Architecture 2017.
* The MIPS port now supports the MIPS16e2 ASE for assembly and disassembly.
* Add support for ELF SHF_GNU_MBIND and PT_GNU_MBIND_XXX.

35
gas/ChangeLog
View file

@ -1,3 +1,38 @@
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
`v9m8' and `v8plusm8'.
(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
(get_hwcap_name): Support the M8 hardware capabilities.
(sparc_ip): Handle new operand types.
* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
-Asparc6, and the corresponding -xarch aliases.
* testsuite/gas/sparc/sparc6.s: New file.
* testsuite/gas/sparc/sparc6.d: Likewise.
* testsuite/gas/sparc/sparc6-diag.s: Likewise.
* testsuite/gas/sparc/sparc6-diag.l: Likewise.
* testsuite/gas/sparc/fpcmpshl.s: Likewise.
* testsuite/gas/sparc/fpcmpshl.d: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
* testsuite/gas/sparc/ldm-stm.s: Likewise.
* testsuite/gas/sparc/ldm-stm.d: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
* testsuite/gas/sparc/on.s: Likewise.
* testsuite/gas/sparc/on.d: Likewise.
* testsuite/gas/sparc/on-diag.s: Likewise.
* testsuite/gas/sparc/on-diag.l: Likewise.
* testsuite/gas/sparc/rle.s: Likewise.
* testsuite/gas/sparc/rle.d: Likewise.
* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
* testsuite/gas/sparc/rdasr.d: Likewise.
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* testsuite/gas/sparc/call-relax.d: Support 32-bit targets.

74
gas/config/tc-sparc.c
View file

@ -256,6 +256,7 @@ static struct sparc_arch {
{ "sparc4", "v9v", v9, 0, 1, 0, 0 },
{ "sparc5", "v9m", v9, 0, 1, 0, 0 },
{ "sparc6", "m8", v9, 0, 1, 0, 0 },
{ "leon", "leon", leon, 32, 1, 0, 0 },
{ "sparclet", "sparclet", sparclet, 32, 1, 0, 0 },
@ -270,6 +271,7 @@ static struct sparc_arch {
{ "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS, 0 },
{ "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS, 0 },
{ "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS, 0 },
{ "v8plusm8", "m8", v9, 0, 1, HWCAP_V8PLUS, 0 },
{ "v9", "v9", v9, 0, 1, 0, 0 },
{ "v9a", "v9a", v9, 0, 1, 0, 0 },
@ -279,6 +281,7 @@ static struct sparc_arch {
{ "v9e", "v9e", v9, 0, 1, 0, 0 },
{ "v9v", "v9v", v9, 0, 1, 0, 0 },
{ "v9m", "v9m", v9, 0, 1, 0, 0 },
{ "v9m8", "m8", v9, 0, 1, 0, 0 },
/* This exists to allow configure.tgt to pass one
value to specify both the default machine and default word size. */
@ -1160,6 +1163,7 @@ sparc_md_end (void)
case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break;
case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break;
case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break;
case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v9m8; break;
default: mach = bfd_mach_sparc_v9; break;
}
else
@ -1174,6 +1178,7 @@ sparc_md_end (void)
case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break;
case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break;
case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break;
case SPARC_OPCODE_ARCH_M8: mach = bfd_mach_sparc_v8plusm8; break;
/* The sparclite is treated like a normal sparc. Perhaps it shouldn't
be but for now it is (since that's the way it's always been
treated). */
@ -1744,6 +1749,22 @@ get_hwcap_name (bfd_uint64_t mask)
return "xmont";
if (mask & HWCAP2_NSEC)
return "nsec";
if (mask & HWCAP2_SPARC6)
return "sparc6";
if (mask & HWCAP2_ONADDSUB)
return "onaddsub";
if (mask & HWCAP2_ONMUL)
return "onmul";
if (mask & HWCAP2_ONDIV)
return "ondiv";
if (mask & HWCAP2_DICTUNP)
return "dictunp";
if (mask & HWCAP2_FPCMPSHL)
return "fpcmpshl";
if (mask & HWCAP2_RLE)
return "rle";
if (mask & HWCAP2_SHA3)
return "sha3";
return "UNKNOWN";
}
@ -2532,10 +2553,13 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'e': /* next operand is a floating point register */
case 'v':
case 'V':
case ';':
case 'f':
case 'B':
case 'R':
case ':':
case '\'':
case '4':
case '5':
@ -2544,6 +2568,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'H':
case 'J':
case '}':
case '^':
{
char format;
@ -2562,6 +2587,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
|| *args == 'B'
|| *args == '5'
|| *args == 'H'
|| *args == '\''
|| format == 'd')
&& (mask & 1))
{
@ -2579,6 +2605,21 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
break;
}
if ((*args == ':'
|| *args == ';'
|| *args == '^')
&& (mask & 7))
{
/* register must be multiple of 8 */
break;
}
if (*args == '\'' && mask < 48)
{
/* register must be higher or equal than %f48 */
break;
}
if (mask >= 64)
{
if (SPARC_OPCODE_ARCH_V9_P (max_architecture))
@ -2624,15 +2665,21 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'v':
case 'V':
case 'e':
case ';':
opcode |= RS1 (mask);
continue;
case 'f':
case 'B':
case 'R':
case ':':
opcode |= RS2 (mask);
continue;
case '\'':
opcode |= RS2 (mask & 0xe);
continue;
case '4':
case '5':
opcode |= RS3 (mask);
@ -2642,6 +2689,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
case 'H':
case 'J':
case '}':
case '^':
opcode |= RD (mask);
continue;
} /* Pack it in. */
@ -3061,6 +3109,12 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
s += 7;
continue;
case '&':
if (strncmp (s, "%entropy", 8) != 0)
break;
s += 8;
continue;
case 'E':
if (strncmp (s, "%ccr", 4) != 0)
break;
@ -3079,6 +3133,26 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
s += 4;
continue;
case '|':
{
int imm2 = 0;
/* Parse a 2-bit immediate. */
if (! parse_const_expr_arg (&s, &imm2))
{
error_message = _(": non-immdiate imm2 operand");
goto error;
}
if ((imm2 & ~0x3) != 0)
{
error_message = _(": imm2 immediate operand out of range (0-3)");
goto error;
}
opcode |= ((imm2 & 0x2) << 3) | (imm2 & 0x1);
continue;
}
case 'x':
{
char *push = input_line_pointer;

28
gas/doc/c-sparc.texi
View file

@ -71,10 +71,11 @@ is explicitly requested. SPARC v9 is always incompatible with sparclite.
@kindex -Asparcvis3
@kindex -Asparcvis3r
@item -Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite
@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv | -Av8plusm
@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m
@itemx -Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd |
@itemx -Av8plusv | -Av8plusm | -Av8plusm8
@itemx -Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9e | -Av9v | -Av9m | -Av9m8
@itemx -Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima
@itemx -Asparcvis3 | -Asparcvis3r | -Asparc5
@itemx -Asparcvis3 | -Asparcvis3r | -Asparc5 | -Asparc6
Use one of the @samp{-A} options to select one of the SPARC
architectures explicitly. If you select an architecture explicitly,
@code{@value{AS}} reports a fatal error if it encounters an instruction
@ -113,6 +114,10 @@ enabled by @samp{-Av8pluse} and @samp{-Av9e}.
xmpmul, xmontmul and xmontsqr instructions, as well as the instructions
enabled by @samp{-Av8plusv} and @samp{-Av9v}.
@samp{-Av8plusm8} and @samp{-Av9m8} enable the instructions introduced
in the Oracle SPARC Architecture 2017 and the M8 processor, as
well as the instructions enabled by @samp{-Av8plusm} and @samp{-Av9m}.
@samp{-Asparc} specifies a v9 environment. It is equivalent to
@samp{-Av9} if the word size is 64-bit, and @samp{-Av8plus} otherwise.
@ -136,17 +141,22 @@ and floating point unfused multiply-add instructions enabled.
@samp{-Asparc5} is equivalent to @samp{-Av9m}.
@samp{-Asparc6} is equivalent to @samp{-Av9m8}.
@item -xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc
@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm | -xarch=v9 | -xarch=v9a
@itemx -xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v | -xarch=v9m
@itemx -xarch=v8plusd | -xarch=v8plusv | -xarch=v8plusm |
@itemx -xarch=v8plusm8 | -xarch=v9 | -xarch=v9a | -xarch=v9b
@itemx -xarch=v9c | -xarch=v9d | -xarch=v9e | -xarch=v9v
@itemx -xarch=v9m | -xarch=v9m8
@itemx -xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2
@itemx -xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3
@itemx -xarch=sparcvis3r | -xarch=sparc5
@itemx -xarch=sparcvis3r | -xarch=sparc5 | -xarch=sparc6
For compatibility with the SunOS v9 assembler. These options are
equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd,
-Av8plusv, -Av8plusm, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9e, -Av9v, -Av9m,
-Asparc, -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima,
-Asparcvis3, and -Asparcvis3r, respectively.
-Av8plusv, -Av8plusm, -Av8plusm8, -Av9, -Av9a, -Av9b, -Av9c, -Av9d,
-Av9e, -Av9v, -Av9m, -Av9m8, -Asparc, -Asparcvis, -Asparcvis2,
-Asparcfmaf, -Asparcima, -Asparcvis3, -Asparcvis3r, -Asparc5 and
-Asparc6 respectively.
@item -bump
Warn whenever it is necessary to switch to another level.

6
gas/testsuite/gas/sparc/fpcmpshl-diag.l Normal file
View file

@ -0,0 +1,6 @@
.*fpcmpshl-diag.s: Assembler messages:
.*fpcmpshl-diag.s:3: Error: Illegal operands: imm2 immediate operand out of range.*
.*fpcmpshl-diag.s:4: Error: Illegal operands
.*fpcmpshl-diag.s:5: Error: Illegal operands
.*fpcmpshl-diag.s:6: Error: Illegal operands
.*fpcmpshl-diag.s:7: Error: Illegal operands

7
gas/testsuite/gas/sparc/fpcmpshl-diag.s Normal file
View file

@ -0,0 +1,7 @@
# Diagnostic tests for FPCP{ULE8,UGT8,EQ8,NE}{8,16,32}SHL instructions.
.text
fpcmpule8shl %f32, %f48, 4, %g1 ! Overflow in imm2 operand.
fpcmpugt8shl %f33, %f50, 4, %g2 ! Invalid frs1.
fpcmpeq8shl %f36, %f53, 4, %g3 ! Invalid frs2.
fpcmpne8shl %f38, %f46, 4, %g4 ! Likewise.
fpcmpule16shl %f32, %f0, 4, %g1 ! Likewise.

27
gas/testsuite/gas/sparc/fpcmpshl.d Normal file
View file

@ -0,0 +1,27 @@
#as: -Av9m8
#objdump: -dr
#name: FPCMPSHL OSA2017 instructions
.*: +file format .*sparc.*
Disassembly of section .text:
0+ <.text>:
0: 83 b0 72 00 fpcmpule8shl %f32, %f48, 0, %g1
4: 85 b0 f2 23 fpcmpugt8shl %f34, %f50, 1, %g2
8: 87 b1 72 54 fpcmpeq8shl %f36, %f52, 2, %g3
c: 89 b1 f2 7f fpcmpne8shl %f38, %f62, 3, %g4
10: 83 b0 72 80 fpcmpule16shl %f32, %f48, 0, %g1
14: 85 b0 f2 a3 fpcmpugt16shl %f34, %f50, 1, %g2
18: 87 b1 72 d4 fpcmpeq16shl %f36, %f52, 2, %g3
1c: 89 b1 f2 ff fpcmpne16shl %f38, %f62, 3, %g4$
20: 83 b0 73 00 fpcmpule32shl %f32, %f48, 0, %g1
24: 85 b0 f3 23 fpcmpugt32shl %f34, %f50, 1, %g2
28: 87 b1 73 54 fpcmpeq32shl %f36, %f52, 2, %g3
2c: 89 b1 f3 7f fpcmpne32shl %f38, %f62, 3, %g4
30: 83 b0 48 a0 fpcmpde8shl %f32, %f48, 0, %g1
34: 85 b0 c8 e3 fpcmpde16shl %f34, %f50, 1, %g2
38: 87 b1 49 54 fpcmpde32shl %f36, %f52, 2, %g3
3c: 83 b0 73 80 fpcmpur8shl %f32, %f48, 0, %g1
40: 85 b0 f3 a3 fpcmpur16shl %f34, %f50, 1, %g2
44: 87 b1 73 d4 fpcmpur32shl %f36, %f52, 2, %g3

19
gas/testsuite/gas/sparc/fpcmpshl.s Normal file
View file

@ -0,0 +1,19 @@
# Test FPCMP{ULE8,UGT8,EQ8,NE,DE,UR}{8,16,32}SHL instructions.
fpcmpule8shl %f32, %f48, 0, %g1
fpcmpugt8shl %f34, %f50, 1, %g2
fpcmpeq8shl %f36, %f52, 2, %g3
fpcmpne8shl %f38, %f62, 3, %g4
fpcmpule16shl %f32, %f48, 0x0, %g1
fpcmpugt16shl %f34, %f50, 0x1, %g2
fpcmpeq16shl %f36, %f52, 0x2, %g3
fpcmpne16shl %f38, %f62, 0x3, %g4
fpcmpule32shl %f32, %f48, 0, %g1
fpcmpugt32shl %f34, %f50, 2-1, %g2
fpcmpeq32shl %f36, %f52, 4/2, %g3
fpcmpne32shl %f38, %f62, 3*1, %g4
fpcmpde8shl %f32, %f48, 0, %g1
fpcmpde16shl %f34, %f50, 1, %g2
fpcmpde32shl %f36, %f52, 2, %g3
fpcmpur8shl %f32, %f48, 0, %g1
fpcmpur16shl %f34, %f50, 1, %g2
fpcmpur32shl %f36, %f52, 2, %g3

3
gas/testsuite/gas/sparc/ldm-stm-diag.l Normal file
View file

@ -0,0 +1,3 @@
.*ldm-stm-diag.s: Assembler messages:
.*ldm-stm-diag.s:3: Error: relocation overflow
.*ldm-stm-diag.s:4: Error: relocation overflow

4
gas/testsuite/gas/sparc/ldm-stm-diag.s Normal file
View file

@ -0,0 +1,4 @@
# Diagnostic tests for ldm/stm/ldma/stma
.text
ldmsh [%g1+0x401], %g2 ! Overflow in simm10 constant.
stmh %g2, [%g1+0x401] ! Likewise.

70
gas/testsuite/gas/sparc/ldm-stm.d Normal file
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@ -0,0 +1,70 @@
#as: -Av9m8
#objdump: -dr
#name: sparc LDM/STM/LDMA/STMA
.*: +file format .*
Disassembly of section .text:
0+ <.text>:
0: c5 88 00 01 ldmsh \[ %g0 \+ %g1 \], %g2
4: c7 88 40 00 ldmsh \[ %g1 \], %g3
8: c7 88 60 66 ldmsh \[ %g1 \+ 0x66 \], %g3
c: c7 88 60 66 ldmsh \[ %g1 \+ 0x66 \], %g3
10: c7 88 20 66 ldmsh \[ 0x66 \], %g3
14: c5 88 04 01 ldmuh \[ %g0 \+ %g1 \], %g2
18: c7 88 44 00 ldmuh \[ %g1 \], %g3
1c: c7 88 64 66 ldmuh \[ %g1 \+ 0x66 \], %g3
20: c7 88 64 66 ldmuh \[ %g1 \+ 0x66 \], %g3
24: c7 88 24 66 ldmuh \[ 0x66 \], %g3
28: c5 88 08 01 ldmsw \[ %g0 \+ %g1 \], %g2
2c: c7 88 48 00 ldmsw \[ %g1 \], %g3
30: c7 88 68 66 ldmsw \[ %g1 \+ 0x66 \], %g3
34: c7 88 68 66 ldmsw \[ %g1 \+ 0x66 \], %g3
38: c7 88 28 66 ldmsw \[ 0x66 \], %g3
3c: c5 88 0c 01 ldmuw \[ %g0 \+ %g1 \], %g2
40: c7 88 4c 00 ldmuw \[ %g1 \], %g3
44: c7 88 6c 66 ldmuw \[ %g1 \+ 0x66 \], %g3
48: c7 88 6c 66 ldmuw \[ %g1 \+ 0x66 \], %g3
4c: c7 88 2c 66 ldmuw \[ 0x66 \], %g3
50: c5 88 14 01 ldmx \[ %g0 \+ %g1 \], %g2
54: c7 88 54 00 ldmx \[ %g1 \], %g3
58: c7 88 74 66 ldmx \[ %g1 \+ 0x66 \], %g3
5c: c7 88 74 66 ldmx \[ %g1 \+ 0x66 \], %g3
60: c7 88 34 66 ldmx \[ 0x66 \], %g3
64: c5 88 14 01 ldmx \[ %g0 \+ %g1 \], %g2
68: c7 88 54 00 ldmx \[ %g1 \], %g3
6c: c7 88 74 66 ldmx \[ %g1 \+ 0x66 \], %g3
70: c7 88 74 66 ldmx \[ %g1 \+ 0x66 \], %g3
74: c7 88 34 66 ldmx \[ 0x66 \], %g3
78: c7 88 42 02 ldmsha \[ %g1 \+ %g2 \] %asi, %g3
7c: c5 88 42 00 ldmsha \[ %g1 \] %asi, %g2
80: c7 88 46 02 ldmuha \[ %g1 \+ %g2 \] %asi, %g3
84: c5 88 46 00 ldmuha \[ %g1 \] %asi, %g2
88: c7 88 4a 02 ldmswa \[ %g1 \+ %g2 \] %asi, %g3
8c: c5 88 4a 00 ldmswa \[ %g1 \] %asi, %g2
90: c7 88 4e 02 ldmuwa \[ %g1 \+ %g2 \] %asi, %g3
94: c5 88 4e 00 ldmuwa \[ %g1 \] %asi, %g2
98: c7 88 56 02 ldmxa \[ %g1 \+ %g2 \] %asi, %g3
9c: c5 88 56 00 ldmxa \[ %g1 \] %asi, %g2
a0: c5 a8 04 01 stmh %g2, \[ %g0 \+ %g1 \]
a4: c7 a8 44 00 stmh %g3, \[ %g1 \]
a8: c7 a8 64 66 stmh %g3, \[ %g1 \+ 0x66 \]
ac: c7 a8 64 66 stmh %g3, \[ %g1 \+ 0x66 \]
b0: c7 a8 24 66 stmh %g3, \[ 0x66 \]
b4: c5 a8 0c 01 stmw %g2, \[ %g0 \+ %g1 \]
b8: c7 a8 4c 00 stmw %g3, \[ %g1 \]
bc: c7 a8 6c 66 stmw %g3, \[ %g1 \+ 0x66 \]
c0: c7 a8 6c 66 stmw %g3, \[ %g1 \+ 0x66 \]
c4: c7 a8 2c 66 stmw %g3, \[ 0x66 \]
c8: c5 a8 14 01 stmx %g2, \[ %g0 \+ %g1 \]
cc: c7 a8 54 00 stmx %g3, \[ %g1 \]
d0: c7 a8 74 66 stmx %g3, \[ %g1 \+ 0x66 \]
d4: c7 a8 74 66 stmx %g3, \[ %g1 \+ 0x66 \]
d8: c7 a8 34 66 stmx %g3, \[ 0x66 \]
dc: c5 a8 06 01 stmha %g2, \[ %g0 \+ %g1 \] %asi
e0: c7 a8 46 00 stmha %g3, \[ %g1 \] %asi
e4: c5 a8 0e 01 stmwa %g2, \[ %g0 \+ %g1 \] %asi
e8: c7 a8 4e 00 stmwa %g3, \[ %g1 \] %asi
ec: c5 a8 16 01 stmxa %g2, \[ %g0 \+ %g1 \] %asi
f0: c7 a8 56 00 stmxa %g3, \[ %g1 \] %asi

63
gas/testsuite/gas/sparc/ldm-stm.s Normal file
View file

@ -0,0 +1,63 @@
# Test ldm/stm/ldma/stma
.text
ldmsh [%g0+%g1], %g2
ldmsh [%g1], %g3
ldmsh [%g1+102], %g3
ldmsh [102+%g1], %g3
ldmsh [102], %g3
ldmuh [%g0+%g1], %g2
ldmuh [%g1], %g3
ldmuh [%g1+102], %g3
ldmuh [102+%g1], %g3
ldmuh [102], %g3
ldmsw [%g0+%g1], %g2
ldmsw [%g1], %g3
ldmsw [%g1+102], %g3
ldmsw [102+%g1], %g3
ldmsw [102], %g3
ldmuw [%g0+%g1], %g2
ldmuw [%g1], %g3
ldmuw [%g1+102], %g3
ldmuw [102+%g1], %g3
ldmuw [102], %g3
ldmx [%g0+%g1], %g2
ldmx [%g1], %g3
ldmx [%g1+102], %g3
ldmx [102+%g1], %g3
ldmx [102], %g3
ldmux [%g0+%g1], %g2
ldmux [%g1], %g3
ldmux [%g1+102], %g3
ldmux [102+%g1], %g3
ldmux [102], %g3
ldmsha [%g1+%g2] %asi, %g3
ldmsha [%g1] %asi, %g2
ldmuha [%g1+%g2] %asi, %g3
ldmuha [%g1] %asi, %g2
ldmswa [%g1+%g2] %asi, %g3
ldmswa [%g1] %asi, %g2
ldmuwa [%g1+%g2] %asi, %g3
ldmuwa [%g1] %asi, %g2
ldmxa [%g1+%g2] %asi, %g3
ldmxa [%g1] %asi, %g2
stmh %g2, [%g0+%g1]
stmh %g3, [%g1]
stmh %g3, [%g1+102]
stmh %g3, [102+%g1]
stmh %g3, [102]
stmw %g2, [%g0+%g1]
stmw %g3, [%g1]
stmw %g3, [%g1+102]
stmw %g3, [102+%g1]
stmw %g3, [102]
stmx %g2, [%g0+%g1]
stmx %g3, [%g1]
stmx %g3, [%g1+102]
stmx %g3, [102+%g1]
stmx %g3, [102]
stmha %g2, [%g0+%g1] %asi
stmha %g3, [%g1] %asi
stmwa %g2, [%g0+%g1] %asi
stmwa %g3, [%g1] %asi
stmxa %g2, [%g0+%g1] %asi
stmxa %g3, [%g1] %asi

11
gas/testsuite/gas/sparc/ldmf-stmf-diag.l Normal file
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@ -0,0 +1,11 @@
.*ldmf-stmf-diag.s: Assembler messages:
.*ldmf-stmf-diag.s:7: Error: Illegal operands
.*ldmf-stmf-diag.s:12: Error: Illegal operands
.*ldmf-stmf-diag.s:3: Error: relocation overflow
.*ldmf-stmf-diag.s:4: Error: relocation overflow
.*ldmf-stmf-diag.s:5: Error: relocation overflow
.*ldmf-stmf-diag.s:6: Error: relocation overflow
.*ldmf-stmf-diag.s:8: Error: relocation overflow
.*ldmf-stmf-diag.s:9: Error: relocation overflow
.*ldmf-stmf-diag.s:10: Error: relocation overflow
.*ldmf-stmf-diag.s:11: Error: relocation overflow

12
gas/testsuite/gas/sparc/ldmf-stmf-diag.s Normal file
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@ -0,0 +1,12 @@
# Diagnostic tests for ldmf/stmf/ldmfa/stmfs
.text
ldmfs [%g1+0x401], %f1 ! Overflow in simm10 constant.
ldmfs [0x401], %f1 ! Likewise.
ldmfd [%g1+0x401], %f2 ! Likewise.
ldmfd [0x401], %f2 ! Likewise.
ldmfd [%g1+%g2], %f1 ! Invalid frd.
stmfs %f1, [%g1+0x401] ! Overflow in simm10 constant.
stmfs %f1, [0x401] ! Likewise.
stmfd %f2, [%g1+0x401] ! Likewise.
stmfd %f2, [0x401] ! Likewise.
stmfd %f1, [%g1+%g2] ! Invalid frd.

37
gas/testsuite/gas/sparc/ldmf-stmf.d Normal file
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@ -0,0 +1,37 @@
#as: -Av9m8
#objdump: -dr
#name: sparc LDMF/STMF/LDMFA/STMFA
.*: +file format .*
Disassembly of section .text:
0+ <.text>:
0: c3 88 18 01 ldmfs \[ %g0 \+ %g1 \], %f1
4: c3 88 58 00 ldmfs \[ %g1 \], %f1
8: c3 88 78 66 ldmfs \[ %g1 \+ 0x66 \], %f1
c: c3 88 78 66 ldmfs \[ %g1 \+ 0x66 \], %f1
10: c3 88 38 66 ldmfs \[ 0x66 \], %f1
14: c3 88 1c 01 ldmfd \[ %g0 \+ %g1 \], %f32
18: c3 88 5c 00 ldmfd \[ %g1 \], %f32
1c: c3 88 7c 66 ldmfd \[ %g1 \+ 0x66 \], %f32
20: c3 88 7c 66 ldmfd \[ %g1 \+ 0x66 \], %f32
24: c3 88 3c 66 ldmfd \[ 0x66 \], %f32
28: c3 88 1a 01 ldmfsa \[ %g0 \+ %g1 \] %asi, %f1
2c: c3 88 5a 00 ldmfsa \[ %g1 \] %asi, %f1
30: c3 88 1e 01 ldmfda \[ %g0 \+ %g1 \] %asi, %f32
34: c3 88 5e 00 ldmfda \[ %g1 \] %asi, %f32
38: c3 a8 18 01 stmfs %f1, \[ %g0 \+ %g1 \]
3c: c3 a8 58 00 stmfs %f1, \[ %g1 \]
40: c3 a8 78 66 stmfs %f1, \[ %g1 \+ 0x66 \]
44: c3 a8 78 66 stmfs %f1, \[ %g1 \+ 0x66 \]
48: c3 a8 38 66 stmfs %f1, \[ 0x66 \]
4c: c3 a8 1c 01 stmfd %f32, \[ %g0 \+ %g1 \]
50: c3 a8 5c 00 stmfd %f32, \[ %g1 \]
54: c3 a8 7c 66 stmfd %f32, \[ %g1 \+ 0x66 \]
58: c3 a8 7c 66 stmfd %f32, \[ %g1 \+ 0x66 \]
5c: c3 a8 3c 66 stmfd %f32, \[ 0x66 \]
60: c3 a8 1a 01 stmfsa %f1, \[ %g0 \+ %g1 \] %asi
64: c3 a8 5a 00 stmfsa %f1, \[ %g1 \] %asi
68: c3 a8 1e 01 stmfda %f32, \[ %g0 \+ %g1 \] %asi
6c: c3 a8 5e 00 stmfda %f32, \[ %g1 \] %asi

31
gas/testsuite/gas/sparc/ldmf-stmf.s Normal file
View file

@ -0,0 +1,31 @@
# Test ldmf/stmf/ldmfa/stmfa
.text
ldmfs [%g0+%g1], %f1
ldmfs [%g1], %f1
ldmfs [%g1+102], %f1
ldmfs [102+%g1], %f1
ldmfs [102], %f1
ldmfd [%g0+%g1], %f32
ldmfd [%g1], %f32
ldmfd [%g1+102], %f32
ldmfd [102+%g1], %f32
ldmfd [102], %f32
ldmfsa [%g0+%g1] %asi, %f1
ldmfsa [%g1] %asi, %f1
ldmfda [%g0+%g1] %asi, %f32
ldmfda [%g1] %asi, %f32
stmfs %f1, [%g0+%g1]
stmfs %f1, [%g1]
stmfs %f1, [%g1+102]
stmfs %f1, [102+%g1]
stmfs %f1, [102]
stmfd %f32, [%g0+%g1]
stmfd %f32, [%g1]
stmfd %f32, [%g1+102]
stmfd %f32, [102+%g1]
stmfd %f32, [102]
stmfsa %f1, [%g0+%g1] %asi
stmfsa %f1, [%g1] %asi
stmfda %f32, [%g0+%g1] %asi
stmfda %f32, [%g1] %asi

5
gas/testsuite/gas/sparc/on-diag.l Normal file
View file

@ -0,0 +1,5 @@
.*on-diag.s: Assembler messages:
.*on-diag.s:3: Error: Illegal operands
.*on-diag.s:4: Error: Illegal operands
.*on-diag.s:5: Error: Illegal operands
.*on-diag.s:6: Error: Illegal operands

6
gas/testsuite/gas/sparc/on-diag.s Normal file
View file

@ -0,0 +1,6 @@
# Diagnostic tests for ON instructions
.text
onadd %f1, %f8, %f16 ! Invalid frs1
onsub %f8, %f17, %f24 ! Invalid frs2
onmul %f32, %f24, %f17 ! Invalid frd
ondiv %f32, %f24, %f1 ! Likewise.

13
gas/testsuite/gas/sparc/on.d Normal file
View file

@ -0,0 +1,13 @@
#as: -Av9m8
#objdump: -dr
#name: OSA2017 ONADD/ONSUB/ONMUL/ONDIV instructions.
.*: +file format .*
Disassembly of section .text:
0+ <.text>:
0: a1 b0 02 a8 onadd %f0, %f8, %f16
4: b5 b2 02 b0 onsub %f8, %f16, %f24
8: a9 b0 42 b8 onmul %f32, %f24, %f16
c: 9d b2 02 a0 ondiv %f8, %f0, %f8

6
gas/testsuite/gas/sparc/on.s Normal file
View file

@ -0,0 +1,6 @@
# Test onadd/onsub/onmul/ondiv
.text
onadd %f0, %f8, %f16
onsub %f8, %f16, %f24
onmul %f32, %f24, %f16
ondiv %f8, %f0, %f8

3
gas/testsuite/gas/sparc/rdasr.d
View file

@ -1,4 +1,4 @@
#as: -64 -Av9m
#as: -64 -Av9m8
#objdump: -dr
#name: sparc64 rdasr
@ -16,3 +16,4 @@ Disassembly of section .text:
18: 8b 46 00 00 rd %stick, %g5
1c: 89 46 40 00 rd %stick_cmpr, %g4
20: 8d 46 80 00 rd %cfr, %g6
24: 85 43 40 00 rd %entropy, %g2

1
gas/testsuite/gas/sparc/rdasr.s
View file

@ -9,3 +9,4 @@
rd %sys_tick,%g5
rd %sys_tick_cmpr,%g4
rd %cfr,%g6
rd %entropy,%g2

12
gas/testsuite/gas/sparc/rle.d Normal file
View file

@ -0,0 +1,12 @@
#as: -Av9m8
#objdump: -dr
#name: OSA2017 RLE instructions
.*: +file format .*sparc.*
Disassembly of section .text:
0+ <.text>:
0: 87 b0 46 02 rle_burst %g1, %g2, %g3
4: 85 b0 06 41 rle_length %g1, %g2

4
gas/testsuite/gas/sparc/rle.s Normal file
View file

@ -0,0 +1,4 @@
# OSA2017 RLE instructions
.text
rle_burst %g1, %g2, %g3
rle_length %g1, %g2

11
gas/testsuite/gas/sparc/sparc.exp
View file

@ -73,6 +73,17 @@ if [istarget sparc*-*-*] {
run_dump_test "imm-plus-rreg"
run_dump_test "dcti-couples-v9"
run_dump_test "call-relax"
run_dump_test "sparc6"
run_list_test "sparc6-diag" "-64"
run_dump_test "fpcmpshl"
run_list_test "fpcmpshl-diag" "-64"
run_dump_test "ldm-stm"
run_list_test "ldm-stm-diag" "-64"
run_dump_test "ldmf-stmf"
run_list_test "ldmf-stmf-diag" "-64"
run_dump_test "on"
run_list_test "on-diag" "-64"
run_dump_test "rle"
} else {
# The next tests are a.out only.
run_dump_test "call-relax-aout"

7
gas/testsuite/gas/sparc/sparc6-diag.l Normal file
View file

@ -0,0 +1,7 @@
.*sparc6-diag.s: Assembler messages:
.*sparc6-diag.s:4: Error: Illegal operands
.*sparc6-diag.s:5: Error: Illegal operands
.*sparc6-diag.s:6: Error: Illegal operands
.*sparc6-diag.s:7: Error: Illegal operands
.*sparc6-diag.s:8: Error: Illegal operands
.*sparc6-diag.s:3: Error: relocation overflow

8
gas/testsuite/gas/sparc/sparc6-diag.s Normal file
View file

@ -0,0 +1,8 @@
# Test error detection and reporting in SPARC6 instructions.
.text
dictunpack %f32, 100, %f34 ! Too big immediate.
dictunpack %f1, 10, %f32 ! rs1 is not a double fp-register
dictunpack %32, 10, %f5 ! rd is not a double fp-register
fpsll64x %f31, %f34, %f36 ! rs1 is not a double fp-register
fpsra64x %f32, %f33, %f36 ! rs2 is not a double fp-register
fpsrl64x %f32, %f34, %f1 ! rd is not a double fp-register

18
gas/testsuite/gas/sparc/sparc6.d Normal file
View file

@ -0,0 +1,18 @@
#as: -Av9m8
#objdump: -dr
#name: SPARC6
.*: +file format .*sparc.*
Disassembly of section .text:
0+ <.text>:
0: 87 b0 43 8a dictunpack %f32, 0xa, %f34
4: 8b b0 60 c3 fpsll64x %f32, %f34, %f36
8: 97 b1 e1 e9 fpsra64x %f38, %f40, %f42
c: a7 b3 60 f1 fpsrl64x %f44, %f48, %f50
10: 85 b0 43 c0 revbitsb %g1, %g2
14: 89 b0 c3 c1 revbytesh %g3, %g4
18: 8d b1 43 c2 revbytesw %g5, %g6
1c: 89 b0 83 c3 revbytesx %g2, %g4
20: 81 b0 28 80 sha3

11
gas/testsuite/gas/sparc/sparc6.s Normal file
View file

@ -0,0 +1,11 @@
# Test SPARC6 instructions
.text
dictunpack %f32, 10, %f34
fpsll64x %f32, %f34, %f36
fpsra64x %f38, %f40, %f42
fpsrl64x %f44, %f48, %f50
revbitsb %g1, %g2
revbytesh %g3, %g4
revbytesw %g5, %g6
revbytesx %g2, %g4
sha3

26
include/ChangeLog
View file

@ -1,3 +1,29 @@
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
(ELF_SPARC_HWCAP2_ONMUL): Likewise.
(ELF_SPARC_HWCAP2_ONDIV): Likewise.
(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
(ELF_SPARC_HWCAP2_RLE): Likewise.
(ELF_SPARC_HWCAP2_SHA3): Likewise.
* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
and adjust SPARC_OPCODE_ARCH_MAX.
(HWCAP2_SPARC6): Define.
(HWCAP2_ONADDSUB): Likewise.
(HWCAP2_ONMUL): Likewise.
(HWCAP2_ONDIV): Likewise.
(HWCAP2_DICTUNP): Likewise.
(HWCAP2_FPCMPSHL): Likewise.
(HWCAP2_RLE): Likewise.
(HWCAP2_SHA3): Likewise.
(OPM): Likewise.
(OPMI): Likewise.
(ONFCN): Likewise.
(REVFCN): Likewise.
(SIMM10): Likewise.
2017-05-16 Alan Modra <amodra@gmail.com>
* bfdlink.h (struct bfd_link_hash_entry <non_ir_ref>): Rename to

9
include/elf/sparc.h
View file

@ -249,4 +249,13 @@ enum
#define ELF_SPARC_HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
#define ELF_SPARC_HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
#define ELF_SPARC_HWCAP2_SPARC6 0x00020000 /* OSA2017 new instructions */
#define ELF_SPARC_HWCAP2_ONADDSUB 0x00040000 /* Oracle Number add/subtract */
#define ELF_SPARC_HWCAP2_ONMUL 0x00080000 /* Oracle Number multiply */
#define ELF_SPARC_HWCAP2_ONDIV 0x00100000 /* Oracle Number divide */
#define ELF_SPARC_HWCAP2_DICTUNP 0x00200000 /* Dictionary unpack instruction */
#define ELF_SPARC_HWCAP2_FPCMPSHL 0x00400000 /* Partition compare with shifted result */
#define ELF_SPARC_HWCAP2_RLE 0x00800000 /* Run-length encoded burst and length */
#define ELF_SPARC_HWCAP2_SHA3 0x01000000 /* SHA3 instruction */
#endif /* _ELF_SPARC_H */

25
include/opcode/sparc.h
View file

@ -58,7 +58,8 @@ enum sparc_opcode_arch_val
SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer
multiply and Fujitsu fp multiply-add. */
SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */
SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_V9M,
SPARC_OPCODE_ARCH_M8, /* V9 with OSA2017 and M8 additions. */
SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_M8,
SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
};
@ -184,6 +185,15 @@ typedef struct
#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
#define HWCAP2_SPARC6 0x00020000 /* OSA2017 new instructions */
#define HWCAP2_ONADDSUB 0x00040000 /* Oracle Number add/subtract */
#define HWCAP2_ONMUL 0x00080000 /* Oracle Number multiply */
#define HWCAP2_ONDIV 0x00100000 /* Oracle Number divide */
#define HWCAP2_DICTUNP 0x00200000 /* Dictionary unpack instruction */
#define HWCAP2_FPCMPSHL 0x00400000 /* Partition compare with shifted result */
#define HWCAP2_RLE 0x00800000 /* Run-length encoded burst and length */
#define HWCAP2_SHA3 0x01000000 /* SHA3 instruction */
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
@ -202,15 +212,19 @@ typedef struct
e frs1 floating point register.
v frs1 floating point register (double/even).
V frs1 floating point register (quad/multiple of 4).
; frs1 floating piont register (multiple of 8).
f frs2 floating point register.
B frs2 floating point register (double/even).
R frs2 floating point register (quad/multiple of 4).
: frs2 floating point register (multiple of 8).
' rs2m floating point register (double/even) in FPCMPSHL. (m8)
4 frs3 floating point register.
5 frs3 floating point register (doube/even).
g frsd floating point register.
H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4).
} frsd floating point register (double/even) that is == frs2
^ frsd floating piont register in ON instructions.
b crs1 coprocessor register
c crs2 coprocessor register
D crsd coprocessor register
@ -253,6 +267,7 @@ typedef struct
P %pc. (v9)
W %tick. (v9)
{ %mcdper. (v9b)
& %entropy. (m8)
o %asi. (v9)
6 %fcc0. (v9)
7 %fcc1. (v9)
@ -269,7 +284,8 @@ typedef struct
/ Ancillary state register in rs1 (v9a)
( entire floating point state register (%efsr)
) 5 bit immediate placed in RS3 field
= 2+8 bit PC relative immediate. (v9) */
= 2+8 bit PC relative immediate. (v9)
| FPCMPSHL 2 bit immediate. (m8) */
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
@ -277,6 +293,10 @@ typedef struct
#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
#define OPM(x) (((x) & 0x7) << 10) /* opm field of misaligned load/store insns. */
#define OPMI(x) (((x) & 0x1) << 9) /* opm i field of misaligned load/store insns. */
#define ONFCN(x) (((x) & 0x3) << 26) /* fcn field of Oracle Number insns. */
#define REVFCN(x) (((x) & 0x3) << 0) /* fcn field of REV* insns. */
#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
#define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
@ -287,6 +307,7 @@ typedef struct
#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
#define SIMM10(x) ((x) & 0x3ff) /* Simm10 field. */
#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */

37
opcodes/ChangeLog
View file

@ -1,3 +1,40 @@
2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
(X_IMM2): Define.
(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
bfd_mach_sparc_v9m8.
(print_insn_sparc): Handle new operand types.
* sparc-opc.c (MASK_M8): Define.
(v6): Add MASK_M8.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Likewise.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(v9andleon): Likewise.
(m8): Define.
(HWS_VM8): Define.
(HWS2_VM8): Likewise.
(sparc_opcode_archs): Add entry for "m8".
(sparc_opcodes): Add OSA2017 and M8 instructions
dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
fpx{ll,ra,rl}64x,
ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
ASI_CORE_SELECT_COMMIT_NHT.
2017-05-18 Alan Modra <amodra@gmail.com>
* aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.

26
opcodes/sparc-dis.c
View file

@ -33,7 +33,8 @@
| (1 << SPARC_OPCODE_ARCH_V9D) \
| (1 << SPARC_OPCODE_ARCH_V9E) \
| (1 << SPARC_OPCODE_ARCH_V9V) \
| (1 << SPARC_OPCODE_ARCH_V9M))
| (1 << SPARC_OPCODE_ARCH_V9M) \
| (1 << SPARC_OPCODE_ARCH_M8))
/* 1 if INSN is for v9 only. */
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
/* 1 if INSN is for v9. */
@ -128,6 +129,7 @@ static char *v9a_asr_reg_names[] =
#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
#define X_IMM22(i) X_DISP22 (i)
#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
#define X_IMM2(i) (((i & 0x10) >> 3) | (i & 0x1))
/* These are for v9. */
#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
@ -261,6 +263,9 @@ compute_arch_mask (unsigned long mach)
case bfd_mach_sparc_v8plusm :
case bfd_mach_sparc_v9m :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
case bfd_mach_sparc_v8plusm8 :
case bfd_mach_sparc_v9m8 :
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8);
}
abort ();
}
@ -653,6 +658,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break;
case 'v': /* Double/even. */
case 'V': /* Quad/multiple of 4. */
case ';': /* Double/even multiple of 8 doubles. */
fregx (X_RS1 (insn));
break;
@ -661,6 +667,7 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
break;
case 'B': /* Double/even. */
case 'R': /* Quad/multiple of 4. */
case ':': /* Double/even multiple of 8 doubles. */
fregx (X_RS2 (insn));
break;
@ -679,6 +686,15 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
case '}': /* Double/even. */
fregx (X_RD (insn));
break;
case '^': /* Double/even multiple of 8 doubles. */
fregx (X_RD (insn) & ~0x6);
break;
case '\'': /* Double/even in FPCMPSHL. */
fregx (X_RS2 (insn | 0x11));
break;
#undef freg
#undef fregx
@ -818,6 +834,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
(*info->fprintf_func) (stream, "%%mcdper");
break;
case '&':
(*info->fprintf_func) (stream, "%%entropy");
break;
case 'o':
(*info->fprintf_func) (stream, "%%asi");
break;
@ -969,6 +989,10 @@ print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
+ X_ASI (insn)));
break;
case '|': /* 2-bit immediate */
(*info->fprintf_func) (stream, "%ld", X_IMM2 (insn));
break;
case 'y':
(*info->fprintf_func) (stream, "%%y");
break;

217
opcodes/sparc-opc.c
View file

@ -42,20 +42,24 @@
#define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)
#define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)
#define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)
#define MASK_M8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8)
/* Bit masks of architectures supporting the insn. */
#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
| MASK_SPARCLET | MASK_SPARCLITE \
| MASK_V9 | MASK_V9A | MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
/* v6 insns not supported on the sparclet. */
#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
#define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
/* Although not all insns are implemented in hardware, sparclite is defined
to be a superset of v8. Unimplemented insns trap and are then theoretically
implemented in software.
@ -64,26 +68,32 @@
recognizes all v8 insns. */
#define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
| MASK_V9 | MASK_V9A | MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
#define sparclet (MASK_SPARCLET)
/* sparclet insns supported by leon. */
#define letandleon (MASK_SPARCLET | MASK_LEON)
#define sparclite (MASK_SPARCLITE)
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
/* v9 insns supported by leon. */
#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_LEON)
| MASK_M8 | MASK_LEON)
#define v9a (MASK_V9A | MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
#define v9b (MASK_V9B \
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
#define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
#define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
#define v9e (MASK_V9E | MASK_V9V | MASK_V9M)
#define v9v (MASK_V9V | MASK_V9M)
#define v9m (MASK_V9M)
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
#define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
| MASK_M8)
#define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8)
#define v9e (MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8)
#define v9v (MASK_V9V | MASK_V9M | MASK_M8)
#define v9m (MASK_V9M | MASK_M8)
#define m8 (MASK_M8)
/* v6 insns not supported by v9. */
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
@ -106,10 +116,15 @@
| HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
#define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
#define HWS_VM HWS_VV
#define HWS_VM8 HWS_VM
#define HWS2_VM \
HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
| HWCAP2_XMPMUL | HWCAP2_XMONT
#define HWS2_VM8 HWS2_VM \
| HWCAP2_SPARC6 | HWCAP2_ONADDSUB | HWCAP2_ONMUL | HWCAP2_ONDIV \
| HWCAP2_DICTUNP | HWCAP2_FPCMPSHL | HWCAP2_RLE | HWCAP2_SHA3
/* Table of opcode architectures.
The order is defined in opcode/sparc.h. */
@ -144,6 +159,10 @@ const struct sparc_opcode_arch sparc_opcode_archs[] =
/* v9 with OSA2015 and M7 additions. */
{ "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M), HWS_VM, HWS2_VM },
/* v9 with OSA2017 and M8 additions. */
{ "m8", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8),
HWS_VM8, HWS2_VM8 },
{ NULL, 0, 0, 0 }
};
@ -1011,6 +1030,7 @@ wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait */
{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9 }, /* rd %tick,r */
{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9 }, /* rd %pc,r */
{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9 }, /* rd %fprs,r */
{ "rd", F3(2, 0x28, 0)|RS1(13), F3(~2, ~0x28, ~0)|RS1(~13)|SIMM13(~0), "&,d", 0, 0, HWCAP2_SPARC6, m8 }, /* rd %entropy,r */
{ "rd", F3(2, 0x28, 0)|RS1(14), F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0), "{,d", 0, 0, HWCAP2_SPARC5, v9m }, /* rd %mcdper,r */
/* Read from ASR registers 16..31, which is the range defined in SPARC
@ -2180,6 +2200,7 @@ SLCBCC("cbnefr", 15),
{ "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9e },
{ "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, 0, v9e },
{ "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, 0, v9e },
{ "sha3", F3F(2, 0x36, 0x144), F3F(~2, ~0x36, ~0x144), "", F_FLOAT, 0, HWCAP2_SHA3, m8 },
{ "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, 0, v9e },
{ "xmpmul", F3F(2, 0x36, 0x148)|RD(1), F3F(~2, ~0x36, ~0x148)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMPMUL, v9m },
{ "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, 0, v9e },
@ -2244,6 +2265,168 @@ SLCBCC("cbnefr", 15),
{ "fpsubus8", F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
{ "fpsubus16", F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m },
/* Other OSA2017 and M8 instructions. */
{ "dictunpack", F3F(2, 0x36, 0x1c), F3F(~2, ~0x36, ~0x1c), "v,X,H", 0, 0, HWCAP2_DICTUNP, m8 },
#define fpcmpshl(cbits, opf) \
{ "fpcmp" cbits "shl", F3F(2, 0x36, (opf)), F3F(~2, ~0x36, ~(opf)), "v,',|,d", 0, 0, HWCAP2_FPCMPSHL, m8 }
fpcmpshl ("ule8", 0x190),
fpcmpshl ("ugt8", 0x191),
fpcmpshl ("eq8", 0x192),
fpcmpshl ("ne8", 0x193),
fpcmpshl ("ule16", 0x194),
fpcmpshl ("ugt16", 0x195),
fpcmpshl ("eq16", 0x196),
fpcmpshl ("ne16", 0x197),
fpcmpshl ("ule32", 0x198),
fpcmpshl ("ugt32", 0x199),
fpcmpshl ("eq32", 0x19a),
fpcmpshl ("ne32", 0x19b),
fpcmpshl ("de8", 0x45),
fpcmpshl ("de16", 0x47),
fpcmpshl ("de32", 0x4a),
fpcmpshl ("ur8", 0x19c),
fpcmpshl ("ur16", 0x19d),
fpcmpshl ("ur32", 0x19e),
#undef fpcmpshl
#define fps64x(dir, opf) \
{ "fps" dir "64x", F3F(2, 0x36, (opf)), F3F(~2, ~0x36, ~(opf)), "v,B,H", 0, 0, HWCAP2_SPARC6, m8 }
fps64x ("ll", 0x106),
fps64x ("ra", 0x10f),
fps64x ("rl", 0x107),
#undef fps64x
#define ldm(width,opm,flags) \
{ "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0), "[1+2],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
{ "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "[1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+%g0],d */ \
{ "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[1+j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
{ "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[j+1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+j],d */ \
{ "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|RS1_G0, "[j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \
{ "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|SIMM10(~0), "[1],d", (flags), 0, HWCAP2_SPARC6, m8 } /* ldm [rs1+0],d */
ldm ("sh", 0x0, 0),
ldm ("uh", 0x1, 0),
ldm ("sw", 0x2, 0),
ldm ("uw", 0x3, 0),
/* Note that opm=0x4 is reserved. */
ldm ("x", 0x5, 0),
ldm ("ux", 0x5, F_ALIAS),
#undef ldm
#define ldma(width,opm,flags) \
{ "ldm" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1), "[1+2]o,d", (flags), 0, HWCAP2_SPARC6, m8 }, \
{ "ldm" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "[1]o,d", (flags), 0, HWCAP2_SPARC6, m8 }
ldma ("sh", 0x0, 0),
ldma ("uh", 0x1, 0),
ldma ("sw", 0x2, 0),
ldma ("uw", 0x3, 0),
/* Note that opm=0x4 is reserved. */
ldma ("x", 0x5, 0),
ldma ("ux", 0x5, F_ALIAS),
#undef ldma
#define ldmf(width,opm,rd) \
{ "ldmf" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0), "[1+2]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
{ "ldmf" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "[1]," rd, 0, 0, HWCAP2_SPARC6, m8 }, /* ldmf [rs1+%g0],rd */ \
{ "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[1+j]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
{ "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[j+1]," rd, 0, 0, HWCAP2_SPARC6, m8 }, /* ldmf [rs1+j],rd */ \
{ "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|RS1_G0, "[j]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
{ "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|SIMM10(~0), "[1]," rd, 0, 0, HWCAP2_SPARC6, m8 } /* ldmf [rs1+0],rd */
ldmf ("s", 0x6, "g"),
ldmf ("d", 0x7, "H"),
#undef ldmf
#define ldmfa(width,opm,rd) \
{ "ldmf" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1), "[1+2]o," rd, 0, 0, HWCAP2_SPARC6, m8 }, \
{ "ldmf" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "[1]o," rd, 0, 0, HWCAP2_SPARC6, m8}
ldmfa ("s", 0x6, "g"),
ldmfa ("d", 0x7, "H"),
#undef ldmfa
#define stm(width,opm) \
{ "stm" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0), "d,[1+2]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stm" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "d,[1]", 0, 0, HWCAP2_SPARC6, m8 }, /* stm d,[rs1+%g0] */ \
{ "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), "d,[1+j]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), "d,[j+1]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|RS1_G0, "d,[j]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|SIMM10(~0), "d,[1]", 0, 0, HWCAP2_SPARC6, m8 }
stm ("h", 0x1),
stm ("w", 0x3),
stm ("x", 0x5),
#undef stm
#define stma(width,opm) \
{ "stm" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1), "d,[1+2]o", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stm" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "d,[1]o", 0, 0, HWCAP2_SPARC6, m8 }
stma ("h", 0x1),
stma ("w", 0x3),
stma ("x", 0x5),
#undef stma
#define stmf(width, opm, rd) \
{ "stmf" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0), rd ",[1+2]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stmf" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, rd ",[1]", 0, 0, HWCAP2_SPARC6, m8 }, /* stmf rd,[rs1+%g0] */ \
{ "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), rd ",[1+j]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), rd ",[j+1]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|RS1_G0, rd ",[j]", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|SIMM10(~0), rd ",[1]", 0, 0, HWCAP2_SPARC6, m8 }
stmf ("s", 0x6, "g"),
stmf ("d", 0x7, "H"),
#define stmfa(width, opm, rd) \
{ "stmf" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1), rd ",[1+2]o", 0, 0, HWCAP2_SPARC6, m8 }, \
{ "stmf" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, rd ",[1]o", 0, 0, HWCAP2_SPARC6, m8 }
stmfa ("s", 0x6, "g"),
stmfa ("d", 0x7, "H"),
#undef stmfa
#define on(op,fcn,hwcaps2) \
{ "on" op, F3F(2, 0x36, 0x15)|ONFCN((fcn)), F3F(~2, ~0x36, ~0x15)|ONFCN(~(fcn)), ";,:,^", 0, 0, (hwcaps2), m8 }
on ("add", 0x0, HWCAP2_ONADDSUB),
on ("sub", 0x1, HWCAP2_ONADDSUB),
on ("mul", 0x2, HWCAP2_ONMUL),
on ("div", 0x3, HWCAP2_ONDIV),
#undef on
#define rev(what,width,fcn) \
{ "rev" what width, F3F(2, 0x36, 0x1e)|REVFCN((fcn)), F3F(~2, ~0x36, ~0x1e)|REVFCN(~(fcn)), "1,d", 0, 0, HWCAP2_SPARC6, m8 }
rev ("bits", "b", 0x0),
rev ("bytes", "h", 0x1),
rev ("bytes", "w", 0x2),
rev ("bytes", "x", 0x3),
#undef rev
{ "rle_burst", F3F(2, 0x36, 0x30), F3F(~2, ~0x36, ~0x30), "1,2,d", 0, 0, HWCAP2_RLE, m8 },
{ "rle_length", F3F(2, 0x36, 0x32)|RS1(0), F3F(~2, ~0x36, ~0x32)|RS1(~0), "2,d", 0, 0, HWCAP2_RLE, m8 },
/* More v9 specific insns, these need to come last so they do not clash
with v9a instructions such as "edge8" which looks like impdep1. */
@ -2311,6 +2494,8 @@ static sparc_asi asi_table[] =
{ 0x21, "#ASI_MMU", v9c },
{ 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS", v9c },
{ 0x24, "#ASI_NUCLEUS_QUAD_LDD", v9b },
{ 0x24, "#ASI_CORE_COMMIT_COUNT", m8 },
{ 0x24, "#ASI_CORE_SELECT_COUNT", m8 },
{ 0x25, "#ASI_QUEUE", v9c },
{ 0x26, "#ASI_QUAD_LDD_PHYS_4V", v9c },
{ 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L", v9b },
@ -2344,17 +2529,22 @@ static sparc_asi asi_table[] =
{ 0x4c, "#ASI_AFSR", v9b },
{ 0x4d, "#ASI_AFAR", v9b },
{ 0x4e, "#ASI_EC_TAG_DATA", v9b },
{ 0x48, "#ASI_ARF_ECC_REG", m8 },
{ 0x50, "#ASI_IMMU", v9b },
{ 0x51, "#ASI_IMMU_TSB_8KB_PTR", v9b },
{ 0x52, "#ASI_IMMU_TSB_64KB_PTR", v9b },
{ 0x53, "#ASI_ITLB_PROBE", m8 },
{ 0x54, "#ASI_ITLB_DATA_IN", v9b },
{ 0x55, "#ASI_ITLB_DATA_ACCESS", v9b },
{ 0x56, "#ASI_ITLB_TAG_READ", v9b },
{ 0x57, "#ASI_IMMU_DEMAP", v9b },
{ 0x58, "#ASI_DMMU", v9b },
{ 0x58, "#ASI_DSFAR", m8 },
{ 0x59, "#ASI_DMMU_TSB_8KB_PTR", v9b },
{ 0x5a, "#ASI_DMMU_TSB_64KB_PTR", v9b },
{ 0x5a, "#ASI_DTLB_PROBE_PRIMARY", m8 },
{ 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR", v9b },
{ 0x5b, "#ASI_DTLB_PROBE_REAL", m8 },
{ 0x5c, "#ASI_DTLB_DATA_IN", v9b },
{ 0x5d, "#ASI_DTLB_DATA_ACCESS", v9b },
{ 0x5e, "#ASI_DTLB_TAG_READ", v9b },
@ -2363,6 +2553,7 @@ static sparc_asi asi_table[] =
{ 0x63, "#ASI_INTR_ID", v9b },
{ 0x63, "#ASI_CORE_ID", v9b },
{ 0x63, "#ASI_CESR_ID", v9b },
{ 0x64, "#ASI_CORE_SELECT_COMMIT_NHT", m8 },
{ 0x66, "#ASI_IC_INSTR", v9b },
{ 0x67, "#ASI_IC_TAG", v9b },
{ 0x68, "#ASI_IC_STAG", v9b },