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binutils: support for the SPARC M8 processor

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This patch adds support for the new SPARC M8 processor (implementing OSA
2017) to binutils.

New instructions:

- Dictionary Unpack

  + dictunpack

- Partitioned Compare with shifted result

  + Signed variants:   fpcmp{le,gt,eq,ne}{8,16,32}shl
  + Unsigned variants: fpcmpu{le,gt}{8,16,32}shl

- Partitioned Dual-Equal compared, with shifted result

  + fpcmpde{8,16,32}shl

- Partitioned Unsigned Range Compare, with shifted result

  + fpcmpur{8,16,32}shl

- 64-bit shifts on Floating-Point registers

  + fps{ll,ra,rl}64x

- Misaligned loads and stores

  + ldm{sh,uh,sw,uw,x,ux}
  + ldm{sh,uh,sw,uw,x,ux}a
  + ldmf{s,d}
  + ldmf{s,d}a

  + stm{h,w,x}
  + stm{h,w,x}a
  + stmf{s,d}
  + stmf{s,d}a

- Oracle Numbers

  + on{add,sub,mul,div}

- Reverse Bytes/Bits

  + revbitsb
  + revbytes{h,w,x}

- Run-Length instructions

  + rle_burst
  + rle_length

- New crypto instructions

  + sha3

- Instruction to read the new register %entropy

  + rd %entropy

New Alternate Address Identifiers:

- 0x24, #ASI_CORE_COMMIT_COUNT
- 0x24, #ASI_CORE_SELECT_COUNT
- 0x48, #ASI_ARF_ECC_REG
- 0x53, #ASI_ITLB_PROBE
- 0x58, #ASI_DSFAR
- 0x5a, #ASI_DTLB_PROBE_PRIMARY
- 0x5b, #ASI_DTLB_PROBE_REAL
- 0x64, #ASI_CORE_SELECT_COMMIT_NHT

The new assembler command-line options for selecting the M8 architecture
are:

-Av9m8 or -Asparc6 for 64-bit binaries.
-Av8plusm8 for 32-bit (v8+) binaries.

The corresponding disassembler command-line options are:

-msparc:v9m8 for 64-bit binaries.
-msparc:v8plusm8 for 32-bit (v8+) binaries.

Tested for regressions in the following targets:
sparc-aout sparc-linux sparc-vxworks sparc64-linux

bfd/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* archures.c (bfd_mach_sparc_v9m8): Define.
	(bfd_mach_sparc_v8plusm8): Likewise.
	(bfd_mach_sparc_v9_p): Adjust to M8.
	(bfd_mach_sparc_64bit_p): Likewise.
	* aoutx.h (machine_type): Handle bfd_mach_sparc_v9m8 and
	bfd_mach_sparc_v8plusm8.
	* bfd-in2.h: Regenerated.
	* cpu-sparc.c (arch_info_struct): Entries for sparc:v9m8 and
	sparc:v8plusm8.
	* elfxx-sparc.c (_bfd_sparc_elf_object_p): Handle
	bfd_mach_sparc_v8plusm8 and bfd_mach_sparc_v9m8 using the new hw
	capabilities ONADDSUB, ONMUL, ONDIV, DICTUNP, FPCPSHL, RLE and
	SHA3.
	* elf32-sparc.c (elf32_sparc_final_write_processing): Handle
	bfd_mach_sparc_v8plusm8.

binutils/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* NEWS: Mention the SPARC M8 support.

gas/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* config/tc-sparc.c (sparc_arch_table): Entries for `sparc6',
	`v9m8' and `v8plusm8'.
	(sparc_md_end): Handle SPARC_OPCODE_ARCH_M8.
	(get_hwcap_name): Support the M8 hardware capabilities.
	(sparc_ip): Handle new operand types.
	* doc/c-sparc.texi (Sparc-Opts): Document -Av9m8, -Av8plusm8 and
	-Asparc6, and the corresponding -xarch aliases.
	* testsuite/gas/sparc/sparc6.s: New file.
	* testsuite/gas/sparc/sparc6.d: Likewise.
	* testsuite/gas/sparc/sparc6-diag.s: Likewise.
	* testsuite/gas/sparc/sparc6-diag.l: Likewise.
	* testsuite/gas/sparc/fpcmpshl.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl.d: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.s: Likewise.
	* testsuite/gas/sparc/fpcmpshl-diag.l: Likewise.
	* testsuite/gas/sparc/ldm-stm.s: Likewise.
	* testsuite/gas/sparc/ldm-stm.d: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.s: Likewise.
	* testsuite/gas/sparc/ldm-stm-diag.l: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf.d: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.s: Likewise.
	* testsuite/gas/sparc/ldmf-stmf-diag.l: Likewise.
	* testsuite/gas/sparc/on.s: Likewise.
	* testsuite/gas/sparc/on.d: Likewise.
	* testsuite/gas/sparc/on-diag.s: Likewise.
	* testsuite/gas/sparc/on-diag.l: Likewise.
	* testsuite/gas/sparc/rle.s: Likewise.
	* testsuite/gas/sparc/rle.d: Likewise.
	* testsuite/gas/sparc/sparc.exp (gas_64_check): Run new tests.
	* testsuite/gas/sparc/rdasr.s: Add test for RDENTROPY.
	* testsuite/gas/sparc/rdasr.d: Likewise.

include/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* elf/sparc.h (ELF_SPARC_HWCAP2_SPARC6): Define.
	(ELF_SPARC_HWCAP2_ONADDSUB): Likewise.
	(ELF_SPARC_HWCAP2_ONMUL): Likewise.
	(ELF_SPARC_HWCAP2_ONDIV): Likewise.
	(ELF_SPARC_HWCAP2_DICTUNP): Likewise.
	(ELF_SPARC_HWCAP2_FPCMPSHL): Likewise.
	(ELF_SPARC_HWCAP2_RLE): Likewise.
	(ELF_SPARC_HWCAP2_SHA3): Likewise.
	* opcode/sparc.h (sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_M8
	and adjust SPARC_OPCODE_ARCH_MAX.
	(HWCAP2_SPARC6): Define.
	(HWCAP2_ONADDSUB): Likewise.
	(HWCAP2_ONMUL): Likewise.
	(HWCAP2_ONDIV): Likewise.
	(HWCAP2_DICTUNP): Likewise.
	(HWCAP2_FPCMPSHL): Likewise.
	(HWCAP2_RLE): Likewise.
	(HWCAP2_SHA3): Likewise.
	(OPM): Likewise.
	(OPMI): Likewise.
	(ONFCN): Likewise.
	(REVFCN): Likewise.
	(SIMM10): Likewise.

opcodes/ChangeLog:

2017-05-19  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
	(X_IMM2): Define.
	(compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
	bfd_mach_sparc_v9m8.
	(print_insn_sparc): Handle new operand types.
	* sparc-opc.c (MASK_M8): Define.
	(v6): Add MASK_M8.
	(v6notlet): Likewise.
	(v7): Likewise.
	(v8): Likewise.
	(v9): Likewise.
	(v9a): Likewise.
	(v9b): Likewise.
	(v9c): Likewise.
	(v9d): Likewise.
	(v9e): Likewise.
	(v9v): Likewise.
	(v9m): Likewise.
	(v9andleon): Likewise.
	(m8): Define.
	(HWS_VM8): Define.
	(HWS2_VM8): Likewise.
	(sparc_opcode_archs): Add entry for "m8".
	(sparc_opcodes): Add OSA2017 and M8 instructions
	dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
	fpx{ll,ra,rl}64x,
	ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
	ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
	revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
	stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
	(asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
	ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
	ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
	ASI_CORE_SELECT_COMMIT_NHT.
This commit is contained in:
Jose E. Marchesi 2017-05-19 09:27:08 -07:00
parent 92f7d783c1
commit 6451799480
43 changed files with 931 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

25
include/opcode/sparc.h
View file

@ -58,7 +58,8 @@ enum sparc_opcode_arch_val
SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer
multiply and Fujitsu fp multiply-add. */
SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */
SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_V9M,
SPARC_OPCODE_ARCH_M8, /* V9 with OSA2017 and M8 additions. */
SPARC_OPCODE_ARCH_MAX = SPARC_OPCODE_ARCH_M8,
SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
};
@ -184,6 +185,15 @@ typedef struct
#define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
#define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
#define HWCAP2_SPARC6 0x00020000 /* OSA2017 new instructions */
#define HWCAP2_ONADDSUB 0x00040000 /* Oracle Number add/subtract */
#define HWCAP2_ONMUL 0x00080000 /* Oracle Number multiply */
#define HWCAP2_ONDIV 0x00100000 /* Oracle Number divide */
#define HWCAP2_DICTUNP 0x00200000 /* Dictionary unpack instruction */
#define HWCAP2_FPCMPSHL 0x00400000 /* Partition compare with shifted result */
#define HWCAP2_RLE 0x00800000 /* Run-length encoded burst and length */
#define HWCAP2_SHA3 0x01000000 /* SHA3 instruction */
/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
macro), which is 64 bits. It is handled as a special case.
@ -202,15 +212,19 @@ typedef struct
e frs1 floating point register.
v frs1 floating point register (double/even).
V frs1 floating point register (quad/multiple of 4).
; frs1 floating piont register (multiple of 8).
f frs2 floating point register.
B frs2 floating point register (double/even).
R frs2 floating point register (quad/multiple of 4).
: frs2 floating point register (multiple of 8).
' rs2m floating point register (double/even) in FPCMPSHL. (m8)
4 frs3 floating point register.
5 frs3 floating point register (doube/even).
g frsd floating point register.
H frsd floating point register (double/even).
J frsd floating point register (quad/multiple of 4).
} frsd floating point register (double/even) that is == frs2
^ frsd floating piont register in ON instructions.
b crs1 coprocessor register
c crs2 coprocessor register
D crsd coprocessor register
@ -253,6 +267,7 @@ typedef struct
P %pc. (v9)
W %tick. (v9)
{ %mcdper. (v9b)
& %entropy. (m8)
o %asi. (v9)
6 %fcc0. (v9)
7 %fcc1. (v9)
@ -269,7 +284,8 @@ typedef struct
/ Ancillary state register in rs1 (v9a)
( entire floating point state register (%efsr)
) 5 bit immediate placed in RS3 field
= 2+8 bit PC relative immediate. (v9) */
= 2+8 bit PC relative immediate. (v9)
| FPCMPSHL 2 bit immediate. (m8) */
#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
@ -277,6 +293,10 @@ typedef struct
#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
#define OPF_LOW4(x) OPF ((x) & 0xf) /* V9. */
#define OPM(x) (((x) & 0x7) << 10) /* opm field of misaligned load/store insns. */
#define OPMI(x) (((x) & 0x1) << 9) /* opm i field of misaligned load/store insns. */
#define ONFCN(x) (((x) & 0x3) << 26) /* fcn field of Oracle Number insns. */
#define REVFCN(x) (((x) & 0x3) << 0) /* fcn field of REV* insns. */
#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
#define F3F4(x, y, z) (OP (x) | OP3 (y) | OPF_LOW4 (z))
#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
@ -287,6 +307,7 @@ typedef struct
#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
#define SIMM10(x) ((x) & 0x3ff) /* Simm10 field. */
#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
#define RS3(x) (((x) & 0x1f) << 9) /* Rs3 field. */