FreeChainXenon/binutils-gdb
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Fix cmov insn.

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This commit is contained in:
Andrew Cagney 1997-09-19 00:50:19 +00:00
parent 46ad7d6ccb
commit 60fe0e06a8
4 changed files with 30 additions and 17 deletions
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9
sim/v850/ChangeLog
View file

@ -1,3 +1,12 @@
Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (condition_met): Make global.
* sim-main.h (TRACE_ALU_INPUT3): Define.
start-sanitize-v850e
* simops.c (OP_32007E0): Move "cmov" to v850.igen, fix.
end-sanitize-v850e
Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com> Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c: Move "mov", "reti", to v850.igen, fix tracing. * simops.c: Move "mov", "reti", to v850.igen, fix tracing.

17
sim/v850/sim-main.h
View file

@ -224,6 +224,10 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
PC, sim_core_write_map, (ADDR), (DATA)) PC, sim_core_write_map, (ADDR), (DATA))
/* compare cccc field against PSW */
unsigned int condition_met (unsigned code);
/* Debug/tracing calls */ /* Debug/tracing calls */
enum op_types enum op_types
@ -310,6 +314,19 @@ do { \
} \ } \
} while (0) } while (0)
#define TRACE_ALU_INPUT3(IN0, IN1, IN2) \
do { \
if (TRACE_ALU_P (CPU)) { \
trace_module = "alu"; \
trace_pc = cia; \
trace_name = itable[MY_INDEX].name; \
trace_values[0] = (IN0); \
trace_values[1] = (IN1); \
trace_values[2] = (IN2); \
trace_num_values = 3; \
} \
} while (0)
#define TRACE_ALU_RESULT(RESULT) \ #define TRACE_ALU_RESULT(RESULT) \
do { \ do { \
if (TRACE_ALU_P (CPU)) { \ if (TRACE_ALU_P (CPU)) { \

17
sim/v850/simops.c
View file

@ -305,7 +305,7 @@ trace_output (result)
/* Returns 1 if the specific condition is met, returns 0 otherwise. */ /* Returns 1 if the specific condition is met, returns 0 otherwise. */
static unsigned int unsigned int
condition_met (unsigned code) condition_met (unsigned code)
{ {
unsigned int psw = PSW; unsigned int psw = PSW;
@ -2896,21 +2896,6 @@ OP_70 (void)
return 2; return 2;
} }
/* end-sanitize-v850e */
/* start-sanitize-v850e */
/* cmov reg1, reg2, reg3 */
int
OP_32007E0 (void)
{
trace_input ("cmov", OP_REG_REG_REG, 0);
State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? State.regs[ OP[0] ] : State.regs[ OP[1] ];
trace_output (OP_REG_REG_REG);
return 4;
}
/* end-sanitize-v850e */ /* end-sanitize-v850e */
/* start-sanitize-v850e */ /* start-sanitize-v850e */
/* mul reg1, reg2, reg3 */ /* mul reg1, reg2, reg3 */

4
sim/v850/v850.igen
View file

@ -353,7 +353,9 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
// end-sanitize-v850eq // end-sanitize-v850eq
"cmov <cccc>, r<reg1>, r<reg2>, r<reg3>" "cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
{ {
COMPAT_2 (OP_32007E0 ()); TRACE_ALU_INPUT3 (cccc, GR[reg1], GR[reg2]);
GR[reg3] = condition_met (cccc) ? GR[reg1] : GR[reg2];
TRACE_ALU_RESULT (GR[reg3]);
} }
// end-sanitize-v850e // end-sanitize-v850e