MIPS: Make the CODE10 operand code consistent between ISAs
This change moves the microMIPS 10-bit uninterpreted immediate code embedded at bits 25..16 in the SYSCALL, WAIT, SDBBP and HYPCALL instructions from `B' over to `+J' which is the operand code used in the standard MIPS instruction set for a similar code embedded at bits 20..11, currently used by HYPCALL only in that set. opcodes/ * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'. (micromips_opcodes): Use "+J" in place of "B" for "hypcall", "sdbbp", "syscall" and "wait". include/opcode/ * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B' over to `+J'.
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4 changed files with 20 additions and 8 deletions
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@ -2056,7 +2056,6 @@ extern const int bfd_mips16_num_opcodes;
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"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
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"z" must be zero register
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"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
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"B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
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"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
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"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
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@ -2081,6 +2080,8 @@ extern const int bfd_mips16_num_opcodes;
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"+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
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Requires that "+A" or "+E" occur first to set position.
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Enforces: 32 < (pos+size) <= 64.
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"+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code
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(MICROMIPSOP_*_CODE10)
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PC-relative addition (ADDIUPC) instruction:
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"mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
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@ -2160,14 +2161,14 @@ extern const int bfd_mips16_num_opcodes;
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Characters used so far, for quick reference when adding more:
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"12345678 0"
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"<>(),+.@\^|~"
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"ABCDEFGHI KLMN RST V "
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"A CDEFGHI KLMN RST V "
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"abcd f hijklmnopqrstuvw yz"
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Extension character sequences used so far ("+" followed by the
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following), for quick reference when adding more:
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""
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"~!@#$%^&*|"
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"ABCEFGHTUVW"
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"ABCEFGHJTUVW"
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"dehijklnouvwx"
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Extension character sequences used so far ("m" followed by the
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