Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
This commit is contained in:
Jan Beulich
parent
567dfba2be
commit
5437a02abc
5 changed files with 41 additions and 31 deletions
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@ -1,3 +1,8 @@
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}.
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* testsuite/gas/aarch64/f64mm.d: Adjust expectations.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for
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@ -10,20 +10,20 @@ Disassembly of section \.text:
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*[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d
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*[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\]
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*[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\]
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*[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27\]
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*[0-9a-f]+: a4a003e0 ld1roh {z0\.h}, p0/z, \[sp, x0\]
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*[0-9a-f]+: a53b17f1 ld1row {z17\.s}, p5/z, \[sp, x27\]
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*[0-9a-f]+: a52003e0 ld1row {z0\.s}, p0/z, \[sp, x0\]
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*[0-9a-f]+: a5bb17f1 ld1rod {z17\.d}, p5/z, \[sp, x27\]
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*[0-9a-f]+: a5a003e0 ld1rod {z0\.d}, p0/z, \[sp, x0\]
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*[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27, lsl #1\]
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*[0-9a-f]+: a4a003e0 ld1roh {z0\.h}, p0/z, \[sp, x0, lsl #1\]
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*[0-9a-f]+: a53b17f1 ld1row {z17\.s}, p5/z, \[sp, x27, lsl #2\]
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*[0-9a-f]+: a52003e0 ld1row {z0\.s}, p0/z, \[sp, x0, lsl #2\]
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*[0-9a-f]+: a5bb17f1 ld1rod {z17\.d}, p5/z, \[sp, x27, lsl #3\]
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*[0-9a-f]+: a5a003e0 ld1rod {z0\.d}, p0/z, \[sp, x0, lsl #3\]
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*[0-9a-f]+: a43b1411 ld1rob {z17\.b}, p5/z, \[x0, x27\]
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*[0-9a-f]+: a4200000 ld1rob {z0\.b}, p0/z, \[x0, x0\]
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*[0-9a-f]+: a4bb1411 ld1roh {z17\.h}, p5/z, \[x0, x27\]
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*[0-9a-f]+: a4a00000 ld1roh {z0\.h}, p0/z, \[x0, x0\]
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*[0-9a-f]+: a53b1411 ld1row {z17\.s}, p5/z, \[x0, x27\]
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*[0-9a-f]+: a5200000 ld1row {z0\.s}, p0/z, \[x0, x0\]
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*[0-9a-f]+: a5bb1411 ld1rod {z17\.d}, p5/z, \[x0, x27\]
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*[0-9a-f]+: a5a00000 ld1rod {z0\.d}, p0/z, \[x0, x0\]
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*[0-9a-f]+: a4bb1411 ld1roh {z17\.h}, p5/z, \[x0, x27, lsl #1\]
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*[0-9a-f]+: a4a00000 ld1roh {z0\.h}, p0/z, \[x0, x0, lsl #1\]
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*[0-9a-f]+: a53b1411 ld1row {z17\.s}, p5/z, \[x0, x27, lsl #2\]
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*[0-9a-f]+: a5200000 ld1row {z0\.s}, p0/z, \[x0, x0, lsl #2\]
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*[0-9a-f]+: a5bb1411 ld1rod {z17\.d}, p5/z, \[x0, x27, lsl #3\]
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*[0-9a-f]+: a5a00000 ld1rod {z0\.d}, p0/z, \[x0, x0, lsl #3\]
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*[0-9a-f]+: a42037f1 ld1rob {z17\.b}, p5/z, \[sp\]
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*[0-9a-f]+: a42723e0 ld1rob {z0\.b}, p0/z, \[sp, #224\]
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*[0-9a-f]+: a42823e0 ld1rob {z0\.b}, p0/z, \[sp, #-256\]
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@ -13,21 +13,21 @@ fmmla z0.d, z0.d, z0.d
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ld1rob { z17.b }, p5/z, [sp, x27]
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ld1rob { z0.b }, p0/z, [sp, x0]
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ld1roh { z17.h }, p5/z, [sp, x27]
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ld1roh { z0.h }, p0/z, [sp, x0]
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ld1row { z17.s }, p5/z, [sp, x27]
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ld1row { z0.s }, p0/z, [sp, x0]
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ld1rod { z17.d }, p5/z, [sp, x27]
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ld1rod { z0.d }, p0/z, [sp, x0]
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ld1roh { z17.h }, p5/z, [sp, x27, lsl #1]
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ld1roh { z0.h }, p0/z, [sp, x0, lsl #1]
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ld1row { z17.s }, p5/z, [sp, x27, lsl #2]
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ld1row { z0.s }, p0/z, [sp, x0, lsl #2]
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ld1rod { z17.d }, p5/z, [sp, x27, lsl #3]
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ld1rod { z0.d }, p0/z, [sp, x0, lsl #3]
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ld1rob { z17.b }, p5/z, [x0, x27]
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ld1rob { z0.b }, p0/z, [x0, x0]
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ld1roh { z17.h }, p5/z, [x0, x27]
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ld1roh { z0.h }, p0/z, [x0, x0]
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ld1row { z17.s }, p5/z, [x0, x27]
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ld1row { z0.s }, p0/z, [x0, x0]
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ld1rod { z17.d }, p5/z, [x0, x27]
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ld1rod { z0.d }, p0/z, [x0, x0]
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ld1roh { z17.h }, p5/z, [x0, x27, lsl #1]
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ld1roh { z0.h }, p0/z, [x0, x0, lsl #1]
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ld1row { z17.s }, p5/z, [x0, x27, lsl #2]
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ld1row { z0.s }, p0/z, [x0, x0, lsl #2]
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ld1rod { z17.d }, p5/z, [x0, x27, lsl #3]
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ld1rod { z0.d }, p0/z, [x0, x0, lsl #3]
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ld1rob { z17.b }, p5/z, [sp, #0]
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ld1rob { z0.b }, p0/z, [sp, #224]
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@ -1,17 +1,22 @@
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
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* aarch64-tbl.h (aarch64_opcode_table): Use
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SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
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forms of SUDOT and USDOT.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
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* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
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uzip{1,2}.
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* opcodes/aarch64-dis-2.c: Re-generate.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
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* opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
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* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
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FMMLA encoding.
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* opcodes/aarch64-dis-2.c: Re-generate.
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@ -5074,10 +5074,10 @@ struct aarch64_opcode aarch64_opcode_table[] =
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INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
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F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
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F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
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F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1rod", 0xa5a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1rod", 0xa5a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1rob", 0xa4202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_BZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1roh", 0xa4a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_HZU, F_OD(1), 0),
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F64MATMUL_SVE_INSN ("ld1row", 0xa5202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_SZU, F_OD(1), 0),
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