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Add SH2E support

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This commit is contained in:
Nick Clifton 2003-01-23 18:50:57 +00:00
parent 3434109f52
commit 5177500f26
13 changed files with 308 additions and 219 deletions
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11
bfd/ChangeLog
View file

@ -1,3 +1,14 @@
2003-01-23 Nick Clifton <nickc@redhat.com>
* Add sh2e support:
2002-04-02 Elena Zannoni <ezannoni@redhat.com>
* archures.c (bfd_mach_sh2e): Added.
* bfd-in2.h: Rebuilt.
* cpu-sh.c (arch_info_struct): Added SH2e.
* elf32-sh.c (sh_elf_set_mach_from_flags): Handle EF_SH2E.
2003-01-23 Alan Modra <amodra@bigpond.net.au>
* elf-bfd.h (struct bfd_elf_section_data): Remove tdata. Change

1
bfd/archures.c
View file

@ -213,6 +213,7 @@ DESCRIPTION
.#define bfd_mach_sh 1
.#define bfd_mach_sh2 0x20
.#define bfd_mach_sh_dsp 0x2d
.#define bfd_mach_sh2e 0x2e
.#define bfd_mach_sh3 0x30
.#define bfd_mach_sh3_dsp 0x3d
.#define bfd_mach_sh3e 0x3e

1
bfd/bfd-in2.h
View file

@ -1640,6 +1640,7 @@ enum bfd_architecture
#define bfd_mach_sh 1
#define bfd_mach_sh2 0x20
#define bfd_mach_sh_dsp 0x2d
#define bfd_mach_sh2e 0x2e
#define bfd_mach_sh3 0x30
#define bfd_mach_sh3_dsp 0x3d
#define bfd_mach_sh3e 0x3e

31
bfd/cpu-sh.c
View file

@ -1,5 +1,5 @@
/* BFD library support routines for the Hitachi-SH architecture.
Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002
Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
Hacked by Steve Chamberlain of Cygnus Support.
@ -25,7 +25,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#if 0
/* This routine is provided two arch_infos and returns whether
they'd be compatible */
they'd be compatible. */
static const bfd_arch_info_type *
compatible (a,b)
@ -40,13 +40,12 @@ compatible (a,b)
#define SH_NEXT &arch_info_struct[0]
#define SH2_NEXT &arch_info_struct[1]
#define SH_DSP_NEXT &arch_info_struct[2]
#define SH3_NEXT &arch_info_struct[3]
#define SH3_DSP_NEXT &arch_info_struct[4]
#define SH3E_NEXT &arch_info_struct[5]
#define SH4_NEXT NULL
#undef SH4_NEXT
#define SH4_NEXT &arch_info_struct[6]
#define SH2E_NEXT &arch_info_struct[2]
#define SH_DSP_NEXT &arch_info_struct[3]
#define SH3_NEXT &arch_info_struct[4]
#define SH3_DSP_NEXT &arch_info_struct[5]
#define SH3E_NEXT &arch_info_struct[6]
#define SH4_NEXT &arch_info_struct[7]
#define SH64_NEXT NULL
static const bfd_arch_info_type arch_info_struct[] =
@ -65,6 +64,20 @@ static const bfd_arch_info_type arch_info_struct[] =
bfd_default_scan,
SH2_NEXT
},
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_sh,
bfd_mach_sh2e,
"sh", /* arch_name */
"sh2e", /* printable name */
1,
FALSE, /* not the default */
bfd_default_compatible,
bfd_default_scan,
SH2E_NEXT
},
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */

3
bfd/elf32-sh.c
View file

@ -6724,6 +6724,9 @@ sh_elf_set_mach_from_flags (abfd)
case EF_SH2:
bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh2);
break;
case EF_SH2E:
bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh2e);
break;
case EF_SH_DSP:
bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh_dsp);
break;

12
gas/ChangeLog
View file

@ -1,3 +1,15 @@
2003-01-23 Nick Clifton <nickc@redhat.com>
NEWS: Announce sh2e support.
* Add sh2e support:
2002-04-02 Alexandre Oliva <aoliva@redhat.com>
* config/tc-sh.c (md_show_usage): Added sh2e next to
sh3e.
(sh_elf_final_processing): Handle arch_sh2e.
2003-01-23 Alan Modra <amodra@bigpond.net.au>
* symbols.c (S_FORCE_RELOC): Add "strict" param.

2
gas/NEWS
View file

@ -1,5 +1,7 @@
-*- text -*-
* Support for SH2E added.
* GASP has now been removed.
* Support for Texas Instruments TMS320C4x and TMS320C3x series of

4
gas/config/tc-sh.c
View file

@ -2718,7 +2718,7 @@ SH options:\n\
-big generate big endian code\n\
-relax alter jump instructions for long displacements\n\
-small align sections to 4 byte boundaries, not 16\n\
-dsp enable sh-dsp insns, and disable sh3e / sh4 insns.\n"));
-dsp enable sh-dsp insns, and disable sh2e/sh3e/sh4 insns.\n"));
#ifdef HAVE_SH64
fprintf (stream, _("\
-isa=[shmedia set default instruction set for SH64\n\
@ -3298,6 +3298,8 @@ sh_elf_final_processing ()
val = EF_SH1;
else if (valid_arch & arch_sh2)
val = EF_SH2;
else if (valid_arch & arch_sh2e)
val = EF_SH2E;
else if (valid_arch & arch_sh_dsp)
val = EF_SH_DSP;
else if (valid_arch & arch_sh3)

12
include/elf/ChangeLog
View file

@ -1,3 +1,15 @@
2003-01-23 Nick Clifton <nickc@redhat.com>
* Add sh2e support:
2002-04-02 Alexandre Oliva <aoliva@redhat.com>
* sh.h (EF_SH_MERGE_MACH): Handle SH2E.
2002-04-02 Elena Zannoni <ezannoni@redhat.com>
* sh.h (EF_SH2E): New.
2003-01-23 Alan Modra <amodra@bigpond.net.au>
* sh.h: Split out various bits to bfd/elf32-sh64.h.

8
include/elf/sh.h
View file

@ -33,6 +33,7 @@
#define EF_SH_HAS_FP(flags) ((flags) & 8)
#define EF_SH3E 8
#define EF_SH4 9
#define EF_SH2E 11
/* This one can only mix in objects from other EF_SH5 objects. */
#define EF_SH5 10
@ -45,6 +46,13 @@
: (((mach1) < EF_SH3 && (mach2) == EF_SH_UNKNOWN) \
|| ((mach2) < EF_SH3 && (mach1) == EF_SH_UNKNOWN)) \
? EF_SH3 \
: ((mach1) == EF_SH2E && EF_SH_HAS_FP (mach2)) \
? (mach2) \
: ((mach2) == EF_SH2E && EF_SH_HAS_FP (mach1)) \
? (mach1) \
: (((mach1) == EF_SH2E && (mach2) == EF_SH_UNKNOWN) \
|| ((mach2) == EF_SH2E && (mach1) == EF_SH_UNKNOWN)) \
? EF_SH2E \
: (((mach1) == EF_SH3E && (mach2) == EF_SH_UNKNOWN) \
|| ((mach2) == EF_SH3E && (mach1) == EF_SH_UNKNOWN)) \
? EF_SH4 \

12
opcodes/ChangeLog
View file

@ -1,3 +1,15 @@
2003-01-23 Nick Clifton <nickc@redhat.com>
* Add sh2e support:
2002-04-02 Alexandre Oliva <aoliva@redhat.com>
* sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e.
* sh-opc.h (arch_sh2e, arch_sh2e_up): New.
(arch_sh2_up): Added sh2e.
(sh_table): Replaced all occurrences of arch_sh3e_up with
arch_sh2e_up, except in fsqrt.
2003-01-23 Alan Modra <amodra@bigpond.net.au>
* sh64-dis.c: Include elf32-sh64.h.

5
opcodes/sh-dis.c
View file

@ -1,5 +1,5 @@
/* Disassemble SH instructions.
Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002
Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
@ -315,6 +315,9 @@ print_insn_sh (memaddr, info)
case bfd_mach_sh2:
target_arch = arch_sh2;
break;
case bfd_mach_sh2e:
target_arch = arch_sh2e;
break;
case bfd_mach_sh_dsp:
target_arch = arch_sh_dsp;
break;

107
opcodes/sh-opc.h
View file

@ -1,5 +1,5 @@
/* Definitions for SH opcodes.
Copyright 1993, 1994, 1995, 1997, 1999, 2000
Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003
Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
@ -16,7 +16,8 @@ You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
typedef enum {
typedef enum
{
HEX_0,
HEX_1,
HEX_2,
@ -65,9 +66,11 @@ typedef enum {
PDC,
PPIC,
REPEAT
} sh_nibble_type;
}
sh_nibble_type;
typedef enum {
typedef enum
{
A_END,
A_BDISP12,
A_BDISP8,
@ -123,8 +126,8 @@ typedef enum {
F_REG_M,
D_REG_N,
D_REG_M,
X_REG_N, /* Only used for argument parsing */
X_REG_M, /* Only used for argument parsing */
X_REG_N, /* Only used for argument parsing. */
X_REG_M, /* Only used for argument parsing. */
DX_REG_N,
DX_REG_M,
V_REG_N,
@ -135,25 +138,30 @@ typedef enum {
FPUL_M,
FPSCR_N,
FPSCR_M
} sh_arg_type;
}
sh_arg_type;
typedef enum {
typedef enum
{
A_A1_NUM = 5,
A_A0_NUM = 7,
A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
} sh_dsp_reg_nums;
}
sh_dsp_reg_nums;
#define arch_sh1 0x0001
#define arch_sh2 0x0002
#define arch_sh3 0x0004
#define arch_sh3e 0x0008
#define arch_sh4 0x0010
#define arch_sh2e 0x0020
#define arch_sh_dsp 0x0100
#define arch_sh3_dsp 0x0200
#define arch_sh1_up (arch_sh1 | arch_sh2_up)
#define arch_sh2_up (arch_sh2 | arch_sh3_up | arch_sh_dsp)
#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
#define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp)
#define arch_sh3e_up (arch_sh3e | arch_sh4_up)
#define arch_sh4_up arch_sh4
@ -161,7 +169,8 @@ typedef enum {
#define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up)
#define arch_sh3_dsp_up arch_sh3_dsp
typedef struct {
typedef struct
{
char *name;
sh_arg_type arg[4];
sh_nibble_type nibbles[4];
@ -170,8 +179,8 @@ typedef struct {
#ifdef DEFINE_TABLE
const sh_opcode_info sh_table[] = {
const sh_opcode_info sh_table[] =
{
/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
@ -306,9 +315,9 @@ const sh_opcode_info sh_table[] = {
/* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh3e_up},
/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh3e_up},
/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
/* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
@ -328,9 +337,9 @@ const sh_opcode_info sh_table[] = {
/* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh3e_up},
/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh3e_up},
/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
@ -551,9 +560,9 @@ const sh_opcode_info sh_table[] = {
/* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh3e_up},
/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh3e_up},
/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
/* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
@ -573,9 +582,9 @@ const sh_opcode_info sh_table[] = {
/* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh3e_up},
/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh3e_up},
/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
/* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
@ -736,57 +745,57 @@ const sh_opcode_info sh_table[] = {
/* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
{"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh3e_up},
/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
/* 1111nnnn01011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up},
/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh3e_up},
/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
/* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up},
/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh3e_up},
/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
/* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up},
/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh3e_up},
/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
/* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up},
/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}, arch_sh4_up},
/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}, arch_sh4_up},
/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh3e_up},
/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
/* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up},
/* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh3e_up},
/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up},
/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh3e_up},
/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up},
/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh3e_up},
/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh3e_up},
/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
/* 1111nnnn00101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up},
/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh3e_up},
/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh3e_up},
/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
/* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up},
/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up},
/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
/* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up},
/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up},
/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
/* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up},
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up},
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
/* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up},
/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up},
/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
/* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up},
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up},
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up},
/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up},
/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
/* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up},
/* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up},
@ -801,22 +810,22 @@ const sh_opcode_info sh_table[] = {
/* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up},
/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up},
/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up},
/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up},
/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up},
/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up},
/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up},
/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh3e_up},
/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
/* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up},
/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh3e_up},
/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
/* 1111nnnn01001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up},
/* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
@ -826,12 +835,12 @@ const sh_opcode_info sh_table[] = {
/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up},
/* 1111nnnn01101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up},
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh3e_up},
/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh3e_up},
/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up},
/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh3e_up},
/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up},
/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up},