bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectures and bfd machine numbers.
This patch adds support for the opcode architectures
SPARC_OPCODE_ARCH_V9{C,D,E,V,M} and its associated BFD machine numbers
bfd_mach_sparc_v9{c,d,e,v,m} and bfd_mach_sparc_v8plus{c,d,e,v,m}.
Note that for arches up to v9b (UltraSPARC III), the detection of the
BFD machine type was based on the bits in the e_machine field of the ELF
header. However, there are no more available bits in that field, so
this patch takes the approach of using the hardware capabilities stored
in the object attributes HWCAPS/HWCAPS2 in order to characterize the
machine the object was built for.
bfd/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* archures.c (bfd_mach_sparc_v8plusc): Define.
(bfd_mach_sparc_v9c): Likewise.
(bfd_mach_sparc_v8plusd): Likewise.
(bfd_mach_sparc_v9d): Likewise.
(bfd_mach_sparc_v8pluse): Likewise.
(bfd_mach_sparc_v9e): Likewise.
(bfd_mach_sparc_v8plusv): Likewise
(bfd_mach_sparc_v9v): Likewise.
(bfd_mach_sparc_v8plusm): Likewise.
(bfd_mach_sparc_v9m): Likewise.
(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
(bfd_mach_sparc_64bit_p): Likewise.
* bfd-in2.h: Regenerate.
* cpu-sparc.c (arch_info_struct): Add entries for
bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
and bfd_mach_sparc_v9{c,d,e,v,m}.
* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
include/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
SPARC_OPCODE_ARCH_V9M.
opcodes/ChangeLog:
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
bfd_mach_sparc_v9{c,d,e,v,m}.
* sparc-opc.c (MASK_V9C): Define.
(MASK_V9D): Likewise.
(MASK_V9E): Likewise.
(MASK_V9V): Likewise.
(MASK_V9M): Likewise.
(v6): Add MASK_V9{C,D,E,V,M}.
(v6notlet): Likewise.
(v7): Likewise.
(v8): Likewise.
(v9): Likewise.
(v9andleon): Likewise.
(v9a): Likewise.
(v9b): Likewise.
(v9c): Define.
(v9d): Likewise.
(v9e): Likewise.
(v9v): Likewise.
(v9m): Likewise.
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
This commit is contained in:
Jose E. Marchesi
parent
e7622e5214
commit
4f26fb3a1b
12 changed files with 382 additions and 16 deletions
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@ -1,3 +1,25 @@
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2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
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* archures.c (bfd_mach_sparc_v8plusc): Define.
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(bfd_mach_sparc_v9c): Likewise.
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(bfd_mach_sparc_v8plusd): Likewise.
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(bfd_mach_sparc_v9d): Likewise.
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(bfd_mach_sparc_v8pluse): Likewise.
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(bfd_mach_sparc_v9e): Likewise.
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(bfd_mach_sparc_v8plusv): Likewise
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(bfd_mach_sparc_v9v): Likewise.
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(bfd_mach_sparc_v8plusm): Likewise.
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(bfd_mach_sparc_v9m): Likewise.
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(bfd_mach_sparc_v9_p): Adapt to v8plusm and v9m.
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(bfd_mach_sparc_64bit_p): Likewise.
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* bfd-in2.h: Regenerate.
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* cpu-sparc.c (arch_info_struct): Add entries for
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bfd_mach_sparc_v8plus{c,d,e,v,m} and bfd_mach_sparc_v9{c,d,e,v,m}.
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* aoutx.h (machine_type): Handle bfd_mach_sparc_v8plus{c,d,e,v,m}
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and bfd_mach_sparc_v9{c,d,e,v,m}.
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* elf32-sparc.c (elf32_sparc_final_write_processing): Likewise.
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* elfxx-sparc.c (_bfd_sparc_elf_object_p): Likewise.
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2016-06-16 H.J. Lu <hongjiu.lu@intel.com>
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* elf32-i386.c (elf_i386_check_relocs): Don't check undefined
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12
bfd/aoutx.h
12
bfd/aoutx.h
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@ -733,9 +733,19 @@ NAME (aout, machine_type) (enum bfd_architecture arch,
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|| machine == bfd_mach_sparc_v8plus
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|| machine == bfd_mach_sparc_v8plusa
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|| machine == bfd_mach_sparc_v8plusb
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|| machine == bfd_mach_sparc_v8plusc
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|| machine == bfd_mach_sparc_v8plusd
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|| machine == bfd_mach_sparc_v8pluse
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|| machine == bfd_mach_sparc_v8plusv
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|| machine == bfd_mach_sparc_v8plusm
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|| machine == bfd_mach_sparc_v9
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|| machine == bfd_mach_sparc_v9a
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|| machine == bfd_mach_sparc_v9b)
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|| machine == bfd_mach_sparc_v9b
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|| machine == bfd_mach_sparc_v9c
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|| machine == bfd_mach_sparc_v9d
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|| machine == bfd_mach_sparc_v9e
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|| machine == bfd_mach_sparc_v9v
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|| machine == bfd_mach_sparc_v9m)
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arch_flags = M_SPARC;
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else if (machine == bfd_mach_sparc_sparclet)
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arch_flags = M_SPARCLET;
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@ -137,13 +137,29 @@ DESCRIPTION
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.#define bfd_mach_sparc_v9a 8 {* with ultrasparc add'ns. *}
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.#define bfd_mach_sparc_v8plusb 9 {* with cheetah add'ns. *}
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.#define bfd_mach_sparc_v9b 10 {* with cheetah add'ns. *}
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.#define bfd_mach_sparc_v8plusc 11 {* with UA2005 and T1 add'ns. *}
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.#define bfd_mach_sparc_v9c 12 {* with UA2005 and T1 add'ns. *}
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.#define bfd_mach_sparc_v8plusd 13 {* with UA2007 and T3 add'ns. *}
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.#define bfd_mach_sparc_v9d 14 {* with UA2007 and T3 add'ns. *}
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.#define bfd_mach_sparc_v8pluse 15 {* with OSA2001 and T4 add'ns (no IMA). *}
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.#define bfd_mach_sparc_v9e 16 {* with OSA2001 and T4 add'ns (no IMA). *}
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.#define bfd_mach_sparc_v8plusv 17 {* with OSA2011 and T4 and IMA and FJMAU add'ns. *}
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.#define bfd_mach_sparc_v9v 18 {* with OSA2011 and T4 and IMA and FJMAU add'ns. *}
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.#define bfd_mach_sparc_v8plusm 19 {* with OSA2015 and M7 add'ns. *}
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.#define bfd_mach_sparc_v9m 20 {* with OSA2015 and M7 add'ns. *}
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.{* Nonzero if MACH has the v9 instruction set. *}
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.#define bfd_mach_sparc_v9_p(mach) \
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. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
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. ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m \
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. && (mach) != bfd_mach_sparc_sparclite_le)
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.{* Nonzero if MACH is a 64 bit sparc architecture. *}
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.#define bfd_mach_sparc_64bit_p(mach) \
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. ((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
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. ((mach) >= bfd_mach_sparc_v9 \
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. && (mach) != bfd_mach_sparc_v8plusb \
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. && (mach) != bfd_mach_sparc_v8plusc \
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. && (mach) != bfd_mach_sparc_v8plusd \
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. && (mach) != bfd_mach_sparc_v8pluse \
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. && (mach) != bfd_mach_sparc_v8plusv \
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. && (mach) != bfd_mach_sparc_v8plusm)
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. bfd_arch_spu, {* PowerPC SPU *}
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.#define bfd_mach_spu 256
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. bfd_arch_mips, {* MIPS Rxxxx *}
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@ -1948,13 +1948,29 @@ enum bfd_architecture
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#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
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#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
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#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
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#define bfd_mach_sparc_v8plusc 11 /* with UA2005 and T1 add'ns. */
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#define bfd_mach_sparc_v9c 12 /* with UA2005 and T1 add'ns. */
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#define bfd_mach_sparc_v8plusd 13 /* with UA2007 and T3 add'ns. */
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#define bfd_mach_sparc_v9d 14 /* with UA2007 and T3 add'ns. */
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#define bfd_mach_sparc_v8pluse 15 /* with OSA2001 and T4 add'ns (no IMA). */
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#define bfd_mach_sparc_v9e 16 /* with OSA2001 and T4 add'ns (no IMA). */
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#define bfd_mach_sparc_v8plusv 17 /* with OSA2011 and T4 and IMA and FJMAU add'ns. */
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#define bfd_mach_sparc_v9v 18 /* with OSA2011 and T4 and IMA and FJMAU add'ns. */
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#define bfd_mach_sparc_v8plusm 19 /* with OSA2015 and M7 add'ns. */
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#define bfd_mach_sparc_v9m 20 /* with OSA2015 and M7 add'ns. */
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/* Nonzero if MACH has the v9 instruction set. */
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#define bfd_mach_sparc_v9_p(mach) \
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((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
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((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9m \
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&& (mach) != bfd_mach_sparc_sparclite_le)
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/* Nonzero if MACH is a 64 bit sparc architecture. */
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#define bfd_mach_sparc_64bit_p(mach) \
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((mach) >= bfd_mach_sparc_v9 && (mach) != bfd_mach_sparc_v8plusb)
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((mach) >= bfd_mach_sparc_v9 \
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&& (mach) != bfd_mach_sparc_v8plusb \
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&& (mach) != bfd_mach_sparc_v8plusc \
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&& (mach) != bfd_mach_sparc_v8plusd \
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&& (mach) != bfd_mach_sparc_v8pluse \
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&& (mach) != bfd_mach_sparc_v8plusv \
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&& (mach) != bfd_mach_sparc_v8plusm)
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bfd_arch_spu, /* PowerPC SPU */
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#define bfd_mach_spu 256
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bfd_arch_mips, /* MIPS Rxxxx */
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150
bfd/cpu-sparc.c
150
bfd/cpu-sparc.c
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@ -157,6 +157,156 @@ static const bfd_arch_info_type arch_info_struct[] =
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[9],
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},
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{
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32, /* bits in a word */
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32, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v8plusc,
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"sparc",
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"sparc:v8plusc",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[10],
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},
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{
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64, /* bits in a word */
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64, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v9c,
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"sparc",
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"sparc:v9c",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[11],
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},
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{
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32, /* bits in a word */
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32, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v8plusd,
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"sparc",
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"sparc:v8plusd",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[12],
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},
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{
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64, /* bits in a word */
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64, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v9d,
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"sparc",
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"sparc:v9d",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[13],
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},
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{
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32, /* bits in a word */
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32, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v8pluse,
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"sparc",
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"sparc:v8pluse",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[14],
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},
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{
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64, /* bits in a word */
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64, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v9e,
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"sparc",
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"sparc:v9e",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[15],
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},
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{
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32, /* bits in a word */
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32, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v8plusv,
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"sparc",
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"sparc:v8plusv",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[16],
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},
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{
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64, /* bits in a word */
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64, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v9v,
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"sparc",
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"sparc:v9v",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[17],
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},
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{
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32, /* bits in a word */
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32, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v8plusm,
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"sparc",
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"sparc:v8plusm",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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&arch_info_struct[18],
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},
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{
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64, /* bits in a word */
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64, /* bits in an address */
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8, /* bits in a byte */
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bfd_arch_sparc,
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bfd_mach_sparc_v9m,
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"sparc",
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"sparc:v9m",
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3,
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FALSE,
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bfd_default_compatible,
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bfd_default_scan,
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bfd_arch_default_fill,
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0,
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}
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};
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@ -136,6 +136,11 @@ elf32_sparc_final_write_processing (bfd *abfd,
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elf_elfheader (abfd)->e_flags |= EF_SPARC_32PLUS | EF_SPARC_SUN_US1;
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break;
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case bfd_mach_sparc_v8plusb :
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case bfd_mach_sparc_v8plusc :
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case bfd_mach_sparc_v8plusd :
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case bfd_mach_sparc_v8pluse :
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case bfd_mach_sparc_v8plusv :
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case bfd_mach_sparc_v8plusm :
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elf_elfheader (abfd)->e_machine = EM_SPARC32PLUS;
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elf_elfheader (abfd)->e_flags &=~ EF_SPARC_32PLUS_MASK;
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elf_elfheader (abfd)->e_flags |= EF_SPARC_32PLUS | EF_SPARC_SUN_US1
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@ -4830,11 +4830,49 @@ _bfd_sparc_elf_finish_dynamic_sections (bfd *output_bfd, struct bfd_link_info *i
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bfd_boolean
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_bfd_sparc_elf_object_p (bfd *abfd)
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{
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obj_attribute *attrs = elf_known_obj_attributes (abfd)[OBJ_ATTR_GNU];
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obj_attribute *hwcaps = &attrs[Tag_GNU_Sparc_HWCAPS];
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obj_attribute *hwcaps2 = &attrs[Tag_GNU_Sparc_HWCAPS2];
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unsigned int v9c_hwcaps_mask = ELF_SPARC_HWCAP_ASI_BLK_INIT;
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unsigned int v9d_hwcaps_mask = (ELF_SPARC_HWCAP_FMAF
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| ELF_SPARC_HWCAP_VIS3
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| ELF_SPARC_HWCAP_HPC);
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unsigned int v9e_hwcaps_mask = (ELF_SPARC_HWCAP_AES
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| ELF_SPARC_HWCAP_DES
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| ELF_SPARC_HWCAP_KASUMI
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| ELF_SPARC_HWCAP_CAMELLIA
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| ELF_SPARC_HWCAP_MD5
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| ELF_SPARC_HWCAP_SHA1
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| ELF_SPARC_HWCAP_SHA256
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| ELF_SPARC_HWCAP_SHA512
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| ELF_SPARC_HWCAP_MPMUL
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| ELF_SPARC_HWCAP_MONT
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| ELF_SPARC_HWCAP_CRC32C
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| ELF_SPARC_HWCAP_CBCOND
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| ELF_SPARC_HWCAP_PAUSE);
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||||
unsigned int v9v_hwcaps_mask = (ELF_SPARC_HWCAP_FJFMAU
|
||||
| ELF_SPARC_HWCAP_IMA);
|
||||
unsigned int v9m_hwcaps2_mask = (ELF_SPARC_HWCAP2_SPARC5
|
||||
| ELF_SPARC_HWCAP2_MWAIT
|
||||
| ELF_SPARC_HWCAP2_XMPMUL
|
||||
| ELF_SPARC_HWCAP2_XMONT);
|
||||
|
||||
if (ABI_64_P (abfd))
|
||||
{
|
||||
unsigned long mach = bfd_mach_sparc_v9;
|
||||
|
||||
if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
|
||||
if (hwcaps2->i & v9m_hwcaps2_mask)
|
||||
mach = bfd_mach_sparc_v9m;
|
||||
else if (hwcaps->i & v9v_hwcaps_mask)
|
||||
mach = bfd_mach_sparc_v9v;
|
||||
else if (hwcaps->i & v9e_hwcaps_mask)
|
||||
mach = bfd_mach_sparc_v9e;
|
||||
else if (hwcaps->i & v9d_hwcaps_mask)
|
||||
mach = bfd_mach_sparc_v9d;
|
||||
else if (hwcaps->i & v9c_hwcaps_mask)
|
||||
mach = bfd_mach_sparc_v9c;
|
||||
else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
|
||||
mach = bfd_mach_sparc_v9b;
|
||||
else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
|
||||
mach = bfd_mach_sparc_v9a;
|
||||
|
|
@ -4844,7 +4882,22 @@ _bfd_sparc_elf_object_p (bfd *abfd)
|
|||
{
|
||||
if (elf_elfheader (abfd)->e_machine == EM_SPARC32PLUS)
|
||||
{
|
||||
if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
|
||||
if (hwcaps2->i & v9m_hwcaps2_mask)
|
||||
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
|
||||
bfd_mach_sparc_v8plusm);
|
||||
else if (hwcaps->i & v9v_hwcaps_mask)
|
||||
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
|
||||
bfd_mach_sparc_v8plusv);
|
||||
else if (hwcaps->i & v9e_hwcaps_mask)
|
||||
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
|
||||
bfd_mach_sparc_v8pluse);
|
||||
else if (hwcaps->i & v9d_hwcaps_mask)
|
||||
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
|
||||
bfd_mach_sparc_v8plusd);
|
||||
else if (hwcaps->i & v9c_hwcaps_mask)
|
||||
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
|
||||
bfd_mach_sparc_v8plusc);
|
||||
else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US3)
|
||||
return bfd_default_set_arch_mach (abfd, bfd_arch_sparc,
|
||||
bfd_mach_sparc_v8plusb);
|
||||
else if (elf_elfheader (abfd)->e_flags & EF_SPARC_SUN_US1)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,10 @@
|
|||
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||||
|
||||
* opcode/sparc.h (enum sparc_opcode_arch_val): Add
|
||||
SPARC_OPCODE_ARCH_V9C, SPARC_OPCODE_ARCH_V9D,
|
||||
SPARC_OPCODE_ARCH_V9E, SPARC_OPCODE_ARCH_V9V and
|
||||
SPARC_OPCODE_ARCH_V9M.
|
||||
|
||||
2016-06-14 John Baldwin <jhb@FreeBSD.org>
|
||||
|
||||
* opcode/msp430-decode.h (MSP430_Size): Remove.
|
||||
|
|
|
|||
|
|
@ -52,6 +52,12 @@ enum sparc_opcode_arch_val
|
|||
SPARC_OPCODE_ARCH_V9,
|
||||
SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
|
||||
SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
|
||||
SPARC_OPCODE_ARCH_V9C, /* V9 with UA2005 and T1 additions. */
|
||||
SPARC_OPCODE_ARCH_V9D, /* V9 with UA2007 and T3 additions. */
|
||||
SPARC_OPCODE_ARCH_V9E, /* V9 with OSA2011 and T4 additions modulus integer multiply-add. */
|
||||
SPARC_OPCODE_ARCH_V9V, /* V9 with OSA2011 and T4 additions, integer
|
||||
multiply and Fujitsu fp multiply-add. */
|
||||
SPARC_OPCODE_ARCH_V9M, /* V9 with OSA2015 and M7 additions. */
|
||||
SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,28 @@
|
|||
2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||||
|
||||
* sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
|
||||
(compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
|
||||
bfd_mach_sparc_v9{c,d,e,v,m}.
|
||||
* sparc-opc.c (MASK_V9C): Define.
|
||||
(MASK_V9D): Likewise.
|
||||
(MASK_V9E): Likewise.
|
||||
(MASK_V9V): Likewise.
|
||||
(MASK_V9M): Likewise.
|
||||
(v6): Add MASK_V9{C,D,E,V,M}.
|
||||
(v6notlet): Likewise.
|
||||
(v7): Likewise.
|
||||
(v8): Likewise.
|
||||
(v9): Likewise.
|
||||
(v9andleon): Likewise.
|
||||
(v9a): Likewise.
|
||||
(v9b): Likewise.
|
||||
(v9c): Define.
|
||||
(v9d): Likewise.
|
||||
(v9e): Likewise.
|
||||
(v9v): Likewise.
|
||||
(v9m): Likewise.
|
||||
(sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
|
||||
|
||||
2016-06-15 Nick Clifton <nickc@redhat.com>
|
||||
|
||||
* nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
|
||||
|
|
|
|||
|
|
@ -28,7 +28,12 @@
|
|||
/* Bitmask of v9 architectures. */
|
||||
#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
|
||||
| (1 << SPARC_OPCODE_ARCH_V9A) \
|
||||
| (1 << SPARC_OPCODE_ARCH_V9B))
|
||||
| (1 << SPARC_OPCODE_ARCH_V9B) \
|
||||
| (1 << SPARC_OPCODE_ARCH_V9C) \
|
||||
| (1 << SPARC_OPCODE_ARCH_V9D) \
|
||||
| (1 << SPARC_OPCODE_ARCH_V9E) \
|
||||
| (1 << SPARC_OPCODE_ARCH_V9V) \
|
||||
| (1 << SPARC_OPCODE_ARCH_V9M))
|
||||
/* 1 if INSN is for v9 only. */
|
||||
#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
|
||||
/* 1 if INSN is for v9. */
|
||||
|
|
@ -241,6 +246,21 @@ compute_arch_mask (unsigned long mach)
|
|||
case bfd_mach_sparc_v8plusb :
|
||||
case bfd_mach_sparc_v9b :
|
||||
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
|
||||
case bfd_mach_sparc_v8plusc :
|
||||
case bfd_mach_sparc_v9c :
|
||||
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C);
|
||||
case bfd_mach_sparc_v8plusd :
|
||||
case bfd_mach_sparc_v9d :
|
||||
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D);
|
||||
case bfd_mach_sparc_v8pluse :
|
||||
case bfd_mach_sparc_v9e :
|
||||
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E);
|
||||
case bfd_mach_sparc_v8plusv :
|
||||
case bfd_mach_sparc_v9v :
|
||||
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V);
|
||||
case bfd_mach_sparc_v8plusm :
|
||||
case bfd_mach_sparc_v9m :
|
||||
return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M);
|
||||
}
|
||||
abort ();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -37,17 +37,25 @@
|
|||
#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
|
||||
#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
|
||||
#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
|
||||
#define MASK_V9C SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C)
|
||||
#define MASK_V9D SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D)
|
||||
#define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E)
|
||||
#define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V)
|
||||
#define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M)
|
||||
|
||||
/* Bit masks of architectures supporting the insn. */
|
||||
|
||||
#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
|
||||
| MASK_SPARCLET | MASK_SPARCLITE \
|
||||
| MASK_V9 | MASK_V9A | MASK_V9B)
|
||||
| MASK_V9 | MASK_V9A | MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
/* v6 insns not supported on the sparclet. */
|
||||
#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
|
||||
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
|
||||
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
#define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \
|
||||
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
|
||||
| MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
/* Although not all insns are implemented in hardware, sparclite is defined
|
||||
to be a superset of v8. Unimplemented insns trap and are then theoretically
|
||||
implemented in software.
|
||||
|
|
@ -55,16 +63,28 @@
|
|||
suggest it is. Rather than complicating things, the sparclet assembler
|
||||
recognizes all v8 insns. */
|
||||
#define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \
|
||||
| MASK_V9 | MASK_V9A | MASK_V9B)
|
||||
| MASK_V9 | MASK_V9A | MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
#define sparclet (MASK_SPARCLET)
|
||||
/* sparclet insns supported by leon. */
|
||||
#define letandleon (MASK_SPARCLET | MASK_LEON)
|
||||
#define sparclite (MASK_SPARCLITE)
|
||||
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
|
||||
#define v9 (MASK_V9 | MASK_V9A | MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
/* v9 insns supported by leon. */
|
||||
#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B | MASK_LEON)
|
||||
#define v9a (MASK_V9A | MASK_V9B)
|
||||
#define v9b (MASK_V9B)
|
||||
#define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \
|
||||
| MASK_LEON)
|
||||
#define v9a (MASK_V9A | MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
#define v9b (MASK_V9B \
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
#define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
#define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
#define v9e (MASK_V9E | MASK_V9V | MASK_V9M)
|
||||
#define v9v (MASK_V9V | MASK_V9M)
|
||||
#define v9m (MASK_V9M)
|
||||
|
||||
/* v6 insns not supported by v9. */
|
||||
#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \
|
||||
| MASK_SPARCLET | MASK_SPARCLITE)
|
||||
|
|
@ -89,6 +109,22 @@ const struct sparc_opcode_arch sparc_opcode_archs[] =
|
|||
{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
|
||||
/* v9 with cheetah additions */
|
||||
{ "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
|
||||
/* v9 with UA2005 and T1 additions. */
|
||||
{ "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
||||
| MASK_V9C) },
|
||||
/* v9 with UA2007 and T3 additions. */
|
||||
{ "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
||||
| MASK_V9C | MASK_V9D) },
|
||||
/* v9 with OSA2011 and T4 additions modulus integer multiply-add. */
|
||||
{ "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E) },
|
||||
/* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp
|
||||
multiply-add. */
|
||||
{ "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V) },
|
||||
/* v9 with OSA2015 and M7 additions. */
|
||||
{ "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
|
||||
| MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) },
|
||||
{ NULL, 0 }
|
||||
};
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue