Remove high bit set characters
gas/ * doc/c-lm32.texi: Fix chars with high bit set. * testsuite/gas/bfin/vector2.s: Likewise. gold/ * arm.cc: Fix comment chars with high bit set. include/ * coff/pe.h: Fix comment chars with high bit set. * opcode/xgate.h: Likewise. ld/ * testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
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10 changed files with 40 additions and 22 deletions
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@ -1,3 +1,8 @@
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2016-12-21 Alan Modra <amodra@gmail.com>
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* doc/c-lm32.texi: Fix chars with high bit set.
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* testsuite/gas/bfin/vector2.s: Likewise.
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2016-12-21 Alan Modra <amodra@gmail.com>
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2016-12-21 Alan Modra <amodra@gmail.com>
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PR gas/10946
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PR gas/10946
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@ -10,7 +10,7 @@
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@ifclear GENERIC
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@ifclear GENERIC
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@node Machine Dependencies
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@node Machine Dependencies
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@chapter LM£" Dependent Features
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@chapter LM32 Dependent Features
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@end ifclear
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@end ifclear
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@cindex LM32 support
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@cindex LM32 support
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@ -93,7 +93,7 @@ r1=r2 +|+ r3 (SCO);
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r4=r3 +|+ r5 (SCO);
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r4=r3 +|+ r5 (SCO);
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r6=r3 +|+ r7 (SCO);
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r6=r3 +|+ r7 (SCO);
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//Dreg = Dreg –|+ Dreg (opt_mode_0) ; /* subtract | add (b) */
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//Dreg = Dreg -|+ Dreg (opt_mode_0) ; /* subtract | add (b) */
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r6=r0 -|+ r1(s) ; /* same as above, subtract|add with saturation */
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r6=r0 -|+ r1(s) ; /* same as above, subtract|add with saturation */
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r0=r1 -|+ r2 ;
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r0=r1 -|+ r2 ;
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@ -125,7 +125,7 @@ r4=r3 -|+ r5 (SCO);
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r6=r3 -|+ r7 (SCO);
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r6=r3 -|+ r7 (SCO);
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//Dreg = Dreg +|– Dreg (opt_mode_0) ; /* add | subtract (b) */
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//Dreg = Dreg +|- Dreg (opt_mode_0) ; /* add | subtract (b) */
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r0=r2 +|- r1(co) ; /* add|subtract with half-word results crossed over in the destination register */
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r0=r2 +|- r1(co) ; /* add|subtract with half-word results crossed over in the destination register */
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r0=r1 +|- r2 ;
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r0=r1 +|- r2 ;
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@ -156,7 +156,7 @@ r1=r2 +|- r3 (SCO);
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r4=r3 +|- r5 (SCO);
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r4=r3 +|- r5 (SCO);
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r6=r3 +|- r7 (SCO);
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r6=r3 +|- r7 (SCO);
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//Dreg = Dreg –|– Dreg (opt_mode_0) ; /* subtract | subtract (b) */
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//Dreg = Dreg -|- Dreg (opt_mode_0) ; /* subtract | subtract (b) */
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r7=r3 -|- r6(sco) ; /* subtract|subtract with saturation and half-word results crossed over in the destination register */
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r7=r3 -|- r6(sco) ; /* subtract|subtract with saturation and half-word results crossed over in the destination register */
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r0=r1 -|- r2 ;
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r0=r1 -|- r2 ;
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@ -188,7 +188,7 @@ r4=r3 -|- r5 (SCO);
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r6=r3 -|- r7 (SCO);
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r6=r3 -|- r7 (SCO);
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//Quad 16-Bit Operations
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//Quad 16-Bit Operations
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//Dreg = Dreg +|+ Dreg, Dreg = Dreg –|– Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */
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//Dreg = Dreg +|+ Dreg, Dreg = Dreg -|- Dreg (opt_mode_0,opt_mode_2) ; /* add | add, subtract | subtract; the set of source registers must be the same for each operation (b) */
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r5=r3 +|+ r4, r7=r3-|-r4 ; /* quad 16-bit operations, add|add, subtract|subtract */
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r5=r3 +|+ r4, r7=r3-|-r4 ; /* quad 16-bit operations, add|add, subtract|subtract */
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r0=r1 +|+ r2, r7=r1 -|- r2;
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r0=r1 +|+ r2, r7=r1 -|- r2;
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@ -284,7 +284,7 @@ r4=r3 +|+ r5, r3=r3 -|- r5(SCO,ASL);
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r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASL);
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r6=r3 +|+ r7, r2=r3 -|- r7(SCO,ASL);
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//Dreg = Dreg +|– Dreg, Dreg = Dreg –|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */
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//Dreg = Dreg +|- Dreg, Dreg = Dreg -|+ Dreg (opt_mode_0,opt_mode_2) ; /* add | subtract, subtract | add; the set of source registers must be the same for each operation (b) */
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r5=r3 +|- r4, r7=r3 -|+ r4 ; /* quad 16-bit operations, add|subtract, subtract|add */
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r5=r3 +|- r4, r7=r3 -|+ r4 ; /* quad 16-bit operations, add|subtract, subtract|add */
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r0=r1 +|- r2, r7=r1 -|+ r2;
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r0=r1 +|- r2, r7=r1 -|+ r2;
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@ -1,3 +1,7 @@
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2016-12-21 Alan Modra <amodra@gmail.com>
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* arm.cc: Fix comment chars with high bit set.
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2016-12-20 Cary Coutant <ccoutant@gmail.com>
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2016-12-20 Cary Coutant <ccoutant@gmail.com>
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* testsuite/Makefile.am: Add missing dependencies on gcctestdir/ld
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* testsuite/Makefile.am: Add missing dependencies on gcctestdir/ld
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@ -3424,7 +3424,7 @@ class Arm_relocate_functions : public Relocate_functions<32, big_endian>
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const Symbol_value<32>* psymval, Arm_address address,
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const Symbol_value<32>* psymval, Arm_address address,
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Arm_address thumb_bit);
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Arm_address thumb_bit);
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// R_ARM_THM_JUMP6: S + A – P
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// R_ARM_THM_JUMP6: S + A - P
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static inline typename This::Status
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static inline typename This::Status
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thm_jump6(unsigned char* view,
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thm_jump6(unsigned char* view,
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const Sized_relobj_file<32, big_endian>* object,
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const Sized_relobj_file<32, big_endian>* object,
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@ -3435,7 +3435,7 @@ class Arm_relocate_functions : public Relocate_functions<32, big_endian>
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typedef typename elfcpp::Swap<16, big_endian>::Valtype Reltype;
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typedef typename elfcpp::Swap<16, big_endian>::Valtype Reltype;
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Valtype* wv = reinterpret_cast<Valtype*>(view);
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Valtype* wv = reinterpret_cast<Valtype*>(view);
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Valtype val = elfcpp::Swap<16, big_endian>::readval(wv);
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Valtype val = elfcpp::Swap<16, big_endian>::readval(wv);
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// bit[9]:bit[7:3]:’0’ (mask: 0x02f8)
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// bit[9]:bit[7:3]:'0' (mask: 0x02f8)
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Reltype addend = (((val & 0x0200) >> 3) | ((val & 0x00f8) >> 2));
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Reltype addend = (((val & 0x0200) >> 3) | ((val & 0x00f8) >> 2));
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Reltype x = (psymval->value(object, addend) - address);
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Reltype x = (psymval->value(object, addend) - address);
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val = (val & 0xfd07) | ((x & 0x0040) << 3) | ((val & 0x003e) << 2);
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val = (val & 0xfd07) | ((x & 0x0040) << 3) | ((val & 0x003e) << 2);
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@ -3446,7 +3446,7 @@ class Arm_relocate_functions : public Relocate_functions<32, big_endian>
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: This::STATUS_OKAY);
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: This::STATUS_OKAY);
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}
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}
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// R_ARM_THM_JUMP8: S + A – P
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// R_ARM_THM_JUMP8: S + A - P
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static inline typename This::Status
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static inline typename This::Status
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thm_jump8(unsigned char* view,
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thm_jump8(unsigned char* view,
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const Sized_relobj_file<32, big_endian>* object,
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const Sized_relobj_file<32, big_endian>* object,
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: This::STATUS_OKAY);
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: This::STATUS_OKAY);
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}
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}
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// R_ARM_THM_JUMP11: S + A – P
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// R_ARM_THM_JUMP11: S + A - P
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static inline typename This::Status
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static inline typename This::Status
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thm_jump11(unsigned char* view,
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thm_jump11(unsigned char* view,
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const Sized_relobj_file<32, big_endian>* object,
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const Sized_relobj_file<32, big_endian>* object,
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@ -1,3 +1,8 @@
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2016-12-21 Alan Modra <amodra@gmail.com>
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* coff/pe.h: Fix comment chars with high bit set.
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* opcode/xgate.h: Likewise.
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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2016-12-20 Maciej W. Rozycki <macro@imgtec.com>
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* opcode/mips.h (mips_opcode_32bit_p): New inline function.
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* opcode/mips.h (mips_opcode_32bit_p): New inline function.
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@ -604,7 +604,7 @@ struct external_IMAGE_DEBUG_DIRECTORY
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#define CVINFO_PDB70_CVSIGNATURE 0x53445352 // "RSDS"
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#define CVINFO_PDB70_CVSIGNATURE 0x53445352 // "RSDS"
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#define CVINFO_PDB20_CVSIGNATURE 0x3031424e // "NB10"
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#define CVINFO_PDB20_CVSIGNATURE 0x3031424e // "NB10"
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#define CVINFO_CV50_CVSIGNATURE 0x3131424e // "NB11"
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#define CVINFO_CV50_CVSIGNATURE 0x3131424e // "NB11"
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#define CVINFO_CV41_CVSIGNATURE 0x3930424e // âNB09"
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#define CVINFO_CV41_CVSIGNATURE 0x3930424e // "NB09"
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typedef struct _CV_INFO_PDB70
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typedef struct _CV_INFO_PDB70
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{
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{
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#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */
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#define XGATE_C_BIT 0x01 /* XGC - Carry Flag */
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/* Access Detail Notation
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/* Access Detail Notation
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V — Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
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V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
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P — Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
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P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
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r — 8-bit data read: lasts for at least one RISC core cycle
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r - 8-bit data read: lasts for at least one RISC core cycle
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R — 16-bit data read: lasts for at least one RISC core cycle
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R - 16-bit data read: lasts for at least one RISC core cycle
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w — 8-bit data write: lasts for at least one RISC core cycle
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w - 8-bit data write: lasts for at least one RISC core cycle
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W — 16-bit data write: lasts for at least one RISC core cycle
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W - 16-bit data write: lasts for at least one RISC core cycle
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A — Alignment cycle: no read or write, lasts for zero or one RISC core cycles
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A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
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f — Free cycle: no read or write, lasts for one RISC core cycles. */
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f - Free cycle: no read or write, lasts for one RISC core cycles. */
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#define XGATE_CYCLE_V 0x01
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#define XGATE_CYCLE_V 0x01
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#define XGATE_CYCLE_P 0x02
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#define XGATE_CYCLE_P 0x02
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#define XGATE_CYCLE_r 0x04
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#define XGATE_CYCLE_r 0x04
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@ -1,3 +1,7 @@
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2016-12-21 Alan Modra <amodra@gmail.com>
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* testsuite/ld-scripts/sysroot-prefix.exp: Fix chars with high bit set.
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2016-12-16 fincs <fincs.alt1@gmail.com>
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2016-12-16 fincs <fincs.alt1@gmail.com>
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* ld.texinfo: Document --gc-keep-exported.
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* ld.texinfo: Document --gc-keep-exported.
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@ -81,7 +81,7 @@ proc sysroot_prefix_test_setup { } {
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global as gasopt srcdir subdir ar
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global as gasopt srcdir subdir ar
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if {![ld_assemble_flags $as $gasopt $srcdir/$subdir/pr14962a.s tmpdir/main.o]} {
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if {![ld_assemble_flags $as $gasopt $srcdir/$subdir/pr14962a.s tmpdir/main.o]} {
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error "Error assembling a trivial file for sysroot-prefix tests framework"
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error "Error assembling a trivial file for sysroot-prefix tests framework"
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return 0
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return 0
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}
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}
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set libnamebase [lindex $test_object 2]
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set libnamebase [lindex $test_object 2]
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if ![ld_assemble_flags $as $gasopt $srcdir/$subdir/$sname $oname] {
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if ![ld_assemble_flags $as $gasopt $srcdir/$subdir/$sname $oname] {
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error "Error assembling trivial file $sname for sysroot-prefix tests framework"
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error "Error assembling trivial file $sname for sysroot-prefix tests framework"
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return 0
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return 0
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}
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}
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if { [string length $libnamebase] != 0 &&
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if { [string length $libnamebase] != 0 &&
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![ar_simple_create $ar "" tmpdir/sysroot/tmp/ldtest-xyzzy/lib$libnamebase.a $oname] } {
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![ar_simple_create $ar "" tmpdir/sysroot/tmp/ldtest-xyzzy/lib$libnamebase.a $oname] } {
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error "Error creating archive $libnamebase for sysroot-prefix tests framework"
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error "Error creating archive $libnamebase for sysroot-prefix tests framework"
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return 0
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return 0
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}
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}
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}
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}
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