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* include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}

Browse source 
to R_ARM_LDC_SB_G{0,1,2} respectively.

bfd/
	* bfd-in2.h: Regenerate.
	* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
	R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
	R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
	R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
	R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
	R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
	R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
	R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
	R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
	R_ARM_LDC_SB_G2): New relocation types.
	(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
	adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
	and friends.
	(elf32_arm_howto_table_3): Delete; contents merged into
	elf32_arm_howto_table_2.
	(elf32_arm_howto_from_type): Adjust correspondingly.
	(elf32_arm_reloc_map): Extend with the above relocations.
	(calculate_group_reloc_mask): New function.
	(identify_add_or_sub): New function.
	(elf32_arm_final_link_relocate): Support for the above
	relocations.
	* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
	codes to correspond to the above relocations.

gas/
	* config/tc-arm.c (enum parse_operand_result): New.
	(struct group_reloc_table_entry): New.
	(enum group_reloc_type): New.
	(group_reloc_table): New array.
	(find_group_reloc_table_entry): New function.
	(parse_shifter_operand_group_reloc): New function.
	(parse_address_main): New function, incorporating code
	from the old parse_address function.  To be used via...
	(parse_address): wrapper for parse_address_main; and
	(parse_address_group_reloc): new function, likewise.
	(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
	OP_ADDRGLDRS, OP_ADDRGLDC.
	(parse_operands): Support for these new operand codes.
	New macro po_misc_or_fail_no_backtrack.
	(encode_arm_cp_address): Preserve group relocations.
	(insns): Modify to use the above operand codes where group
	relocations are permitted.
	(md_apply_fix): Handle the group relocations
	ALU_PC_G0_NC through LDC_SB_G2.
	(tc_gen_reloc): Likewise.
	(arm_force_relocation): Leave group relocations for the linker.
	(arm_fix_adjustable): Likewise.

gas/testsuite/
	* gas/arm/group-reloc-alu.d: New test.
	* gas/arm/group-reloc-alu-encoding-bad.d: New test.
	* gas/arm/group-reloc-alu-encoding-bad.l: New test.
	* gas/arm/group-reloc-alu-encoding-bad.s: New test.
	* gas/arm/group-reloc-alu-parsing-bad.d: New test.
	* gas/arm/group-reloc-alu-parsing-bad.l: New test.
	* gas/arm/group-reloc-alu-parsing-bad.s: New test.
	* gas/arm/group-reloc-alu.s: New test.
	* gas/arm/group-reloc-ldc.d: New test.
	* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
	* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
	* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
	* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
	* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
	* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
	* gas/arm/group-reloc-ldc.s: New test.
	* gas/arm/group-reloc-ldr.d: New test.
	* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
	* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
	* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
	* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
	* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
	* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
	* gas/arm/group-reloc-ldr.s: New test.
	* gas/arm/group-reloc-ldrs.d: New test.
	* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
	* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
	* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
	* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
	* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
	* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
	* gas/arm/group-reloc-ldrs.s: New test.

ld/testsuite/
	* ld-arm/group-relocs-alu-bad.d: New test.
	* ld-arm/group-relocs-alu-bad.s: New test.
	* ld-arm/group-relocs.d: New test.
	* ld-arm/group-relocs-ldc-bad.d: New test.
	* ld-arm/group-relocs-ldc-bad.s: New test.
	* ld-arm/group-relocs-ldr-bad.d: New test.
	* ld-arm/group-relocs-ldr-bad.s: New test.
	* ld-arm/group-relocs-ldrs-bad.d: New test.
	* ld-arm/group-relocs-ldrs-bad.s: New test.
	* ld-arm/group-relocs.s: New test.
	* ld-arm/arm-elf.exp: Wire in new tests.
This commit is contained in:
Mark Shinwell 2006-06-15 11:03:02 +00:00
parent cd2f129fb4
commit 4962c51a67
54 changed files with 5299 additions and 90 deletions
Download patch file Download diff file Expand all files Collapse all files

5
ChangeLog
View file

@ -1,3 +1,8 @@
2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
* include/elf/arm.h: Correct names of R_ARM_LDC_G{0,1,2}
to R_ARM_LDC_SB_G{0,1,2} respectively.
2006-06-15 Paolo Bonzini <bonzini@gnu.org>
* Makefile.tpl (POSTSTAGE1_HOST_EXPORTS): Export CFLAGS and LDFLAGS

27
bfd/ChangeLog
View file

@ -1,3 +1,30 @@
2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
* bfd-in2.h: Regenerate.
* elf32-arm.c (R_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0,
R_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1, R_ARM_ALU_PC_G2,
R_ARM_LDR_PC_G1, R_ARM_LDR_PC_G2, R_ARM_LDRS_PC_G0,
R_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G2, R_ARM_LDC_PC_G0,
R_ARM_LDC_PC_G1, R_ARM_LDC_PC_G2, R_ARM_ALU_SB_G0_NC,
R_ARM_ALU_SB_G0, R_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1,
R_ARM_ALU_SB_G2, R_ARM_LDR_SB_G0, R_ARM_LDR_SB_G1,
R_ARM_LDR_SB_G2, R_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G1,
R_ARM_LDRS_SB_G2, R_ARM_LDC_SB_G0, R_ARM_LDC_SB_G1,
R_ARM_LDC_SB_G2): New relocation types.
(R_ARM_PC13): Rename to AAELF name R_ARM_LDR_PC_G0 and
adjust HOWTO entry to be consistent with R_ARM_LDR_PC_G1
and friends.
(elf32_arm_howto_table_3): Delete; contents merged into
elf32_arm_howto_table_2.
(elf32_arm_howto_from_type): Adjust correspondingly.
(elf32_arm_reloc_map): Extend with the above relocations.
(calculate_group_reloc_mask): New function.
(identify_add_or_sub): New function.
(elf32_arm_final_link_relocate): Support for the above
relocations.
* reloc.c: Add enumeration entries for BFD_RELOC_ARM_...
codes to correspond to the above relocations.
2006-06-14 Richard Sandiford <richard@codesourcery.com>
* elf32-m68k.c (elf_m68k_plt_info): New structure.

30
bfd/bfd-in2.h
View file

@ -2931,6 +2931,36 @@ pc-relative or some form of GOT-indirect relocation. */
BFD_RELOC_ARM_TLS_IE32,
BFD_RELOC_ARM_TLS_LE32,
/* ARM group relocations. */
BFD_RELOC_ARM_ALU_PC_G0_NC,
BFD_RELOC_ARM_ALU_PC_G0,
BFD_RELOC_ARM_ALU_PC_G1_NC,
BFD_RELOC_ARM_ALU_PC_G1,
BFD_RELOC_ARM_ALU_PC_G2,
BFD_RELOC_ARM_LDR_PC_G0,
BFD_RELOC_ARM_LDR_PC_G1,
BFD_RELOC_ARM_LDR_PC_G2,
BFD_RELOC_ARM_LDRS_PC_G0,
BFD_RELOC_ARM_LDRS_PC_G1,
BFD_RELOC_ARM_LDRS_PC_G2,
BFD_RELOC_ARM_LDC_PC_G0,
BFD_RELOC_ARM_LDC_PC_G1,
BFD_RELOC_ARM_LDC_PC_G2,
BFD_RELOC_ARM_ALU_SB_G0_NC,
BFD_RELOC_ARM_ALU_SB_G0,
BFD_RELOC_ARM_ALU_SB_G1_NC,
BFD_RELOC_ARM_ALU_SB_G1,
BFD_RELOC_ARM_ALU_SB_G2,
BFD_RELOC_ARM_LDR_SB_G0,
BFD_RELOC_ARM_LDR_SB_G1,
BFD_RELOC_ARM_LDR_SB_G2,
BFD_RELOC_ARM_LDRS_SB_G0,
BFD_RELOC_ARM_LDRS_SB_G1,
BFD_RELOC_ARM_LDRS_SB_G2,
BFD_RELOC_ARM_LDC_SB_G0,
BFD_RELOC_ARM_LDC_SB_G1,
BFD_RELOC_ARM_LDC_SB_G2,
/* These relocs are only used within the ARM assembler. They are not
(at present) written to any object files. */
BFD_RELOC_ARM_IMMEDIATE,

897
bfd/elf32-arm.c
View file

@ -130,19 +130,19 @@ static reloc_howto_type elf32_arm_howto_table_1[] =
TRUE), /* pcrel_offset */
/* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
HOWTO (R_ARM_PC13, /* type */
HOWTO (R_ARM_LDR_PC_G0, /* type */
0, /* rightshift */
0, /* size (0 = byte, 1 = short, 2 = long) */
8, /* bitsize */
FALSE, /* pc_relative */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_bitfield,/* complain_on_overflow */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_PC13", /* name */
"R_ARM_LDR_PC_G0", /* name */
FALSE, /* partial_inplace */
0x000000ff, /* src_mask */
0x000000ff, /* dst_mask */
FALSE), /* pcrel_offset */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* 16 bit absolute */
HOWTO (R_ARM_ABS16, /* type */
@ -884,13 +884,389 @@ static reloc_howto_type elf32_arm_howto_table_1[] =
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
FALSE), /* pcrel_offset */
};
/* Relocations 57 .. 83 are the "group relocations" which we do not
support. */
/* Group relocations. */
HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_PC_G0_NC", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_PC_G0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_PC_G0", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_PC_G1_NC", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_PC_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_PC_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_PC_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_PC_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDR_PC_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDR_PC_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDR_PC_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDR_PC_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDRS_PC_G0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDRS_PC_G0", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDRS_PC_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDRS_PC_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDRS_PC_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDRS_PC_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDC_PC_G0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDC_PC_G0", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDC_PC_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDC_PC_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDC_PC_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDC_PC_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_SB_G0_NC", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_SB_G0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_SB_G0", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_SB_G1_NC", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_SB_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_SB_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_ALU_SB_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_ALU_SB_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDR_SB_G0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDR_SB_G0", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDR_SB_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDR_SB_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDR_SB_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDR_SB_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDRS_SB_G0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDRS_SB_G0", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDRS_SB_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDRS_SB_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDRS_SB_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDRS_SB_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDC_SB_G0, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDC_SB_G0", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDC_SB_G1, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDC_SB_G1", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
HOWTO (R_ARM_LDC_SB_G2, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
32, /* bitsize */
TRUE, /* pc_relative */
0, /* bitpos */
complain_overflow_dont,/* complain_on_overflow */
bfd_elf_generic_reloc, /* special_function */
"R_ARM_LDC_SB_G2", /* name */
FALSE, /* partial_inplace */
0xffffffff, /* src_mask */
0xffffffff, /* dst_mask */
TRUE), /* pcrel_offset */
/* End of group relocations. */
static reloc_howto_type elf32_arm_howto_table_2[] =
{
HOWTO (R_ARM_MOVW_BREL_NC, /* type */
0, /* rightshift */
2, /* size (0 = byte, 1 = short, 2 = long) */
@ -1230,7 +1606,7 @@ static reloc_howto_type elf32_arm_howto_table_2[] =
249-255 extended, currently unused, relocations: */
static reloc_howto_type elf32_arm_howto_table_3[4] =
static reloc_howto_type elf32_arm_howto_table_2[4] =
{
HOWTO (R_ARM_RREL32, /* type */
0, /* rightshift */
@ -1295,13 +1671,9 @@ elf32_arm_howto_from_type (unsigned int r_type)
if (r_type < NUM_ELEM (elf32_arm_howto_table_1))
return &elf32_arm_howto_table_1[r_type];
if (r_type >= R_ARM_MOVW_BREL_NC
&& r_type < R_ARM_MOVW_BREL_NC + NUM_ELEM (elf32_arm_howto_table_2))
return &elf32_arm_howto_table_2[r_type - R_ARM_MOVW_BREL_NC];
if (r_type >= R_ARM_RREL32
&& r_type < R_ARM_RREL32 + NUM_ELEM (elf32_arm_howto_table_2))
return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
return &elf32_arm_howto_table_2[r_type - R_ARM_RREL32];
return NULL;
}
@ -1374,6 +1746,34 @@ static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
{BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
{BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
{BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
{BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
{BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
{BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
{BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
{BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
{BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
{BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
{BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
{BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
{BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
{BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
{BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
{BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
{BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
{BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
{BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
{BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
{BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
{BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
{BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
{BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
{BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
{BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
{BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
{BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
{BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
{BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
{BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2}
};
static reloc_howto_type *
@ -2964,6 +3364,74 @@ elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
return bfd_reloc_ok;
}
/* For a given value of n, calculate the value of G_n as required to
deal with group relocations. We return it in the form of an
encoded constant-and-rotation, together with the final residual. If n is
specified as less than zero, then final_residual is filled with the
input value and no further action is performed. */
static bfd_vma
calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
{
int current_n;
bfd_vma g_n;
bfd_vma encoded_g_n = 0;
bfd_vma residual = value; /* Also known as Y_n. */
for (current_n = 0; current_n <= n; current_n++)
{
int shift;
/* Calculate which part of the value to mask. */
if (residual == 0)
shift = 0;
else
{
int msb;
/* Determine the most significant bit in the residual and
align the resulting value to a 2-bit boundary. */
for (msb = 30; msb >= 0; msb -= 2)
if (residual & (3 << msb))
break;
/* The desired shift is now (msb - 6), or zero, whichever
is the greater. */
shift = msb - 6;
if (shift < 0)
shift = 0;
}
/* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
g_n = residual & (0xff << shift);
encoded_g_n = (g_n >> shift)
| ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
/* Calculate the residual for the next time around. */
residual &= ~g_n;
}
*final_residual = residual;
return encoded_g_n;
}
/* Given an ARM instruction, determine whether it is an ADD or a SUB.
Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
static int
identify_add_or_sub(bfd_vma insn)
{
int opcode = insn & 0x1e00000;
if (opcode == 1 << 23) /* ADD */
return 1;
if (opcode == 1 << 22) /* SUB */
return -1;
return 0;
}
/* Perform a relocation as part of a final link. */
static bfd_reloc_status_type
@ -4187,6 +4655,397 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
}
return bfd_reloc_ok;
case R_ARM_ALU_PC_G0_NC:
case R_ARM_ALU_PC_G1_NC:
case R_ARM_ALU_PC_G0:
case R_ARM_ALU_PC_G1:
case R_ARM_ALU_PC_G2:
case R_ARM_ALU_SB_G0_NC:
case R_ARM_ALU_SB_G1_NC:
case R_ARM_ALU_SB_G0:
case R_ARM_ALU_SB_G1:
case R_ARM_ALU_SB_G2:
{
bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
bfd_vma pc = input_section->output_section->vma
+ input_section->output_offset + rel->r_offset;
/* sb should be the origin of the *segment* containing the symbol.
It is not clear how to obtain this OS-dependent value, so we
make an arbitrary choice of zero. */
bfd_vma sb = 0;
bfd_vma residual;
bfd_vma g_n;
bfd_signed_vma signed_value;
int group = 0;
/* Determine which group of bits to select. */
switch (r_type)
{
case R_ARM_ALU_PC_G0_NC:
case R_ARM_ALU_PC_G0:
case R_ARM_ALU_SB_G0_NC:
case R_ARM_ALU_SB_G0:
group = 0;
break;
case R_ARM_ALU_PC_G1_NC:
case R_ARM_ALU_PC_G1:
case R_ARM_ALU_SB_G1_NC:
case R_ARM_ALU_SB_G1:
group = 1;
break;
case R_ARM_ALU_PC_G2:
case R_ARM_ALU_SB_G2:
group = 2;
break;
default:
abort();
}
/* If REL, extract the addend from the insn. If RELA, it will
have already been fetched for us. */
if (globals->use_rel)
{
int negative;
bfd_vma constant = insn & 0xff;
bfd_vma rotation = (insn & 0xf00) >> 8;
if (rotation == 0)
signed_addend = constant;
else
{
/* Compensate for the fact that in the instruction, the
rotation is stored in multiples of 2 bits. */
rotation *= 2;
/* Rotate "constant" right by "rotation" bits. */
signed_addend = (constant >> rotation) |
(constant << (8 * sizeof (bfd_vma) - rotation));
}
/* Determine if the instruction is an ADD or a SUB.
(For REL, this determines the sign of the addend.) */
negative = identify_add_or_sub (insn);
if (negative == 0)
{
(*_bfd_error_handler)
(_("%B(%A+0x%lx): Only ADD or SUB instructions are allowed for ALU group relocations"),
input_bfd, input_section,
(long) rel->r_offset, howto->name);
return bfd_reloc_overflow;
}
signed_addend *= negative;
}
/* Compute the value (X) to go in the place. */
if (r_type == R_ARM_ALU_PC_G0_NC
|| r_type == R_ARM_ALU_PC_G1_NC
|| r_type == R_ARM_ALU_PC_G0
|| r_type == R_ARM_ALU_PC_G1
|| r_type == R_ARM_ALU_PC_G2)
/* PC relative. */
signed_value = value - pc + signed_addend;
else
/* Section base relative. */
signed_value = value - sb + signed_addend;
/* If the target symbol is a Thumb function, then set the
Thumb bit in the address. */
if (sym_flags == STT_ARM_TFUNC)
signed_value |= 1;
/* Calculate the value of the relevant G_n, in encoded
constant-with-rotation format. */
g_n = calculate_group_reloc_mask (abs (signed_value), group,
&residual);
/* Check for overflow if required. */
if ((r_type == R_ARM_ALU_PC_G0
|| r_type == R_ARM_ALU_PC_G1
|| r_type == R_ARM_ALU_PC_G2
|| r_type == R_ARM_ALU_SB_G0
|| r_type == R_ARM_ALU_SB_G1
|| r_type == R_ARM_ALU_SB_G2) && residual != 0)
{
(*_bfd_error_handler)
(_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
input_bfd, input_section,
(long) rel->r_offset, abs (signed_value), howto->name);
return bfd_reloc_overflow;
}
/* Mask out the value and the ADD/SUB part of the opcode; take care
not to destroy the S bit. */
insn &= 0xff1ff000;
/* Set the opcode according to whether the value to go in the
place is negative. */
if (signed_value < 0)
insn |= 1 << 22;
else
insn |= 1 << 23;
/* Encode the offset. */
insn |= g_n;
bfd_put_32 (input_bfd, insn, hit_data);
}
return bfd_reloc_ok;
case R_ARM_LDR_PC_G0:
case R_ARM_LDR_PC_G1:
case R_ARM_LDR_PC_G2:
case R_ARM_LDR_SB_G0:
case R_ARM_LDR_SB_G1:
case R_ARM_LDR_SB_G2:
{
bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
bfd_vma pc = input_section->output_section->vma
+ input_section->output_offset + rel->r_offset;
bfd_vma sb = 0; /* See note above. */
bfd_vma residual;
bfd_signed_vma signed_value;
int group = 0;
/* Determine which groups of bits to calculate. */
switch (r_type)
{
case R_ARM_LDR_PC_G0:
case R_ARM_LDR_SB_G0:
group = 0;
break;
case R_ARM_LDR_PC_G1:
case R_ARM_LDR_SB_G1:
group = 1;
break;
case R_ARM_LDR_PC_G2:
case R_ARM_LDR_SB_G2:
group = 2;
break;
default:
abort();
}
/* If REL, extract the addend from the insn. If RELA, it will
have already been fetched for us. */
if (globals->use_rel)
{
int negative = (insn & (1 << 23)) ? 1 : -1;
signed_addend = negative * (insn & 0xfff);
}
/* Compute the value (X) to go in the place. */
if (r_type == R_ARM_LDR_PC_G0
|| r_type == R_ARM_LDR_PC_G1
|| r_type == R_ARM_LDR_PC_G2)
/* PC relative. */
signed_value = value - pc + signed_addend;
else
/* Section base relative. */
signed_value = value - sb + signed_addend;
/* Calculate the value of the relevant G_{n-1} to obtain
the residual at that stage. */
calculate_group_reloc_mask (abs (signed_value), group - 1, &residual);
/* Check for overflow. */
if (residual >= 0x1000)
{
(*_bfd_error_handler)
(_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
input_bfd, input_section,
(long) rel->r_offset, abs (signed_value), howto->name);
return bfd_reloc_overflow;
}
/* Mask out the value and U bit. */
insn &= 0xff7ff000;
/* Set the U bit if the value to go in the place is non-negative. */
if (signed_value >= 0)
insn |= 1 << 23;
/* Encode the offset. */
insn |= residual;
bfd_put_32 (input_bfd, insn, hit_data);
}
return bfd_reloc_ok;
case R_ARM_LDRS_PC_G0:
case R_ARM_LDRS_PC_G1:
case R_ARM_LDRS_PC_G2:
case R_ARM_LDRS_SB_G0:
case R_ARM_LDRS_SB_G1:
case R_ARM_LDRS_SB_G2:
{
bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
bfd_vma pc = input_section->output_section->vma
+ input_section->output_offset + rel->r_offset;
bfd_vma sb = 0; /* See note above. */
bfd_vma residual;
bfd_signed_vma signed_value;
int group = 0;
/* Determine which groups of bits to calculate. */
switch (r_type)
{
case R_ARM_LDRS_PC_G0:
case R_ARM_LDRS_SB_G0:
group = 0;
break;
case R_ARM_LDRS_PC_G1:
case R_ARM_LDRS_SB_G1:
group = 1;
break;
case R_ARM_LDRS_PC_G2:
case R_ARM_LDRS_SB_G2:
group = 2;
break;
default:
abort();
}
/* If REL, extract the addend from the insn. If RELA, it will
have already been fetched for us. */
if (globals->use_rel)
{
int negative = (insn & (1 << 23)) ? 1 : -1;
signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
}
/* Compute the value (X) to go in the place. */
if (r_type == R_ARM_LDRS_PC_G0
|| r_type == R_ARM_LDRS_PC_G1
|| r_type == R_ARM_LDRS_PC_G2)
/* PC relative. */
signed_value = value - pc + signed_addend;
else
/* Section base relative. */
signed_value = value - sb + signed_addend;
/* Calculate the value of the relevant G_{n-1} to obtain
the residual at that stage. */
calculate_group_reloc_mask (abs (signed_value), group - 1, &residual);
/* Check for overflow. */
if (residual >= 0x100)
{
(*_bfd_error_handler)
(_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
input_bfd, input_section,
(long) rel->r_offset, abs (signed_value), howto->name);
return bfd_reloc_overflow;
}
/* Mask out the value and U bit. */
insn &= 0xff7ff0f0;
/* Set the U bit if the value to go in the place is non-negative. */
if (signed_value >= 0)
insn |= 1 << 23;
/* Encode the offset. */
insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
bfd_put_32 (input_bfd, insn, hit_data);
}
return bfd_reloc_ok;
case R_ARM_LDC_PC_G0:
case R_ARM_LDC_PC_G1:
case R_ARM_LDC_PC_G2:
case R_ARM_LDC_SB_G0:
case R_ARM_LDC_SB_G1:
case R_ARM_LDC_SB_G2:
{
bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
bfd_vma pc = input_section->output_section->vma
+ input_section->output_offset + rel->r_offset;
bfd_vma sb = 0; /* See note above. */
bfd_vma residual;
bfd_signed_vma signed_value;
int group = 0;
/* Determine which groups of bits to calculate. */
switch (r_type)
{
case R_ARM_LDC_PC_G0:
case R_ARM_LDC_SB_G0:
group = 0;
break;
case R_ARM_LDC_PC_G1:
case R_ARM_LDC_SB_G1:
group = 1;
break;
case R_ARM_LDC_PC_G2:
case R_ARM_LDC_SB_G2:
group = 2;
break;
default:
abort();
}
/* If REL, extract the addend from the insn. If RELA, it will
have already been fetched for us. */
if (globals->use_rel)
{
int negative = (insn & (1 << 23)) ? 1 : -1;
signed_addend = negative * ((insn & 0xff) << 2);
}
/* Compute the value (X) to go in the place. */
if (r_type == R_ARM_LDC_PC_G0
|| r_type == R_ARM_LDC_PC_G1
|| r_type == R_ARM_LDC_PC_G2)
/* PC relative. */
signed_value = value - pc + signed_addend;
else
/* Section base relative. */
signed_value = value - sb + signed_addend;
/* Calculate the value of the relevant G_{n-1} to obtain
the residual at that stage. */
calculate_group_reloc_mask (abs (signed_value), group - 1, &residual);
/* Check for overflow. (The absolute value to go in the place must be
divisible by four and, after having been divided by four, must
fit in eight bits.) */
if ((residual & 0x3) != 0 || residual >= 0x400)
{
(*_bfd_error_handler)
(_("%B(%A+0x%lx): Overflow whilst splitting 0x%lx for group relocation %s"),
input_bfd, input_section,
(long) rel->r_offset, abs (signed_value), howto->name);
return bfd_reloc_overflow;
}
/* Mask out the value and U bit. */
insn &= 0xff7fff00;
/* Set the U bit if the value to go in the place is non-negative. */
if (signed_value >= 0)
insn |= 1 << 23;
/* Encode the offset. */
insn |= residual >> 2;
bfd_put_32 (input_bfd, insn, hit_data);
}
return bfd_reloc_ok;
default:
return bfd_reloc_notsupported;
}

28
bfd/libbfd.h
View file

@ -1231,6 +1231,34 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_ARM_TLS_TPOFF32",
"BFD_RELOC_ARM_TLS_IE32",
"BFD_RELOC_ARM_TLS_LE32",
"BFD_RELOC_ARM_ALU_PC_G0_NC",
"BFD_RELOC_ARM_ALU_PC_G0",
"BFD_RELOC_ARM_ALU_PC_G1_NC",
"BFD_RELOC_ARM_ALU_PC_G1",
"BFD_RELOC_ARM_ALU_PC_G2",
"BFD_RELOC_ARM_LDR_PC_G0",
"BFD_RELOC_ARM_LDR_PC_G1",
"BFD_RELOC_ARM_LDR_PC_G2",
"BFD_RELOC_ARM_LDRS_PC_G0",
"BFD_RELOC_ARM_LDRS_PC_G1",
"BFD_RELOC_ARM_LDRS_PC_G2",
"BFD_RELOC_ARM_LDC_PC_G0",
"BFD_RELOC_ARM_LDC_PC_G1",
"BFD_RELOC_ARM_LDC_PC_G2",
"BFD_RELOC_ARM_ALU_SB_G0_NC",
"BFD_RELOC_ARM_ALU_SB_G0",
"BFD_RELOC_ARM_ALU_SB_G1_NC",
"BFD_RELOC_ARM_ALU_SB_G1",
"BFD_RELOC_ARM_ALU_SB_G2",
"BFD_RELOC_ARM_LDR_SB_G0",
"BFD_RELOC_ARM_LDR_SB_G1",
"BFD_RELOC_ARM_LDR_SB_G2",
"BFD_RELOC_ARM_LDRS_SB_G0",
"BFD_RELOC_ARM_LDRS_SB_G1",
"BFD_RELOC_ARM_LDRS_SB_G2",
"BFD_RELOC_ARM_LDC_SB_G0",
"BFD_RELOC_ARM_LDC_SB_G1",
"BFD_RELOC_ARM_LDC_SB_G2",
"BFD_RELOC_ARM_IMMEDIATE",
"BFD_RELOC_ARM_ADRL_IMMEDIATE",
"BFD_RELOC_ARM_T32_IMMEDIATE",

59
bfd/reloc.c
View file

@ -2756,6 +2756,65 @@ ENUMX
ENUMDOC
ARM thread-local storage relocations.
ENUM
BFD_RELOC_ARM_ALU_PC_G0_NC
ENUMX
BFD_RELOC_ARM_ALU_PC_G0
ENUMX
BFD_RELOC_ARM_ALU_PC_G1_NC
ENUMX
BFD_RELOC_ARM_ALU_PC_G1
ENUMX
BFD_RELOC_ARM_ALU_PC_G2
ENUMX
BFD_RELOC_ARM_LDR_PC_G0
ENUMX
BFD_RELOC_ARM_LDR_PC_G1
ENUMX
BFD_RELOC_ARM_LDR_PC_G2
ENUMX
BFD_RELOC_ARM_LDRS_PC_G0
ENUMX
BFD_RELOC_ARM_LDRS_PC_G1
ENUMX
BFD_RELOC_ARM_LDRS_PC_G2
ENUMX
BFD_RELOC_ARM_LDC_PC_G0
ENUMX
BFD_RELOC_ARM_LDC_PC_G1
ENUMX
BFD_RELOC_ARM_LDC_PC_G2
ENUMX
BFD_RELOC_ARM_ALU_SB_G0_NC
ENUMX
BFD_RELOC_ARM_ALU_SB_G0
ENUMX
BFD_RELOC_ARM_ALU_SB_G1_NC
ENUMX
BFD_RELOC_ARM_ALU_SB_G1
ENUMX
BFD_RELOC_ARM_ALU_SB_G2
ENUMX
BFD_RELOC_ARM_LDR_SB_G0
ENUMX
BFD_RELOC_ARM_LDR_SB_G1
ENUMX
BFD_RELOC_ARM_LDR_SB_G2
ENUMX
BFD_RELOC_ARM_LDRS_SB_G0
ENUMX
BFD_RELOC_ARM_LDRS_SB_G1
ENUMX
BFD_RELOC_ARM_LDRS_SB_G2
ENUMX
BFD_RELOC_ARM_LDC_SB_G0
ENUMX
BFD_RELOC_ARM_LDC_SB_G1
ENUMX
BFD_RELOC_ARM_LDC_SB_G2
ENUMDOC
ARM group relocations.
ENUM
BFD_RELOC_ARM_IMMEDIATE
ENUMX

25
gas/ChangeLog
View file

@ -1,3 +1,28 @@
2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
* config/tc-arm.c (enum parse_operand_result): New.
(struct group_reloc_table_entry): New.
(enum group_reloc_type): New.
(group_reloc_table): New array.
(find_group_reloc_table_entry): New function.
(parse_shifter_operand_group_reloc): New function.
(parse_address_main): New function, incorporating code
from the old parse_address function. To be used via...
(parse_address): wrapper for parse_address_main; and
(parse_address_group_reloc): new function, likewise.
(enum operand_parse_code): New codes OP_SHG, OP_ADDRGLDR,
OP_ADDRGLDRS, OP_ADDRGLDC.
(parse_operands): Support for these new operand codes.
New macro po_misc_or_fail_no_backtrack.
(encode_arm_cp_address): Preserve group relocations.
(insns): Modify to use the above operand codes where group
relocations are permitted.
(md_apply_fix): Handle the group relocations
ALU_PC_G0_NC through LDC_SB_G2.
(tc_gen_reloc): Likewise.
(arm_force_relocation): Leave group relocations for the linker.
(arm_fix_adjustable): Likewise.
2006-06-15 Julian Brown <julian@codesourcery.com>
* config/tc-arm.c (do_vfp_nsyn_ldr_str): Remove, fold into...

614
gas/config/tc-arm.c
View file

@ -79,6 +79,15 @@ static struct
unsigned sp_restored:1;
} unwind;
/* Results from operand parsing worker functions. */
typedef enum
{
PARSE_OPERAND_SUCCESS,
PARSE_OPERAND_FAIL,
PARSE_OPERAND_FAIL_NO_BACKTRACK
} parse_operand_result;
/* Bit N indicates that an R_ARM_NONE relocation has been output for
__aeabi_unwind_cpp_prN already if set. This enables dependencies to be
emitted only once per section, to save unnecessary bloat. */
@ -4261,6 +4270,168 @@ parse_shifter_operand (char **str, int i)
return SUCCESS;
}
/* Group relocation information. Each entry in the table contains the
textual name of the relocation as may appear in assembler source
and must end with a colon.
Along with this textual name are the relocation codes to be used if
the corresponding instruction is an ALU instruction (ADD or SUB only),
an LDR, an LDRS, or an LDC. */
struct group_reloc_table_entry
{
const char *name;
int alu_code;
int ldr_code;
int ldrs_code;
int ldc_code;
};
typedef enum
{
/* Varieties of non-ALU group relocation. */
GROUP_LDR,
GROUP_LDRS,
GROUP_LDC
} group_reloc_type;
static struct group_reloc_table_entry group_reloc_table[] =
{ /* Program counter relative: */
{ "pc_g0_nc",
BFD_RELOC_ARM_ALU_PC_G0_NC, /* ALU */
0, /* LDR */
0, /* LDRS */
0 }, /* LDC */
{ "pc_g0",
BFD_RELOC_ARM_ALU_PC_G0, /* ALU */
BFD_RELOC_ARM_LDR_PC_G0, /* LDR */
BFD_RELOC_ARM_LDRS_PC_G0, /* LDRS */
BFD_RELOC_ARM_LDC_PC_G0 }, /* LDC */
{ "pc_g1_nc",
BFD_RELOC_ARM_ALU_PC_G1_NC, /* ALU */
0, /* LDR */
0, /* LDRS */
0 }, /* LDC */
{ "pc_g1",
BFD_RELOC_ARM_ALU_PC_G1, /* ALU */
BFD_RELOC_ARM_LDR_PC_G1, /* LDR */
BFD_RELOC_ARM_LDRS_PC_G1, /* LDRS */
BFD_RELOC_ARM_LDC_PC_G1 }, /* LDC */
{ "pc_g2",
BFD_RELOC_ARM_ALU_PC_G2, /* ALU */
BFD_RELOC_ARM_LDR_PC_G2, /* LDR */
BFD_RELOC_ARM_LDRS_PC_G2, /* LDRS */
BFD_RELOC_ARM_LDC_PC_G2 }, /* LDC */
/* Section base relative */
{ "sb_g0_nc",
BFD_RELOC_ARM_ALU_SB_G0_NC, /* ALU */
0, /* LDR */
0, /* LDRS */
0 }, /* LDC */
{ "sb_g0",
BFD_RELOC_ARM_ALU_SB_G0, /* ALU */
BFD_RELOC_ARM_LDR_SB_G0, /* LDR */
BFD_RELOC_ARM_LDRS_SB_G0, /* LDRS */
BFD_RELOC_ARM_LDC_SB_G0 }, /* LDC */
{ "sb_g1_nc",
BFD_RELOC_ARM_ALU_SB_G1_NC, /* ALU */
0, /* LDR */
0, /* LDRS */
0 }, /* LDC */
{ "sb_g1",
BFD_RELOC_ARM_ALU_SB_G1, /* ALU */
BFD_RELOC_ARM_LDR_SB_G1, /* LDR */
BFD_RELOC_ARM_LDRS_SB_G1, /* LDRS */
BFD_RELOC_ARM_LDC_SB_G1 }, /* LDC */
{ "sb_g2",
BFD_RELOC_ARM_ALU_SB_G2, /* ALU */
BFD_RELOC_ARM_LDR_SB_G2, /* LDR */
BFD_RELOC_ARM_LDRS_SB_G2, /* LDRS */
BFD_RELOC_ARM_LDC_SB_G2 } }; /* LDC */
/* Given the address of a pointer pointing to the textual name of a group
relocation as may appear in assembler source, attempt to find its details
in group_reloc_table. The pointer will be updated to the character after
the trailing colon. On failure, FAIL will be returned; SUCCESS
otherwise. On success, *entry will be updated to point at the relevant
group_reloc_table entry. */
static int
find_group_reloc_table_entry (char **str, struct group_reloc_table_entry **out)
{
unsigned int i;
for (i = 0; i < ARRAY_SIZE (group_reloc_table); i++)
{
int length = strlen (group_reloc_table[i].name);
if (strncasecmp (group_reloc_table[i].name, *str, length) == 0 &&
(*str)[length] == ':')
{
*out = &group_reloc_table[i];
*str += (length + 1);
return SUCCESS;
}
}
return FAIL;
}
/* Parse a <shifter_operand> for an ARM data processing instruction
(as for parse_shifter_operand) where group relocations are allowed:
#<immediate>
#<immediate>, <rotate>
#:<group_reloc>:<expression>
<Rm>
<Rm>, <shift>
where <group_reloc> is one of the strings defined in group_reloc_table.
The hashes are optional.
Everything else is as for parse_shifter_operand. */
static parse_operand_result
parse_shifter_operand_group_reloc (char **str, int i)
{
/* Determine if we have the sequence of characters #: or just :
coming next. If we do, then we check for a group relocation.
If we don't, punt the whole lot to parse_shifter_operand. */
if (((*str)[0] == '#' && (*str)[1] == ':')
|| (*str)[0] == ':')
{
struct group_reloc_table_entry *entry;
if ((*str)[0] == '#')
(*str) += 2;
else
(*str)++;
/* Try to parse a group relocation. Anything else is an error. */
if (find_group_reloc_table_entry (str, &entry) == FAIL)
{
inst.error = _("unknown group relocation");
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
}
/* We now have the group relocation table entry corresponding to
the name in the assembler source. Next, we parse the expression. */
if (my_get_expression (&inst.reloc.exp, str, GE_NO_PREFIX))
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
/* Record the relocation type (always the ALU variant here). */
inst.reloc.type = entry->alu_code;
assert (inst.reloc.type != 0);
return PARSE_OPERAND_SUCCESS;
}
else
return parse_shifter_operand (str, i) == SUCCESS
? PARSE_OPERAND_SUCCESS : PARSE_OPERAND_FAIL;
/* Never reached. */
}
/* Parse all forms of an ARM address expression. Information is written
to inst.operands[i] and/or inst.reloc.
@ -4293,8 +4464,9 @@ parse_shifter_operand (char **str, int i)
It is the caller's responsibility to check for addressing modes not
supported by the instruction, and to set inst.reloc.type. */
static int
parse_address (char **str, int i)
static parse_operand_result
parse_address_main (char **str, int i, int group_relocations,
group_reloc_type group_type)
{
char *p = *str;
int reg;
@ -4312,16 +4484,16 @@ parse_address (char **str, int i)
/* else a load-constant pseudo op, no special treatment needed here */
if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
return FAIL;
return PARSE_OPERAND_FAIL;
*str = p;
return SUCCESS;
return PARSE_OPERAND_SUCCESS;
}
if ((reg = arm_reg_parse (&p, REG_TYPE_RN)) == FAIL)
{
inst.error = _(reg_expected_msgs[REG_TYPE_RN]);
return FAIL;
return PARSE_OPERAND_FAIL;
}
inst.operands[i].reg = reg;
inst.operands[i].isreg = 1;
@ -4340,7 +4512,7 @@ parse_address (char **str, int i)
if (skip_past_comma (&p) == SUCCESS)
if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
return FAIL;
return PARSE_OPERAND_FAIL;
}
else if (skip_past_char (&p, ':') == SUCCESS)
{
@ -4352,7 +4524,7 @@ parse_address (char **str, int i)
if (exp.X_op != O_constant)
{
inst.error = _("alignment must be constant");
return FAIL;
return PARSE_OPERAND_FAIL;
}
inst.operands[i].imm = exp.X_add_number << 8;
inst.operands[i].immisalign = 1;
@ -4366,15 +4538,68 @@ parse_address (char **str, int i)
inst.operands[i].negative = 0;
p--;
}
if (group_relocations &&
((*p == '#' && *(p + 1) == ':') || *p == ':'))
{
struct group_reloc_table_entry *entry;
/* Skip over the #: or : sequence. */
if (*p == '#')
p += 2;
else
p++;
/* Try to parse a group relocation. Anything else is an
error. */
if (find_group_reloc_table_entry (&p, &entry) == FAIL)
{
inst.error = _("unknown group relocation");
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
}
/* We now have the group relocation table entry corresponding to
the name in the assembler source. Next, we parse the
expression. */
if (my_get_expression (&inst.reloc.exp, &p, GE_NO_PREFIX))
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
/* Record the relocation type. */
switch (group_type)
{
case GROUP_LDR:
inst.reloc.type = entry->ldr_code;
break;
case GROUP_LDRS:
inst.reloc.type = entry->ldrs_code;
break;
case GROUP_LDC:
inst.reloc.type = entry->ldc_code;
break;
default:
assert (0);
}
if (inst.reloc.type == 0)
{
inst.error = _("this group relocation is not allowed on this instruction");
return PARSE_OPERAND_FAIL_NO_BACKTRACK;
}
}
else
if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
return FAIL;
return PARSE_OPERAND_FAIL;
}
}
if (skip_past_char (&p, ']') == FAIL)
{
inst.error = _("']' expected");
return FAIL;
return PARSE_OPERAND_FAIL;
}
if (skip_past_char (&p, '!') == SUCCESS)
@ -4387,20 +4612,20 @@ parse_address (char **str, int i)
/* [Rn], {expr} - unindexed, with option */
if (parse_immediate (&p, &inst.operands[i].imm,
0, 255, TRUE) == FAIL)
return FAIL;
return PARSE_OPERAND_FAIL;
if (skip_past_char (&p, '}') == FAIL)
{
inst.error = _("'}' expected at end of 'option' field");
return FAIL;
return PARSE_OPERAND_FAIL;
}
if (inst.operands[i].preind)
{
inst.error = _("cannot combine index with option");
return FAIL;
return PARSE_OPERAND_FAIL;
}
*str = p;
return SUCCESS;
return PARSE_OPERAND_SUCCESS;
}
else
{
@ -4410,7 +4635,7 @@ parse_address (char **str, int i)
if (inst.operands[i].preind)
{
inst.error = _("cannot combine pre- and post-indexing");
return FAIL;
return PARSE_OPERAND_FAIL;
}
if (*p == '+') p++;
@ -4428,7 +4653,7 @@ parse_address (char **str, int i)
if (skip_past_comma (&p) == SUCCESS)
if (parse_shift (&p, i, SHIFT_IMMEDIATE) == FAIL)
return FAIL;
return PARSE_OPERAND_FAIL;
}
else
{
@ -4438,7 +4663,7 @@ parse_address (char **str, int i)
p--;
}
if (my_get_expression (&inst.reloc.exp, &p, GE_IMM_PREFIX))
return FAIL;
return PARSE_OPERAND_FAIL;
}
}
}
@ -4452,7 +4677,20 @@ parse_address (char **str, int i)
inst.reloc.exp.X_add_number = 0;
}
*str = p;
return SUCCESS;
return PARSE_OPERAND_SUCCESS;
}
static int
parse_address (char **str, int i)
{
return parse_address_main (str, i, 0, 0) == PARSE_OPERAND_SUCCESS
? SUCCESS : FAIL;
}
static parse_operand_result
parse_address_group_reloc (char **str, int i, group_reloc_type type)
{
return parse_address_main (str, i, 1, type);
}
/* Parse an operand for a MOVW or MOVT instruction. */
@ -5051,7 +5289,11 @@ enum operand_parse_code
OP_I31b, /* 0 .. 31 */
OP_SH, /* shifter operand */
OP_SHG, /* shifter operand with possible group relocation */
OP_ADDR, /* Memory address expression (any mode) */
OP_ADDRGLDR, /* Mem addr expr (any mode) with possible LDR group reloc */
OP_ADDRGLDRS, /* Mem addr expr (any mode) with possible LDRS group reloc */
OP_ADDRGLDC, /* Mem addr expr (any mode) with possible LDC group reloc */
OP_EXP, /* arbitrary expression */
OP_EXPi, /* same, with optional immediate prefix */
OP_EXPr, /* same, with optional relocation suffix */
@ -5106,6 +5348,7 @@ parse_operands (char *str, const unsigned char *pattern)
const char *backtrack_error = 0;
int i, val, backtrack_index = 0;
enum arm_reg_type rtype;
parse_operand_result result;
#define po_char_or_fail(chr) do { \
if (skip_past_char (&str, chr) == FAIL) \
@ -5163,6 +5406,14 @@ parse_operands (char *str, const unsigned char *pattern)
goto failure; \
} while (0)
#define po_misc_or_fail_no_backtrack(expr) do { \
result = expr; \
if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
backtrack_pos = 0; \
if (result != PARSE_OPERAND_SUCCESS) \
goto failure; \
} while (0)
skip_whitespace (str);
for (i = 0; upat[i] != OP_stop; i++)
@ -5545,10 +5796,30 @@ parse_operands (char *str, const unsigned char *pattern)
po_misc_or_fail (parse_address (&str, i));
break;
case OP_ADDRGLDR:
po_misc_or_fail_no_backtrack (
parse_address_group_reloc (&str, i, GROUP_LDR));
break;
case OP_ADDRGLDRS:
po_misc_or_fail_no_backtrack (
parse_address_group_reloc (&str, i, GROUP_LDRS));
break;
case OP_ADDRGLDC:
po_misc_or_fail_no_backtrack (
parse_address_group_reloc (&str, i, GROUP_LDC));
break;
case OP_SH:
po_misc_or_fail (parse_shifter_operand (&str, i));
break;
case OP_SHG:
po_misc_or_fail_no_backtrack (
parse_shifter_operand_group_reloc (&str, i));
break;
case OP_oSHll:
po_misc_or_fail (parse_shift (&str, i, SHIFT_LSL_IMMEDIATE));
break;
@ -5902,7 +6173,8 @@ encode_arm_addr_mode_3 (int i, bfd_boolean is_t)
into a coprocessor load/store instruction. If wb_ok is false,
reject use of writeback; if unind_ok is false, reject use of
unindexed addressing. If reloc_override is not 0, use it instead
of BFD_ARM_CP_OFF_IMM. */
of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
(in which case it is preserved). */
static int
encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
@ -5944,10 +6216,16 @@ encode_arm_cp_address (int i, int wb_ok, int unind_ok, int reloc_override)
if (reloc_override)
inst.reloc.type = reloc_override;
else if (thumb_mode)
else if ((inst.reloc.type < BFD_RELOC_ARM_ALU_PC_G0_NC
|| inst.reloc.type > BFD_RELOC_ARM_LDC_SB_G2)
&& inst.reloc.type != BFD_RELOC_ARM_LDR_PC_G0)
{
if (thumb_mode)
inst.reloc.type = BFD_RELOC_ARM_T32_CP_OFF_IMM;
else
inst.reloc.type = BFD_RELOC_ARM_CP_OFF_IMM;
}
return SUCCESS;
}
@ -14040,8 +14318,8 @@ static const struct asm_opcode insns[] =
tC3(eors, 0300000, eors, 3, (RR, oRR, SH), arit, t_arit3c),
tCE(sub, 0400000, sub, 3, (RR, oRR, SH), arit, t_add_sub),
tC3(subs, 0500000, subs, 3, (RR, oRR, SH), arit, t_add_sub),
tCE(add, 0800000, add, 3, (RR, oRR, SH), arit, t_add_sub),
tC3(adds, 0900000, adds, 3, (RR, oRR, SH), arit, t_add_sub),
tCE(add, 0800000, add, 3, (RR, oRR, SHG), arit, t_add_sub),
tC3(adds, 0900000, adds, 3, (RR, oRR, SHG), arit, t_add_sub),
tCE(adc, 0a00000, adc, 3, (RR, oRR, SH), arit, t_arit3c),
tC3(adcs, 0b00000, adcs, 3, (RR, oRR, SH), arit, t_arit3c),
tCE(sbc, 0c00000, sbc, 3, (RR, oRR, SH), arit, t_arit3),
@ -14069,10 +14347,10 @@ static const struct asm_opcode insns[] =
tCE(mvn, 1e00000, mvn, 2, (RR, SH), mov, t_mvn_tst),
tC3(mvns, 1f00000, mvns, 2, (RR, SH), mov, t_mvn_tst),
tCE(ldr, 4100000, ldr, 2, (RR, ADDR), ldst, t_ldst),
tC3(ldrb, 4500000, ldrb, 2, (RR, ADDR), ldst, t_ldst),
tCE(str, 4000000, str, 2, (RR, ADDR), ldst, t_ldst),
tC3(strb, 4400000, strb, 2, (RR, ADDR), ldst, t_ldst),
tCE(ldr, 4100000, ldr, 2, (RR, ADDRGLDR),ldst, t_ldst),
tC3(ldrb, 4500000, ldrb, 2, (RR, ADDRGLDR),ldst, t_ldst),
tCE(str, 4000000, str, 2, (RR, ADDRGLDR),ldst, t_ldst),
tC3(strb, 4400000, strb, 2, (RR, ADDRGLDR),ldst, t_ldst),
tCE(stm, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
tC3(stmia, 8800000, stmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
@ -14156,10 +14434,10 @@ static const struct asm_opcode insns[] =
/* Generic coprocessor instructions. */
TCE(cdp, e000000, ee000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDR), lstc, lstc),
TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDR), lstc, lstc),
TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDR), lstc, lstc),
TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDR), lstc, lstc),
TCE(ldc, c100000, ec100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TC3(ldcl, c500000, ec500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
@ -14188,12 +14466,12 @@ static const struct asm_opcode insns[] =
#define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
#undef THUMB_VARIANT
#define THUMB_VARIANT &arm_ext_v4t
tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDR), ldstv4, t_ldst),
tC3(strh, 00000b0, strh, 2, (RR, ADDR), ldstv4, t_ldst),
tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDR), ldstv4, t_ldst),
tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDR), ldstv4, t_ldst),
tC3(ldrh, 01000b0, ldrh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
tC3(strh, 00000b0, strh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
tC3(ldrsh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
tC3(ldrsb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
tCM(ld,sh, 01000f0, ldrsh, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
tCM(ld,sb, 01000d0, ldrsb, 2, (RR, ADDRGLDRS), ldstv4, t_ldst),
#undef ARM_VARIANT
#define ARM_VARIANT &arm_ext_v4t_5
@ -14214,10 +14492,10 @@ static const struct asm_opcode insns[] =
#undef THUMB_VARIANT
#define THUMB_VARIANT &arm_ext_v6t2
TCE(clz, 16f0f10, fab0f080, 2, (RRnpc, RRnpc), rd_rm, t_clz),
TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDR), lstc, lstc),
TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDR), lstc, lstc),
TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDR), lstc, lstc),
TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDR), lstc, lstc),
TUF(ldc2, c100000, fc100000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TUF(ldc2l, c500000, fc500000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TUF(stc2, c000000, fc000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
@ -14253,8 +14531,8 @@ static const struct asm_opcode insns[] =
#undef ARM_VARIANT
#define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
TUF(pld, 450f000, f810f000, 1, (ADDR), pld, t_pld),
TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDR), ldrd, t_ldstd),
TC3(ldrd, 00000d0, e9500000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
TC3(strd, 00000f0, e9400000, 3, (RRnpc, oRRnpc, ADDRGLDRS), ldrd, t_ldstd),
TCE(mcrr, c400000, ec400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
TCE(mrrc, c500000, ec500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c),
@ -14470,15 +14748,15 @@ static const struct asm_opcode insns[] =
cCE(wfc, e400110, 1, (RR), rd),
cCE(rfc, e500110, 1, (RR), rd),
cCL(ldfs, c100100, 2, (RF, ADDR), rd_cpaddr),
cCL(ldfd, c108100, 2, (RF, ADDR), rd_cpaddr),
cCL(ldfe, c500100, 2, (RF, ADDR), rd_cpaddr),
cCL(ldfp, c508100, 2, (RF, ADDR), rd_cpaddr),
cCL(ldfs, c100100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(ldfd, c108100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(ldfe, c500100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(ldfp, c508100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(stfs, c000100, 2, (RF, ADDR), rd_cpaddr),
cCL(stfd, c008100, 2, (RF, ADDR), rd_cpaddr),
cCL(stfe, c400100, 2, (RF, ADDR), rd_cpaddr),
cCL(stfp, c408100, 2, (RF, ADDR), rd_cpaddr),
cCL(stfs, c000100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(stfd, c008100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(stfe, c400100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(stfp, c408100, 2, (RF, ADDRGLDC), rd_cpaddr),
cCL(mvfs, e008100, 2, (RF, RF_IF), rd_rm),
cCL(mvfsp, e008120, 2, (RF, RF_IF), rd_rm),
@ -14921,8 +15199,8 @@ static const struct asm_opcode insns[] =
cCE(fmxr, ee00a10, 2, (RVC, RR), rn_rd),
/* Memory operations. */
cCE(flds, d100a00, 2, (RVS, ADDR), vfp_sp_ldst),
cCE(fsts, d000a00, 2, (RVS, ADDR), vfp_sp_ldst),
cCE(flds, d100a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
cCE(fsts, d000a00, 2, (RVS, ADDRGLDC), vfp_sp_ldst),
cCE(fldmias, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
cCE(fldmfds, c900a00, 2, (RRw, VRSLST), vfp_sp_ldstmia),
cCE(fldmdbs, d300a00, 2, (RRw, VRSLST), vfp_sp_ldstmdb),
@ -14980,8 +15258,8 @@ static const struct asm_opcode insns[] =
cCE(ftouizd, ebc0bc0, 2, (RVS, RVD), vfp_sp_dp_cvt),
/* Memory operations. */
cCE(fldd, d100b00, 2, (RVD, ADDR), vfp_dp_ldst),
cCE(fstd, d000b00, 2, (RVD, ADDR), vfp_dp_ldst),
cCE(fldd, d100b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
cCE(fstd, d000b00, 2, (RVD, ADDRGLDC), vfp_dp_ldst),
cCE(fldmiad, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
cCE(fldmfdd, c900b00, 2, (RRw, VRDLST), vfp_dp_ldstmia),
cCE(fldmdbd, d300b00, 2, (RRw, VRDLST), vfp_dp_ldstmdb),
@ -15055,8 +15333,8 @@ static const struct asm_opcode insns[] =
NCE(vstm, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
NCE(vstmia, c800b00, 2, (RRw, VRSDLST), neon_ldm_stm),
NCE(vstmdb, d000b00, 2, (RRw, VRSDLST), neon_ldm_stm),
NCE(vldr, d100b00, 2, (RVSD, ADDR), neon_ldr_str),
NCE(vstr, d000b00, 2, (RVSD, ADDR), neon_ldr_str),
NCE(vldr, d100b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
NCE(vstr, d000b00, 2, (RVSD, ADDRGLDC), neon_ldr_str),
nCEF(vcvt, vcvt, 3, (RNSDQ, RNSDQ, oI32b), neon_cvt),
@ -15512,14 +15790,14 @@ static const struct asm_opcode insns[] =
#undef ARM_VARIANT
#define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
cCE(cfldrs, c100400, 2, (RMF, ADDR), rd_cpaddr),
cCE(cfldrd, c500400, 2, (RMD, ADDR), rd_cpaddr),
cCE(cfldr32, c100500, 2, (RMFX, ADDR), rd_cpaddr),
cCE(cfldr64, c500500, 2, (RMDX, ADDR), rd_cpaddr),
cCE(cfstrs, c000400, 2, (RMF, ADDR), rd_cpaddr),
cCE(cfstrd, c400400, 2, (RMD, ADDR), rd_cpaddr),
cCE(cfstr32, c000500, 2, (RMFX, ADDR), rd_cpaddr),
cCE(cfstr64, c400500, 2, (RMDX, ADDR), rd_cpaddr),
cCE(cfldrs, c100400, 2, (RMF, ADDRGLDC), rd_cpaddr),
cCE(cfldrd, c500400, 2, (RMD, ADDRGLDC), rd_cpaddr),
cCE(cfldr32, c100500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
cCE(cfldr64, c500500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
cCE(cfstrs, c000400, 2, (RMF, ADDRGLDC), rd_cpaddr),
cCE(cfstrd, c400400, 2, (RMD, ADDRGLDC), rd_cpaddr),
cCE(cfstr32, c000500, 2, (RMFX, ADDRGLDC), rd_cpaddr),
cCE(cfstr64, c400500, 2, (RMDX, ADDRGLDC), rd_cpaddr),
cCE(cfmvsr, e000450, 2, (RMF, RR), rn_rd),
cCE(cfmvrs, e100450, 2, (RR, RMF), rd_rn),
cCE(cfmvdlr, e000410, 2, (RMD, RR), rn_rd),
@ -16918,6 +17196,7 @@ md_apply_fix (fixS * fixP,
assert (fixP->fx_r_type <= BFD_RELOC_UNUSED);
/* Note whether this will delete the relocation. */
if (fixP->fx_addsy == 0 && !fixP->fx_pcrel)
fixP->fx_done = 1;
@ -17793,6 +18072,175 @@ md_apply_fix (fixS * fixP,
}
return;
case BFD_RELOC_ARM_ALU_PC_G0_NC:
case BFD_RELOC_ARM_ALU_PC_G0:
case BFD_RELOC_ARM_ALU_PC_G1_NC:
case BFD_RELOC_ARM_ALU_PC_G1:
case BFD_RELOC_ARM_ALU_PC_G2:
case BFD_RELOC_ARM_ALU_SB_G0_NC:
case BFD_RELOC_ARM_ALU_SB_G0:
case BFD_RELOC_ARM_ALU_SB_G1_NC:
case BFD_RELOC_ARM_ALU_SB_G1:
case BFD_RELOC_ARM_ALU_SB_G2:
assert (!fixP->fx_done);
if (!seg->use_rela_p)
{
bfd_vma insn;
bfd_vma encoded_addend;
bfd_vma addend_abs = abs (value);
/* Check that the absolute value of the addend can be
expressed as an 8-bit constant plus a rotation. */
encoded_addend = encode_arm_immediate (addend_abs);
if (encoded_addend == (unsigned int) FAIL)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("the offset 0x%08lX is not representable"),
addend_abs);
/* Extract the instruction. */
insn = md_chars_to_number (buf, INSN_SIZE);
/* If the addend is positive, use an ADD instruction.
Otherwise use a SUB. Take care not to destroy the S bit. */
insn &= 0xff1fffff;
if (value < 0)
insn |= 1 << 22;
else
insn |= 1 << 23;
/* Place the encoded addend into the first 12 bits of the
instruction. */
insn &= 0xfffff000;
insn |= encoded_addend;
/* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
case BFD_RELOC_ARM_LDR_PC_G0:
case BFD_RELOC_ARM_LDR_PC_G1:
case BFD_RELOC_ARM_LDR_PC_G2:
case BFD_RELOC_ARM_LDR_SB_G0:
case BFD_RELOC_ARM_LDR_SB_G1:
case BFD_RELOC_ARM_LDR_SB_G2:
assert (!fixP->fx_done);
if (!seg->use_rela_p)
{
bfd_vma insn;
bfd_vma addend_abs = abs (value);
/* Check that the absolute value of the addend can be
encoded in 12 bits. */
if (addend_abs >= 0x1000)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
addend_abs);
/* Extract the instruction. */
insn = md_chars_to_number (buf, INSN_SIZE);
/* If the addend is negative, clear bit 23 of the instruction.
Otherwise set it. */
if (value < 0)
insn &= ~(1 << 23);
else
insn |= 1 << 23;
/* Place the absolute value of the addend into the first 12 bits
of the instruction. */
insn &= 0xfffff000;
insn |= addend_abs;
/* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
case BFD_RELOC_ARM_LDRS_PC_G0:
case BFD_RELOC_ARM_LDRS_PC_G1:
case BFD_RELOC_ARM_LDRS_PC_G2:
case BFD_RELOC_ARM_LDRS_SB_G0:
case BFD_RELOC_ARM_LDRS_SB_G1:
case BFD_RELOC_ARM_LDRS_SB_G2:
assert (!fixP->fx_done);
if (!seg->use_rela_p)
{
bfd_vma insn;
bfd_vma addend_abs = abs (value);
/* Check that the absolute value of the addend can be
encoded in 8 bits. */
if (addend_abs >= 0x100)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
addend_abs);
/* Extract the instruction. */
insn = md_chars_to_number (buf, INSN_SIZE);
/* If the addend is negative, clear bit 23 of the instruction.
Otherwise set it. */
if (value < 0)
insn &= ~(1 << 23);
else
insn |= 1 << 23;
/* Place the first four bits of the absolute value of the addend
into the first 4 bits of the instruction, and the remaining
four into bits 8 .. 11. */
insn &= 0xfffff0f0;
insn |= (addend_abs & 0xf) | ((addend_abs & 0xf0) << 4);
/* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
case BFD_RELOC_ARM_LDC_PC_G0:
case BFD_RELOC_ARM_LDC_PC_G1:
case BFD_RELOC_ARM_LDC_PC_G2:
case BFD_RELOC_ARM_LDC_SB_G0:
case BFD_RELOC_ARM_LDC_SB_G1:
case BFD_RELOC_ARM_LDC_SB_G2:
assert (!fixP->fx_done);
if (!seg->use_rela_p)
{
bfd_vma insn;
bfd_vma addend_abs = abs (value);
/* Check that the absolute value of the addend is a multiple of
four and, when divided by four, fits in 8 bits. */
if (addend_abs & 0x3)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("bad offset 0x%08lX (must be word-aligned)"),
addend_abs);
if ((addend_abs >> 2) > 0xff)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("bad offset 0x%08lX (must be an 8-bit number of words)"),
addend_abs);
/* Extract the instruction. */
insn = md_chars_to_number (buf, INSN_SIZE);
/* If the addend is negative, clear bit 23 of the instruction.
Otherwise set it. */
if (value < 0)
insn &= ~(1 << 23);
else
insn |= 1 << 23;
/* Place the addend (divided by four) into the first eight
bits of the instruction. */
insn &= 0xfffffff0;
insn |= addend_abs >> 2;
/* Update the instruction. */
md_number_to_chars (buf, insn, INSN_SIZE);
}
break;
case BFD_RELOC_UNUSED:
default:
as_bad_where (fixP->fx_file, fixP->fx_line,
@ -17912,6 +18360,34 @@ tc_gen_reloc (asection *section, fixS *fixp)
case BFD_RELOC_ARM_TLS_LDO32:
case BFD_RELOC_ARM_PCREL_CALL:
case BFD_RELOC_ARM_PCREL_JUMP:
case BFD_RELOC_ARM_ALU_PC_G0_NC:
case BFD_RELOC_ARM_ALU_PC_G0:
case BFD_RELOC_ARM_ALU_PC_G1_NC:
case BFD_RELOC_ARM_ALU_PC_G1:
case BFD_RELOC_ARM_ALU_PC_G2:
case BFD_RELOC_ARM_LDR_PC_G0:
case BFD_RELOC_ARM_LDR_PC_G1:
case BFD_RELOC_ARM_LDR_PC_G2:
case BFD_RELOC_ARM_LDRS_PC_G0:
case BFD_RELOC_ARM_LDRS_PC_G1:
case BFD_RELOC_ARM_LDRS_PC_G2:
case BFD_RELOC_ARM_LDC_PC_G0:
case BFD_RELOC_ARM_LDC_PC_G1:
case BFD_RELOC_ARM_LDC_PC_G2:
case BFD_RELOC_ARM_ALU_SB_G0_NC:
case BFD_RELOC_ARM_ALU_SB_G0:
case BFD_RELOC_ARM_ALU_SB_G1_NC:
case BFD_RELOC_ARM_ALU_SB_G1:
case BFD_RELOC_ARM_ALU_SB_G2:
case BFD_RELOC_ARM_LDR_SB_G0:
case BFD_RELOC_ARM_LDR_SB_G1:
case BFD_RELOC_ARM_LDR_SB_G2:
case BFD_RELOC_ARM_LDRS_SB_G0:
case BFD_RELOC_ARM_LDRS_SB_G1:
case BFD_RELOC_ARM_LDRS_SB_G2:
case BFD_RELOC_ARM_LDC_SB_G0:
case BFD_RELOC_ARM_LDC_SB_G1:
case BFD_RELOC_ARM_LDC_SB_G2:
code = fixp->fx_r_type;
break;
@ -18080,6 +18556,12 @@ arm_force_relocation (struct fix * fixp)
|| fixp->fx_r_type == BFD_RELOC_ARM_T32_ADD_PC12)
return 0;
/* Always leave these relocations for the linker. */
if ((fixp->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
&& fixp->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
|| fixp->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
return 1;
return generic_force_reloc (fixp);
}
@ -18157,6 +18639,12 @@ arm_fix_adjustable (fixS * fixP)
|| fixP->fx_r_type == BFD_RELOC_ARM_TARGET2)
return 0;
/* Similarly for group relocations. */
if ((fixP->fx_r_type >= BFD_RELOC_ARM_ALU_PC_G0_NC
&& fixP->fx_r_type <= BFD_RELOC_ARM_LDC_SB_G2)
|| fixP->fx_r_type == BFD_RELOC_ARM_LDR_PC_G0)
return 0;
return 1;
}

35
gas/testsuite/ChangeLog
View file

@ -1,3 +1,38 @@
2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
* gas/arm/group-reloc-alu.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.d: New test.
* gas/arm/group-reloc-alu-encoding-bad.l: New test.
* gas/arm/group-reloc-alu-encoding-bad.s: New test.
* gas/arm/group-reloc-alu-parsing-bad.d: New test.
* gas/arm/group-reloc-alu-parsing-bad.l: New test.
* gas/arm/group-reloc-alu-parsing-bad.s: New test.
* gas/arm/group-reloc-alu.s: New test.
* gas/arm/group-reloc-ldc.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.d: New test.
* gas/arm/group-reloc-ldc-encoding-bad.l: New test.
* gas/arm/group-reloc-ldc-encoding-bad.s: New test.
* gas/arm/group-reloc-ldc-parsing-bad.d: New test.
* gas/arm/group-reloc-ldc-parsing-bad.l: New test.
* gas/arm/group-reloc-ldc-parsing-bad.s: New test.
* gas/arm/group-reloc-ldc.s: New test.
* gas/arm/group-reloc-ldr.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.d: New test.
* gas/arm/group-reloc-ldr-encoding-bad.l: New test.
* gas/arm/group-reloc-ldr-encoding-bad.s: New test.
* gas/arm/group-reloc-ldr-parsing-bad.d: New test.
* gas/arm/group-reloc-ldr-parsing-bad.l: New test.
* gas/arm/group-reloc-ldr-parsing-bad.s: New test.
* gas/arm/group-reloc-ldr.s: New test.
* gas/arm/group-reloc-ldrs.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.d: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.l: New test.
* gas/arm/group-reloc-ldrs-encoding-bad.s: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.d: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.l: New test.
* gas/arm/group-reloc-ldrs-parsing-bad.s: New test.
* gas/arm/group-reloc-ldrs.s: New test.
2006-06-14 Thiemo Seufer <ths@mips.com>
Maciej W. Rozycki <macro@mips.com>

2
gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.d Normal file
View file

@ -0,0 +1,2 @@
#name: Group relocation tests, encoding failures (alu)
#error-output: group-reloc-alu-encoding-bad.l

81
gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.l Normal file
View file

@ -0,0 +1,81 @@
[^:]*: Assembler messages:
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:23: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:24: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:25: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:26: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:28: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:29: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:30: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable
[^:]*:31: Error: the offset 0x00011001 is not representable

35
gas/testsuite/gas/arm/group-reloc-alu-encoding-bad.s Normal file
View file

@ -0,0 +1,35 @@
@ Tests that should fail for ALU group relocations.
.text
.macro alutest insn sym offset
\insn r0, r0, #:pc_g0:(\sym + \offset)
\insn r0, r0, #:pc_g1:(\sym + \offset)
\insn r0, r0, #:pc_g2:(\sym + \offset)
\insn r0, r0, #:pc_g0_nc:(\sym + \offset)
\insn r0, r0, #:pc_g1_nc:(\sym + \offset)
\insn r0, r0, #:sb_g0:(\sym + \offset)
\insn r0, r0, #:sb_g1:(\sym + \offset)
\insn r0, r0, #:sb_g2:(\sym + \offset)
\insn r0, r0, #:sb_g0_nc:(\sym + \offset)
\insn r0, r0, #:sb_g1_nc:(\sym + \offset)
.endm
alutest add f 0x11001
alutest add localsym 0x11001
alutest adds f 0x11001
alutest adds localsym 0x11001
alutest add f "-0x11001"
alutest add localsym "-0x11001"
alutest adds f "-0x11001"
alutest adds localsym "-0x11001"
localsym:
mov r0, #0

2
gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.d Normal file
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@ -0,0 +1,2 @@
#name: Group relocation tests, parsing failures (alu)
#error-output: group-reloc-alu-parsing-bad.l

5
gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.l Normal file
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@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:6: Error: shift expression expected -- `sub r0,r0,#:pc_g0:\(foo\)'
[^:]*:7: Error: shift expression expected -- `subs r0,r0,#:pc_g0:\(foo\)'
[^:]*:10: Error: unknown group relocation -- `add r0,r0,#:pc_g2_nc:\(foo\)'
[^:]*:11: Error: unknown group relocation -- `add r0,r0,#:sb_g2_nc:\(foo\)'

12
gas/testsuite/gas/arm/group-reloc-alu-parsing-bad.s Normal file
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@ -0,0 +1,12 @@
@ Tests that should fail for ALU group relocations.
.text
@ Group relocs aren't allowed on SUB(S) instructions...
sub r0, r0, #:pc_g0:(foo)
subs r0, r0, #:pc_g0:(foo)
@ Some nonexistent relocations:
add r0, r0, #:pc_g2_nc:(foo)
add r0, r0, #:sb_g2_nc:(foo)

167
gas/testsuite/gas/arm/group-reloc-alu.d Normal file
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@ -0,0 +1,167 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: Group relocation tests (alu)
.*: +file format .*arm.*
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
0: R_ARM_ALU_PC_G0 f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
4: R_ARM_ALU_PC_G1 f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
8: R_ARM_ALU_PC_G2 f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
c: R_ARM_ALU_PC_G0_NC f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
10: R_ARM_ALU_PC_G1_NC f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
14: R_ARM_ALU_SB_G0 f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
18: R_ARM_ALU_SB_G1 f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
1c: R_ARM_ALU_SB_G2 f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
20: R_ARM_ALU_SB_G0_NC f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
24: R_ARM_ALU_SB_G1_NC f
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
28: R_ARM_ALU_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
2c: R_ARM_ALU_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
30: R_ARM_ALU_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
34: R_ARM_ALU_PC_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
38: R_ARM_ALU_PC_G1_NC localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
3c: R_ARM_ALU_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
40: R_ARM_ALU_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
44: R_ARM_ALU_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
48: R_ARM_ALU_SB_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2800c01 add r0, r0, #256 ; 0x100
4c: R_ARM_ALU_SB_G1_NC localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
50: R_ARM_ALU_PC_G0 f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
54: R_ARM_ALU_PC_G1 f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
58: R_ARM_ALU_PC_G2 f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
5c: R_ARM_ALU_PC_G0_NC f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
60: R_ARM_ALU_PC_G1_NC f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
64: R_ARM_ALU_SB_G0 f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
68: R_ARM_ALU_SB_G1 f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
6c: R_ARM_ALU_SB_G2 f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
70: R_ARM_ALU_SB_G0_NC f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
74: R_ARM_ALU_SB_G1_NC f
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
78: R_ARM_ALU_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
7c: R_ARM_ALU_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
80: R_ARM_ALU_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
84: R_ARM_ALU_PC_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
88: R_ARM_ALU_PC_G1_NC localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
8c: R_ARM_ALU_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
90: R_ARM_ALU_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
94: R_ARM_ALU_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
98: R_ARM_ALU_SB_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2900c01 adds r0, r0, #256 ; 0x100
9c: R_ARM_ALU_SB_G1_NC localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
a0: R_ARM_ALU_PC_G0 f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
a4: R_ARM_ALU_PC_G1 f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
a8: R_ARM_ALU_PC_G2 f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
ac: R_ARM_ALU_PC_G0_NC f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
b0: R_ARM_ALU_PC_G1_NC f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
b4: R_ARM_ALU_SB_G0 f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
b8: R_ARM_ALU_SB_G1 f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
bc: R_ARM_ALU_SB_G2 f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
c0: R_ARM_ALU_SB_G0_NC f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
c4: R_ARM_ALU_SB_G1_NC f
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
c8: R_ARM_ALU_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
cc: R_ARM_ALU_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
d0: R_ARM_ALU_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
d4: R_ARM_ALU_PC_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
d8: R_ARM_ALU_PC_G1_NC localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
dc: R_ARM_ALU_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
e0: R_ARM_ALU_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
e4: R_ARM_ALU_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
e8: R_ARM_ALU_SB_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2400c01 sub r0, r0, #256 ; 0x100
ec: R_ARM_ALU_SB_G1_NC localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
f0: R_ARM_ALU_PC_G0 f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
f4: R_ARM_ALU_PC_G1 f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
f8: R_ARM_ALU_PC_G2 f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
fc: R_ARM_ALU_PC_G0_NC f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
100: R_ARM_ALU_PC_G1_NC f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
104: R_ARM_ALU_SB_G0 f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
108: R_ARM_ALU_SB_G1 f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
10c: R_ARM_ALU_SB_G2 f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
110: R_ARM_ALU_SB_G0_NC f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
114: R_ARM_ALU_SB_G1_NC f
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
118: R_ARM_ALU_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
11c: R_ARM_ALU_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
120: R_ARM_ALU_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
124: R_ARM_ALU_PC_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
128: R_ARM_ALU_PC_G1_NC localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
12c: R_ARM_ALU_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
130: R_ARM_ALU_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
134: R_ARM_ALU_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
138: R_ARM_ALU_SB_G0_NC localsym
0[0-9a-f]+ <[^>]+> e2500c01 subs r0, r0, #256 ; 0x100
13c: R_ARM_ALU_SB_G1_NC localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0

39
gas/testsuite/gas/arm/group-reloc-alu.s Normal file
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@ -0,0 +1,39 @@
@ Tests for ALU group relocations.
.text
.macro alutest insn sym offset
\insn r0, r0, #:pc_g0:(\sym \offset)
\insn r0, r0, #:pc_g1:(\sym \offset)
@ Try this one without the hash; it should still work.
\insn r0, r0, :pc_g2:(\sym \offset)
\insn r0, r0, #:pc_g0_nc:(\sym \offset)
\insn r0, r0, #:pc_g1_nc:(\sym \offset)
\insn r0, r0, #:sb_g0:(\sym \offset)
\insn r0, r0, #:sb_g1:(\sym \offset)
\insn r0, r0, #:sb_g2:(\sym \offset)
\insn r0, r0, #:sb_g0_nc:(\sym \offset)
\insn r0, r0, #:sb_g1_nc:(\sym \offset)
.endm
alutest add f "+ 0x100"
alutest add localsym "+ 0x100"
alutest adds f "+ 0x100"
alutest adds localsym "+ 0x100"
@ The following should cause the insns to be switched to SUB(S).
alutest add f "- 0x100"
alutest add localsym "- 0x100"
alutest adds f "- 0x100"
alutest adds localsym "- 0x100"
localsym:
mov r0, #0

2
gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.d Normal file
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@ -0,0 +1,2 @@
#name: Group relocation tests, encoding failures (ldc)
#error-output: group-reloc-ldc-encoding-bad.l

721
gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.l Normal file
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@ -0,0 +1,721 @@
[^:]*: Assembler messages:
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:43: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:44: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:45: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:46: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:48: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:49: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:50: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:51: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:93: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:94: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:95: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:96: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:98: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:99: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:100: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:101: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:143: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:144: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:148: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:149: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:153: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:154: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:160: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:161: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:162: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:163: Error: bad offset 0x00000001 \(must be word-aligned\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:165: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:166: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:167: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)
[^:]*:168: Error: bad offset 0x00000808 \(must be an 8-bit number of words\)

169
gas/testsuite/gas/arm/group-reloc-ldc-encoding-bad.s Normal file
View file

@ -0,0 +1,169 @@
@ LDC group relocation tests that are supposed to fail during encoding.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store cst
\load 0, c0, [r0, #:pc_g0:(f + \cst)]
\load 0, c0, [r0, #:pc_g1:(f + \cst)]
\load 0, c0, [r0, #:pc_g2:(f + \cst)]
\load 0, c0, [r0, #:sb_g0:(f + \cst)]
\load 0, c0, [r0, #:sb_g1:(f + \cst)]
\load 0, c0, [r0, #:sb_g2:(f + \cst)]
\store 0, c0, [r0, #:pc_g0:(f + \cst)]
\store 0, c0, [r0, #:pc_g1:(f + \cst)]
\store 0, c0, [r0, #:pc_g2:(f + \cst)]
\store 0, c0, [r0, #:sb_g0:(f + \cst)]
\store 0, c0, [r0, #:sb_g1:(f + \cst)]
\store 0, c0, [r0, #:sb_g2:(f + \cst)]
\load 0, c0, [r0, #:pc_g0:(f - \cst)]
\load 0, c0, [r0, #:pc_g1:(f - \cst)]
\load 0, c0, [r0, #:pc_g2:(f - \cst)]
\load 0, c0, [r0, #:sb_g0:(f - \cst)]
\load 0, c0, [r0, #:sb_g1:(f - \cst)]
\load 0, c0, [r0, #:sb_g2:(f - \cst)]
\store 0, c0, [r0, #:pc_g0:(f - \cst)]
\store 0, c0, [r0, #:pc_g1:(f - \cst)]
\store 0, c0, [r0, #:pc_g2:(f - \cst)]
\store 0, c0, [r0, #:sb_g0:(f - \cst)]
\store 0, c0, [r0, #:sb_g1:(f - \cst)]
\store 0, c0, [r0, #:sb_g2:(f - \cst)]
.endm
ldctest ldc stc 0x1
ldctest ldcl stcl 0x1
ldctest ldc2 stc2 0x1
ldctest ldc2l stc2l 0x1
ldctest ldc stc 0x808
ldctest ldcl stcl 0x808
ldctest ldc2 stc2 0x808
ldctest ldc2l stc2l 0x808
@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
.fpu fpa
.macro fpa_test load store cst
\load f0, [r0, #:pc_g0:(f + \cst)]
\load f0, [r0, #:pc_g1:(f + \cst)]
\load f0, [r0, #:pc_g2:(f + \cst)]
\load f0, [r0, #:sb_g0:(f + \cst)]
\load f0, [r0, #:sb_g1:(f + \cst)]
\load f0, [r0, #:sb_g2:(f + \cst)]
\store f0, [r0, #:pc_g0:(f + \cst)]
\store f0, [r0, #:pc_g1:(f + \cst)]
\store f0, [r0, #:pc_g2:(f + \cst)]
\store f0, [r0, #:sb_g0:(f + \cst)]
\store f0, [r0, #:sb_g1:(f + \cst)]
\store f0, [r0, #:sb_g2:(f + \cst)]
\load f0, [r0, #:pc_g0:(f - \cst)]
\load f0, [r0, #:pc_g1:(f - \cst)]
\load f0, [r0, #:pc_g2:(f - \cst)]
\load f0, [r0, #:sb_g0:(f - \cst)]
\load f0, [r0, #:sb_g1:(f - \cst)]
\load f0, [r0, #:sb_g2:(f - \cst)]
\store f0, [r0, #:pc_g0:(f - \cst)]
\store f0, [r0, #:pc_g1:(f - \cst)]
\store f0, [r0, #:pc_g2:(f - \cst)]
\store f0, [r0, #:sb_g0:(f - \cst)]
\store f0, [r0, #:sb_g1:(f - \cst)]
\store f0, [r0, #:sb_g2:(f - \cst)]
.endm
fpa_test ldfs stfs 0x1
fpa_test ldfd stfd 0x1
fpa_test ldfe stfe 0x1
fpa_test ldfp stfp 0x1
fpa_test ldfs stfs 0x808
fpa_test ldfd stfd 0x808
fpa_test ldfe stfe 0x808
fpa_test ldfp stfp 0x808
@ FLDS/FSTS
.fpu vfp
.macro vfp_test load store reg cst
\load \reg, [r0, #:pc_g0:(f + \cst)]
\load \reg, [r0, #:pc_g1:(f + \cst)]
\load \reg, [r0, #:pc_g2:(f + \cst)]
\load \reg, [r0, #:sb_g0:(f + \cst)]
\load \reg, [r0, #:sb_g1:(f + \cst)]
\load \reg, [r0, #:sb_g2:(f + \cst)]
\store \reg, [r0, #:pc_g0:(f + \cst)]
\store \reg, [r0, #:pc_g1:(f + \cst)]
\store \reg, [r0, #:pc_g2:(f + \cst)]
\store \reg, [r0, #:sb_g0:(f + \cst)]
\store \reg, [r0, #:sb_g1:(f + \cst)]
\store \reg, [r0, #:sb_g2:(f + \cst)]
\load \reg, [r0, #:pc_g0:(f - \cst)]
\load \reg, [r0, #:pc_g1:(f - \cst)]
\load \reg, [r0, #:pc_g2:(f - \cst)]
\load \reg, [r0, #:sb_g0:(f - \cst)]
\load \reg, [r0, #:sb_g1:(f - \cst)]
\load \reg, [r0, #:sb_g2:(f - \cst)]
\store \reg, [r0, #:pc_g0:(f - \cst)]
\store \reg, [r0, #:pc_g1:(f - \cst)]
\store \reg, [r0, #:pc_g2:(f - \cst)]
\store \reg, [r0, #:sb_g0:(f - \cst)]
\store \reg, [r0, #:sb_g1:(f - \cst)]
\store \reg, [r0, #:sb_g2:(f - \cst)]
.endm
vfp_test flds fsts s0 0x1
vfp_test flds fsts s0 0x808
@ FLDD/FSTD
vfp_test fldd fstd d0 0x1
vfp_test fldd fstd d0 0x808
@ VLDR/VSTR
vfp_test vldr vstr d0 0x1
vfp_test vldr vstr d0 0x808
@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
.cpu ep9312
vfp_test cfldrs cfstrs mvf0 0x1
vfp_test cfldrd cfstrd mvd0 0x1
vfp_test cfldr32 cfstr32 mvfx0 0x1
vfp_test cfldr64 cfstr64 mvdx0 0x1
vfp_test cfldrs cfstrs mvf0 0x808
vfp_test cfldrd cfstrd mvd0 0x808
vfp_test cfldr32 cfstr32 mvfx0 0x808
vfp_test cfldr64 cfstr64 mvdx0 0x808

2
gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.d Normal file
View file

@ -0,0 +1,2 @@
#name: Group relocation tests, parsing failures (ldc)
#error-output: group-reloc-ldc-parsing-bad.l

147
gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.l Normal file
View file

@ -0,0 +1,147 @@
[^:]*: Assembler messages:
[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:25: Error: this group relocation is not allowed on this instruction -- `ldc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:25: Error: unknown group relocation -- `ldc 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:26: Error: this group relocation is not allowed on this instruction -- `ldcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:26: Error: unknown group relocation -- `ldcl 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:27: Error: unknown group relocation -- `ldc2 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:28: Error: unknown group relocation -- `ldc2l 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:30: Error: this group relocation is not allowed on this instruction -- `stc 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:30: Error: unknown group relocation -- `stc 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:31: Error: this group relocation is not allowed on this instruction -- `stcl 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:31: Error: unknown group relocation -- `stcl 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:32: Error: this group relocation is not allowed on this instruction -- `stc2 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:32: Error: unknown group relocation -- `stc2 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:33: Error: this group relocation is not allowed on this instruction -- `stc2l 0,c0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:33: Error: unknown group relocation -- `stc2l 0,c0,\[r0,#:foo:\(sym\)\]'
[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:37: Error: this group relocation is not allowed on this instruction -- `ldfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:37: Error: unknown group relocation -- `ldfs f0,\[r0,#:foo:\(sym\)\]'
[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:38: Error: this group relocation is not allowed on this instruction -- `stfs f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:38: Error: unknown group relocation -- `stfs f0,\[r0,#:foo:\(sym\)\]'
[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:39: Error: this group relocation is not allowed on this instruction -- `ldfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:39: Error: unknown group relocation -- `ldfd f0,\[r0,#:foo:\(sym\)\]'
[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:40: Error: this group relocation is not allowed on this instruction -- `stfd f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:40: Error: unknown group relocation -- `stfd f0,\[r0,#:foo:\(sym\)\]'
[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:41: Error: this group relocation is not allowed on this instruction -- `ldfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:41: Error: unknown group relocation -- `ldfe f0,\[r0,#:foo:\(sym\)\]'
[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:42: Error: this group relocation is not allowed on this instruction -- `stfe f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:42: Error: unknown group relocation -- `stfe f0,\[r0,#:foo:\(sym\)\]'
[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:43: Error: this group relocation is not allowed on this instruction -- `ldfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:43: Error: unknown group relocation -- `ldfp f0,\[r0,#:foo:\(sym\)\]'
[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:44: Error: this group relocation is not allowed on this instruction -- `stfp f0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:44: Error: unknown group relocation -- `stfp f0,\[r0,#:foo:\(sym\)\]'
[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:48: Error: this group relocation is not allowed on this instruction -- `flds s0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:48: Error: unknown group relocation -- `flds s0,\[r0,#:foo:\(sym\)\]'
[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:49: Error: this group relocation is not allowed on this instruction -- `fsts s0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:49: Error: unknown group relocation -- `fsts s0,\[r0,#:foo:\(sym\)\]'
[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:51: Error: this group relocation is not allowed on this instruction -- `fldd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:51: Error: unknown group relocation -- `fldd d0,\[r0,#:foo:\(sym\)\]'
[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:52: Error: this group relocation is not allowed on this instruction -- `fstd d0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:52: Error: unknown group relocation -- `fstd d0,\[r0,#:foo:\(sym\)\]'
[^:]*:54: Error: too many positional arguments
[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:55: Error: this group relocation is not allowed on this instruction -- `vstr d0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:55: Error: unknown group relocation -- `vstr d0,\[r0,#:foo:\(sym\)\]'
[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:59: Error: this group relocation is not allowed on this instruction -- `cfldrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:59: Error: unknown group relocation -- `cfldrs mvf0,\[r0,#:foo:\(sym\)\]'
[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:60: Error: this group relocation is not allowed on this instruction -- `cfstrs mvf0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:60: Error: unknown group relocation -- `cfstrs mvf0,\[r0,#:foo:\(sym\)\]'
[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:61: Error: this group relocation is not allowed on this instruction -- `cfldrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:61: Error: unknown group relocation -- `cfldrd mvd0,\[r0,#:foo:\(sym\)\]'
[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:62: Error: this group relocation is not allowed on this instruction -- `cfstrd mvd0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:62: Error: unknown group relocation -- `cfstrd mvd0,\[r0,#:foo:\(sym\)\]'
[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:63: Error: this group relocation is not allowed on this instruction -- `cfldr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:63: Error: unknown group relocation -- `cfldr32 mvfx0,\[r0,#:foo:\(sym\)\]'
[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:64: Error: this group relocation is not allowed on this instruction -- `cfstr32 mvfx0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:64: Error: unknown group relocation -- `cfstr32 mvfx0,\[r0,#:foo:\(sym\)\]'
[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:65: Error: this group relocation is not allowed on this instruction -- `cfldr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:65: Error: unknown group relocation -- `cfldr64 mvdx0,\[r0,#:foo:\(sym\)\]'
[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g0_nc:\(sym\)\]'
[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:pc_g1_nc:\(sym\)\]'
[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g0_nc:\(sym\)\]'
[^:]*:66: Error: this group relocation is not allowed on this instruction -- `cfstr64 mvdx0,\[r0,#:sb_g1_nc:\(sym\)\]'
[^:]*:66: Error: unknown group relocation -- `cfstr64 mvdx0,\[r0,#:foo:\(sym\)\]'

67
gas/testsuite/gas/arm/group-reloc-ldc-parsing-bad.s Normal file
View file

@ -0,0 +1,67 @@
@ Tests for LDC group relocations that are meant to fail during parsing.
.macro ldctest insn reg
\insn 0, \reg, [r0, #:pc_g0_nc:(sym)]
\insn 0, \reg, [r0, #:pc_g1_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g0_nc:(sym)]
\insn 0, \reg, [r0, #:sb_g1_nc:(sym)]
\insn 0, \reg, [r0, #:foo:(sym)]
.endm
.macro ldctest2 insn reg
\insn \reg, [r0, #:pc_g0_nc:(sym)]
\insn \reg, [r0, #:pc_g1_nc:(sym)]
\insn \reg, [r0, #:sb_g0_nc:(sym)]
\insn \reg, [r0, #:sb_g1_nc:(sym)]
\insn \reg, [r0, #:foo:(sym)]
.endm
ldctest ldc c0
ldctest ldcl c0
ldctest ldc2 c0
ldctest ldc2l c0
ldctest stc c0
ldctest stcl c0
ldctest stc2 c0
ldctest stc2l c0
.fpu fpa
ldctest2 ldfs f0
ldctest2 stfs f0
ldctest2 ldfd f0
ldctest2 stfd f0
ldctest2 ldfe f0
ldctest2 stfe f0
ldctest2 ldfp f0
ldctest2 stfp f0
.fpu vfp
ldctest2 flds s0
ldctest2 fsts s0
ldctest2 fldd d0
ldctest2 fstd d0
ldctest2 vldr d0 FIXME
ldctest2 vstr d0
.cpu ep9312
ldctest2 cfldrs mvf0
ldctest2 cfstrs mvf0
ldctest2 cfldrd mvd0
ldctest2 cfstrd mvd0
ldctest2 cfldr32 mvfx0
ldctest2 cfstr32 mvfx0
ldctest2 cfldr64 mvdx0
ldctest2 cfstr64 mvdx0

726
gas/testsuite/gas/arm/group-reloc-ldc.d Normal file
View file

@ -0,0 +1,726 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: Group relocation tests (ldc)
.*: +file format .*arm.*
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\]
0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\]
4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\]
8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\]
c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\]
10: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed900085 ldc 0, cr0, \[r0, #532\]
14: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\]
18: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\]
1c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\]
20: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\]
24: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\]
28: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed800085 stc 0, cr0, \[r0, #532\]
2c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\]
30: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\]
34: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\]
38: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\]
3c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\]
40: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed100085 ldc 0, cr0, \[r0, #-532\]
44: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\]
48: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\]
4c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\]
50: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\]
54: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\]
58: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000085 stc 0, cr0, \[r0, #-532\]
5c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\]
60: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\]
64: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\]
68: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\]
6c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\]
70: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edd00085 ldcl 0, cr0, \[r0, #532\]
74: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\]
78: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\]
7c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\]
80: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\]
84: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\]
88: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edc00085 stcl 0, cr0, \[r0, #532\]
8c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\]
90: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\]
94: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\]
98: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\]
9c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\]
a0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed500085 ldcl 0, cr0, \[r0, #-532\]
a4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\]
a8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\]
ac: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\]
b0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\]
b4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\]
b8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed400085 stcl 0, cr0, \[r0, #-532\]
bc: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\]
c0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\]
c4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\]
c8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\]
cc: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\]
d0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fd900085 ldc2 0, cr0, \[r0, #532\]
d4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\]
d8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\]
dc: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\]
e0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\]
e4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\]
e8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fd800085 stc2 0, cr0, \[r0, #532\]
ec: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\]
f0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\]
f4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\]
f8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\]
fc: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\]
100: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fd100085 ldc2 0, cr0, \[r0, #-532\]
104: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\]
108: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\]
10c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\]
110: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\]
114: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\]
118: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fd000085 stc2 0, cr0, \[r0, #-532\]
11c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\]
120: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\]
124: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\]
128: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\]
12c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\]
130: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fdd00085 ldc2l 0, cr0, \[r0, #532\]
134: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\]
138: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\]
13c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\]
140: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\]
144: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\]
148: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fdc00085 stc2l 0, cr0, \[r0, #532\]
14c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\]
150: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\]
154: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\]
158: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\]
15c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\]
160: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fd500085 ldc2l 0, cr0, \[r0, #-532\]
164: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\]
168: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\]
16c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\]
170: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\]
174: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\]
178: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> fd400085 stc2l 0, cr0, \[r0, #-532\]
17c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\]
180: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\]
184: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\]
188: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\]
18c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\]
190: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed900185 ldfs f0, \[r0, #532\]
194: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\]
198: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\]
19c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\]
1a0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\]
1a4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\]
1a8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed800185 stfs f0, \[r0, #532\]
1ac: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\]
1b0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\]
1b4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\]
1b8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\]
1bc: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\]
1c0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed100185 ldfs f0, \[r0, #-532\]
1c4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\]
1c8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\]
1cc: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\]
1d0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\]
1d4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\]
1d8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000185 stfs f0, \[r0, #-532\]
1dc: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\]
1e0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\]
1e4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\]
1e8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\]
1ec: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\]
1f0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed908185 ldfd f0, \[r0, #532\]
1f4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\]
1f8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\]
1fc: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\]
200: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\]
204: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\]
208: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed808185 stfd f0, \[r0, #532\]
20c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\]
210: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\]
214: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\]
218: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\]
21c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\]
220: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed108185 ldfd f0, \[r0, #-532\]
224: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\]
228: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\]
22c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\]
230: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\]
234: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\]
238: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed008185 stfd f0, \[r0, #-532\]
23c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\]
240: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\]
244: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\]
248: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\]
24c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\]
250: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edd00185 ldfe f0, \[r0, #532\]
254: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\]
258: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\]
25c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\]
260: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\]
264: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\]
268: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edc00185 stfe f0, \[r0, #532\]
26c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\]
270: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\]
274: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\]
278: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\]
27c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\]
280: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed500185 ldfe f0, \[r0, #-532\]
284: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\]
288: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\]
28c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\]
290: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\]
294: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\]
298: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed400185 stfe f0, \[r0, #-532\]
29c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\]
2a0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\]
2a4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\]
2a8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\]
2ac: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\]
2b0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edd08185 ldfp f0, \[r0, #532\]
2b4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\]
2b8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\]
2bc: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\]
2c0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\]
2c4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\]
2c8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edc08185 stfp f0, \[r0, #532\]
2cc: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\]
2d0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\]
2d4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\]
2d8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\]
2dc: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\]
2e0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed508185 ldfp f0, \[r0, #-532\]
2e4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\]
2e8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\]
2ec: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\]
2f0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\]
2f4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\]
2f8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed408185 stfp f0, \[r0, #-532\]
2fc: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\]
300: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\]
304: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\]
308: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\]
30c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\]
310: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed900a85 flds s0, \[r0, #532\]
314: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\]
318: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\]
31c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\]
320: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\]
324: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\]
328: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed800a85 fsts s0, \[r0, #532\]
32c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\]
330: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\]
334: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\]
338: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\]
33c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\]
340: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed100a85 flds s0, \[r0, #-532\]
344: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\]
348: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\]
34c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\]
350: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\]
354: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\]
358: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000a85 fsts s0, \[r0, #-532\]
35c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
360: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
364: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
368: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
36c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
370: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
374: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
378: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
37c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
380: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
384: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
388: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
38c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
390: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
394: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
398: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
39c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
3a0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
3a4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
3a8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
3ac: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
3b0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
3b4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
3b8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
3bc: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
3c0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
3c4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
3c8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
3cc: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
3d0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed900b85 vldr d0, \[r0, #532\]
3d4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
3d8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
3dc: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
3e0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
3e4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
3e8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed800b85 vstr d0, \[r0, #532\]
3ec: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
3f0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
3f4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
3f8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
3fc: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
400: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed100b85 vldr d0, \[r0, #-532\]
404: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
408: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
40c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
410: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
414: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
418: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000b85 vstr d0, \[r0, #-532\]
41c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\]
420: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\]
424: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\]
428: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\]
42c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\]
430: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed900485 cfldrs mvf0, \[r0, #532\]
434: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\]
438: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\]
43c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\]
440: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\]
444: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\]
448: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed800485 cfstrs mvf0, \[r0, #532\]
44c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\]
450: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\]
454: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\]
458: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\]
45c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\]
460: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed100485 cfldrs mvf0, \[r0, #-532\]
464: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\]
468: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\]
46c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\]
470: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\]
474: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\]
478: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000485 cfstrs mvf0, \[r0, #-532\]
47c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\]
480: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\]
484: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\]
488: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\]
48c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\]
490: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edd00485 cfldrd mvd0, \[r0, #532\]
494: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\]
498: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\]
49c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\]
4a0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\]
4a4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\]
4a8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edc00485 cfstrd mvd0, \[r0, #532\]
4ac: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\]
4b0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\]
4b4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\]
4b8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\]
4bc: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\]
4c0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed500485 cfldrd mvd0, \[r0, #-532\]
4c4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\]
4c8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\]
4cc: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\]
4d0: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\]
4d4: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\]
4d8: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed400485 cfstrd mvd0, \[r0, #-532\]
4dc: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\]
4e0: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\]
4e4: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\]
4e8: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\]
4ec: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\]
4f0: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed900585 cfldr32 mvfx0, \[r0, #532\]
4f4: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\]
4f8: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\]
4fc: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\]
500: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\]
504: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\]
508: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed800585 cfstr32 mvfx0, \[r0, #532\]
50c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\]
510: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\]
514: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\]
518: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\]
51c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\]
520: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed100585 cfldr32 mvfx0, \[r0, #-532\]
524: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\]
528: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\]
52c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\]
530: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\]
534: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\]
538: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed000585 cfstr32 mvfx0, \[r0, #-532\]
53c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\]
540: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\]
544: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\]
548: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\]
54c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\]
550: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edd00585 cfldr64 mvdx0, \[r0, #532\]
554: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\]
558: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\]
55c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\]
560: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\]
564: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\]
568: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> edc00585 cfstr64 mvdx0, \[r0, #532\]
56c: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\]
570: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\]
574: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\]
578: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\]
57c: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\]
580: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed500585 cfldr64 mvdx0, \[r0, #-532\]
584: R_ARM_LDC_SB_G2 f
0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\]
588: R_ARM_LDC_PC_G0 f
0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\]
58c: R_ARM_LDC_PC_G1 f
0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\]
590: R_ARM_LDC_PC_G2 f
0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\]
594: R_ARM_LDC_SB_G0 f
0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\]
598: R_ARM_LDC_SB_G1 f
0[0-9a-f]+ <[^>]+> ed400585 cfstr64 mvdx0, \[r0, #-532\]
59c: R_ARM_LDC_SB_G2 f

151
gas/testsuite/gas/arm/group-reloc-ldc.s Normal file
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@ LDC group relocation tests.
.text
@ LDC/LDCL/LDC2/LDC2L/STC/STCL/STC2/STC2L
.macro ldctest load store
\load 0, c0, [r0, #:pc_g0:(f + 0x214)]
\load 0, c0, [r0, #:pc_g1:(f + 0x214)]
\load 0, c0, [r0, #:pc_g2:(f + 0x214)]
\load 0, c0, [r0, #:sb_g0:(f + 0x214)]
\load 0, c0, [r0, #:sb_g1:(f + 0x214)]
\load 0, c0, [r0, #:sb_g2:(f + 0x214)]
\store 0, c0, [r0, #:pc_g0:(f + 0x214)]
\store 0, c0, [r0, #:pc_g1:(f + 0x214)]
\store 0, c0, [r0, #:pc_g2:(f + 0x214)]
\store 0, c0, [r0, #:sb_g0:(f + 0x214)]
\store 0, c0, [r0, #:sb_g1:(f + 0x214)]
\store 0, c0, [r0, #:sb_g2:(f + 0x214)]
\load 0, c0, [r0, #:pc_g0:(f - 0x214)]
\load 0, c0, [r0, #:pc_g1:(f - 0x214)]
\load 0, c0, [r0, #:pc_g2:(f - 0x214)]
\load 0, c0, [r0, #:sb_g0:(f - 0x214)]
\load 0, c0, [r0, #:sb_g1:(f - 0x214)]
\load 0, c0, [r0, #:sb_g2:(f - 0x214)]
\store 0, c0, [r0, #:pc_g0:(f - 0x214)]
\store 0, c0, [r0, #:pc_g1:(f - 0x214)]
\store 0, c0, [r0, #:pc_g2:(f - 0x214)]
\store 0, c0, [r0, #:sb_g0:(f - 0x214)]
\store 0, c0, [r0, #:sb_g1:(f - 0x214)]
\store 0, c0, [r0, #:sb_g2:(f - 0x214)]
.endm
ldctest ldc stc
ldctest ldcl stcl
ldctest ldc2 stc2
ldctest ldc2l stc2l
@ LDFS/STFS/LDFD/STFD/LDFE/STFE/LDFP/STFP
.fpu fpa
.macro fpa_test load store
\load f0, [r0, #:pc_g0:(f + 0x214)]
\load f0, [r0, #:pc_g1:(f + 0x214)]
\load f0, [r0, #:pc_g2:(f + 0x214)]
\load f0, [r0, #:sb_g0:(f + 0x214)]
\load f0, [r0, #:sb_g1:(f + 0x214)]
\load f0, [r0, #:sb_g2:(f + 0x214)]
\store f0, [r0, #:pc_g0:(f + 0x214)]
\store f0, [r0, #:pc_g1:(f + 0x214)]
\store f0, [r0, #:pc_g2:(f + 0x214)]
\store f0, [r0, #:sb_g0:(f + 0x214)]
\store f0, [r0, #:sb_g1:(f + 0x214)]
\store f0, [r0, #:sb_g2:(f + 0x214)]
\load f0, [r0, #:pc_g0:(f - 0x214)]
\load f0, [r0, #:pc_g1:(f - 0x214)]
\load f0, [r0, #:pc_g2:(f - 0x214)]
\load f0, [r0, #:sb_g0:(f - 0x214)]
\load f0, [r0, #:sb_g1:(f - 0x214)]
\load f0, [r0, #:sb_g2:(f - 0x214)]
\store f0, [r0, #:pc_g0:(f - 0x214)]
\store f0, [r0, #:pc_g1:(f - 0x214)]
\store f0, [r0, #:pc_g2:(f - 0x214)]
\store f0, [r0, #:sb_g0:(f - 0x214)]
\store f0, [r0, #:sb_g1:(f - 0x214)]
\store f0, [r0, #:sb_g2:(f - 0x214)]
.endm
fpa_test ldfs stfs
fpa_test ldfd stfd
fpa_test ldfe stfe
fpa_test ldfp stfp
@ FLDS/FSTS
.fpu vfp
.macro vfp_test load store reg
\load \reg, [r0, #:pc_g0:(f + 0x214)]
\load \reg, [r0, #:pc_g1:(f + 0x214)]
\load \reg, [r0, #:pc_g2:(f + 0x214)]
\load \reg, [r0, #:sb_g0:(f + 0x214)]
\load \reg, [r0, #:sb_g1:(f + 0x214)]
\load \reg, [r0, #:sb_g2:(f + 0x214)]
\store \reg, [r0, #:pc_g0:(f + 0x214)]
\store \reg, [r0, #:pc_g1:(f + 0x214)]
\store \reg, [r0, #:pc_g2:(f + 0x214)]
\store \reg, [r0, #:sb_g0:(f + 0x214)]
\store \reg, [r0, #:sb_g1:(f + 0x214)]
\store \reg, [r0, #:sb_g2:(f + 0x214)]
\load \reg, [r0, #:pc_g0:(f - 0x214)]
\load \reg, [r0, #:pc_g1:(f - 0x214)]
\load \reg, [r0, #:pc_g2:(f - 0x214)]
\load \reg, [r0, #:sb_g0:(f - 0x214)]
\load \reg, [r0, #:sb_g1:(f - 0x214)]
\load \reg, [r0, #:sb_g2:(f - 0x214)]
\store \reg, [r0, #:pc_g0:(f - 0x214)]
\store \reg, [r0, #:pc_g1:(f - 0x214)]
\store \reg, [r0, #:pc_g2:(f - 0x214)]
\store \reg, [r0, #:sb_g0:(f - 0x214)]
\store \reg, [r0, #:sb_g1:(f - 0x214)]
\store \reg, [r0, #:sb_g2:(f - 0x214)]
.endm
vfp_test flds fsts s0
@ FLDD/FSTD
vfp_test fldd fstd d0
@ VLDR/VSTR
vfp_test vldr vstr d0
@ CFLDRS/CFLDRD/CFLDR32/CFLDR64/CFSTRS/CFSTRD/CFSTR32/CFSTR64
.cpu ep9312
vfp_test cfldrs cfstrs mvf0
vfp_test cfldrd cfstrd mvd0
vfp_test cfldr32 cfstr32 mvfx0
vfp_test cfldr64 cfstr64 mvdx0

2
gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.d Normal file
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#name: Group relocation tests, encoding failures (ldr)
#error-output: group-reloc-ldr-encoding-bad.l

97
gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.l Normal file
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[^:]*: Assembler messages:
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:27: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:28: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:29: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:34: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00001000 \(only 12 bits available for the magnitude\)

39
gas/testsuite/gas/arm/group-reloc-ldr-encoding-bad.s Normal file
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@ -0,0 +1,39 @@
@ Tests that are supposed to fail during encoding
@ for LDR group relocations.
.text
.macro ldrtest load store sym offset
\load r0, [r0, #:pc_g0:(\sym \offset)]
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
\store r0, [r0, #:pc_g0:(\sym \offset)]
\store r0, [r0, #:pc_g1:(\sym \offset)]
\store r0, [r0, #:pc_g2:(\sym \offset)]
\store r0, [r0, #:sb_g0:(\sym \offset)]
\store r0, [r0, #:sb_g1:(\sym \offset)]
\store r0, [r0, #:sb_g2:(\sym \offset)]
.endm
@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
@ So these should all fail.
ldrtest ldr str f "+ 4096"
ldrtest ldrb strb f "+ 4096"
ldrtest ldr str f "- 4096"
ldrtest ldrb strb f "- 4096"
ldrtest ldr str localsym "+ 4096"
ldrtest ldrb strb localsym "+ 4096"
ldrtest ldr str localsym "- 4096"
ldrtest ldrb strb localsym "- 4096"
localsym:
mov r0, #0

2
gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.d Normal file
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@ -0,0 +1,2 @@
#name: Group relocation tests, parsing failures (ldr)
#error-output: group-reloc-ldr-parsing-bad.l

21
gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.l Normal file
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@ -0,0 +1,21 @@
[^:]*: Assembler messages:
[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldr r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:12: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:13: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:14: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:15: Error: this group relocation is not allowed on this instruction -- `str r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrb r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strb r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:29: Error: unknown group relocation -- `ldr r0,\[r0,#:foo:\(f\)\]'
[^:]*:30: Error: unknown group relocation -- `str r0,\[r0,#:foo:\(f\)\]'
[^:]*:31: Error: unknown group relocation -- `ldrb r0,\[r0,#:foo:\(f\)\]'
[^:]*:32: Error: unknown group relocation -- `strb r0,\[r0,#:foo:\(f\)\]'

33
gas/testsuite/gas/arm/group-reloc-ldr-parsing-bad.s Normal file
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@ -0,0 +1,33 @@
@ Tests that are supposed to fail during parsing of LDR group relocations.
.text
@ No NC variants exist for the LDR relocations.
ldr r0, [r0, #:pc_g0_nc:(f)]
ldr r0, [r0, #:pc_g1_nc:(f)]
ldr r0, [r0, #:sb_g0_nc:(f)]
ldr r0, [r0, #:sb_g1_nc:(f)]
str r0, [r0, #:pc_g0_nc:(f)]
str r0, [r0, #:pc_g1_nc:(f)]
str r0, [r0, #:sb_g0_nc:(f)]
str r0, [r0, #:sb_g1_nc:(f)]
ldrb r0, [r0, #:pc_g0_nc:(f)]
ldrb r0, [r0, #:pc_g1_nc:(f)]
ldrb r0, [r0, #:sb_g0_nc:(f)]
ldrb r0, [r0, #:sb_g1_nc:(f)]
strb r0, [r0, #:pc_g0_nc:(f)]
strb r0, [r0, #:pc_g1_nc:(f)]
strb r0, [r0, #:sb_g0_nc:(f)]
strb r0, [r0, #:sb_g1_nc:(f)]
@ Instructions with a gibberish relocation code.
ldr r0, [r0, #:foo:(f)]
str r0, [r0, #:foo:(f)]
ldrb r0, [r0, #:foo:(f)]
strb r0, [r0, #:foo:(f)]

199
gas/testsuite/gas/arm/group-reloc-ldr.d Normal file
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@ -0,0 +1,199 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: Group relocation tests (ldr)
.*: +file format .*arm.*
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
0: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
4: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
8: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
10: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
14: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
18: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
1c: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
20: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
24: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
28: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
2c: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
30: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
34: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
38: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
3c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
40: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
44: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
48: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
4c: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
50: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
54: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
58: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
5c: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
60: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
64: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
68: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
6c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
70: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
74: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
78: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
7c: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
80: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
84: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
88: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
8c: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
90: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
94: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
98: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
9c: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
a0: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
a4: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
a8: R_ARM_LDR_PC_G0 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
ac: R_ARM_LDR_PC_G1 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
b0: R_ARM_LDR_PC_G2 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
b4: R_ARM_LDR_SB_G0 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
b8: R_ARM_LDR_SB_G1 f
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
bc: R_ARM_LDR_SB_G2 f
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
c0: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
c4: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
c8: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
cc: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
d0: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5900fff ldr r0, \[r0, #4095\]
d4: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
d8: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
dc: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
e0: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
e4: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
e8: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5800fff str r0, \[r0, #4095\]
ec: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
f0: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
f4: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
f8: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
fc: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
100: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5d00fff ldrb r0, \[r0, #4095\]
104: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
108: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
10c: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
110: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
114: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
118: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5c00fff strb r0, \[r0, #4095\]
11c: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
120: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
124: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
128: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
12c: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
130: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5100fff ldr r0, \[r0, #-4095\]
134: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
138: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
13c: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
140: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
144: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
148: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5000fff str r0, \[r0, #-4095\]
14c: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
150: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
154: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
158: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
15c: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
160: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5500fff ldrb r0, \[r0, #-4095\]
164: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
168: R_ARM_LDR_PC_G0 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
16c: R_ARM_LDR_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
170: R_ARM_LDR_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
174: R_ARM_LDR_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
178: R_ARM_LDR_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e5400fff strb r0, \[r0, #-4095\]
17c: R_ARM_LDR_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0

41
gas/testsuite/gas/arm/group-reloc-ldr.s Normal file
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@ -0,0 +1,41 @@
@ Tests for LDR group relocations.
.text
.macro ldrtest load store sym offset
\load r0, [r0, #:pc_g0:(\sym \offset)]
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
\store r0, [r0, #:pc_g0:(\sym \offset)]
\store r0, [r0, #:pc_g1:(\sym \offset)]
\store r0, [r0, #:pc_g2:(\sym \offset)]
\store r0, [r0, #:sb_g0:(\sym \offset)]
\store r0, [r0, #:sb_g1:(\sym \offset)]
\store r0, [r0, #:sb_g2:(\sym \offset)]
.endm
@ LDR/STR/LDRB/STRB only have 12 bits available for the magnitude of the addend.
@ So these should all (just) work.
ldrtest ldr str f "+ 4095"
ldrtest ldrb strb f "+ 4095"
ldrtest ldr str f "- 4095"
ldrtest ldrb strb f "- 4095"
@ The same as the above, but for a local symbol. These should not be
@ resolved by the assembler but instead left to the linker.
ldrtest ldr str localsym "+ 4095"
ldrtest ldrb strb localsym "+ 4095"
ldrtest ldr str localsym "- 4095"
ldrtest ldrb strb localsym "- 4095"
localsym:
mov r0, #0

2
gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.d Normal file
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@ -0,0 +1,2 @@
#name: Group relocation tests, encoding failures (ldrs)
#error-output: group-reloc-ldrs-encoding-bad.l

121
gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.l Normal file
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@ -0,0 +1,121 @@
[^:]*: Assembler messages:
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:30: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:31: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:32: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:33: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:35: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:36: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:37: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:38: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:42: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:43: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:44: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:45: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:47: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:48: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:49: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)
[^:]*:50: Error: bad offset 0x00000100 \(only 8 bits available for the magnitude\)

54
gas/testsuite/gas/arm/group-reloc-ldrs-encoding-bad.s Normal file
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@ -0,0 +1,54 @@
@ Tests that are meant to fail during encoding of LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.endm
.macro ldrtest load store sym offset
ldrtest2 \load \sym \offset
\store r0, [r0, #:pc_g1:(\sym \offset)]
\store r0, [r0, #:pc_g2:(\sym \offset)]
\store r0, [r0, #:sb_g0:(\sym \offset)]
\store r0, [r0, #:sb_g1:(\sym \offset)]
\store r0, [r0, #:sb_g2:(\sym \offset)]
.endm
@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the
@ magnitude of the addend. So these should all (just) fail.
ldrtest ldrd strd f "+ 256"
ldrtest ldrh strh f "+ 256"
ldrtest2 ldrsh f "+ 256"
ldrtest2 ldrsb f "+ 256"
ldrtest ldrd strd f "- 256"
ldrtest ldrh strh f "- 256"
ldrtest2 ldrsh f "- 256"
ldrtest2 ldrsb f "- 256"
@ The same as the above, but for a local symbol.
ldrtest ldrd strd localsym "+ 256"
ldrtest ldrh strh localsym "+ 256"
ldrtest2 ldrsh localsym "+ 256"
ldrtest2 ldrsb localsym "+ 256"
ldrtest ldrd strd localsym "- 256"
ldrtest ldrh strh localsym "- 256"
ldrtest2 ldrsh localsym "- 256"
ldrtest2 ldrsb localsym "- 256"
localsym:
mov r0, #0

2
gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.d Normal file
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@ -0,0 +1,2 @@
#name: Group relocation tests, parsing failures (ldrs)
#error-output: group-reloc-ldrs-parsing-bad.l

31
gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.l Normal file
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@ -0,0 +1,31 @@
[^:]*: Assembler messages:
[^:]*:7: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:8: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:9: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:10: Error: this group relocation is not allowed on this instruction -- `ldrd r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:12: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:13: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:14: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:15: Error: this group relocation is not allowed on this instruction -- `strd r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:17: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:18: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:19: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:20: Error: this group relocation is not allowed on this instruction -- `ldrh r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:22: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:23: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:24: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:25: Error: this group relocation is not allowed on this instruction -- `strh r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:27: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:28: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:29: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:30: Error: this group relocation is not allowed on this instruction -- `ldrsh r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:32: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g0_nc:\(f\)\]'
[^:]*:33: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:pc_g1_nc:\(f\)\]'
[^:]*:34: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g0_nc:\(f\)\]'
[^:]*:35: Error: this group relocation is not allowed on this instruction -- `ldrsb r0,\[r0,#:sb_g1_nc:\(f\)\]'
[^:]*:38: Error: unknown group relocation -- `ldrd r0,\[r0,#:foo:\(f\)\]'
[^:]*:39: Error: unknown group relocation -- `strd r0,\[r0,#:foo:\(f\)\]'
[^:]*:40: Error: unknown group relocation -- `ldrh r0,\[r0,#:foo:\(f\)\]'
[^:]*:41: Error: unknown group relocation -- `strh r0,\[r0,#:foo:\(f\)\]'
[^:]*:42: Error: unknown group relocation -- `ldrsh r0,\[r0,#:foo:\(f\)\]'
[^:]*:43: Error: unknown group relocation -- `ldrsb r0,\[r0,#:foo:\(f\)\]'

44
gas/testsuite/gas/arm/group-reloc-ldrs-parsing-bad.s Normal file
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@ -0,0 +1,44 @@
@ Tests that are supposed to fail during parsing of LDRS group relocations.
.text
@ No NC variants exist for the LDRS relocations.
ldrd r0, [r0, #:pc_g0_nc:(f)]
ldrd r0, [r0, #:pc_g1_nc:(f)]
ldrd r0, [r0, #:sb_g0_nc:(f)]
ldrd r0, [r0, #:sb_g1_nc:(f)]
strd r0, [r0, #:pc_g0_nc:(f)]
strd r0, [r0, #:pc_g1_nc:(f)]
strd r0, [r0, #:sb_g0_nc:(f)]
strd r0, [r0, #:sb_g1_nc:(f)]
ldrh r0, [r0, #:pc_g0_nc:(f)]
ldrh r0, [r0, #:pc_g1_nc:(f)]
ldrh r0, [r0, #:sb_g0_nc:(f)]
ldrh r0, [r0, #:sb_g1_nc:(f)]
strh r0, [r0, #:pc_g0_nc:(f)]
strh r0, [r0, #:pc_g1_nc:(f)]
strh r0, [r0, #:sb_g0_nc:(f)]
strh r0, [r0, #:sb_g1_nc:(f)]
ldrsh r0, [r0, #:pc_g0_nc:(f)]
ldrsh r0, [r0, #:pc_g1_nc:(f)]
ldrsh r0, [r0, #:sb_g0_nc:(f)]
ldrsh r0, [r0, #:sb_g1_nc:(f)]
ldrsb r0, [r0, #:pc_g0_nc:(f)]
ldrsb r0, [r0, #:pc_g1_nc:(f)]
ldrsb r0, [r0, #:sb_g0_nc:(f)]
ldrsb r0, [r0, #:sb_g1_nc:(f)]
@ Instructions with a gibberish relocation code.
ldrd r0, [r0, #:foo:(f)]
strd r0, [r0, #:foo:(f)]
ldrh r0, [r0, #:foo:(f)]
strh r0, [r0, #:foo:(f)]
ldrsh r0, [r0, #:foo:(f)]
ldrsb r0, [r0, #:foo:(f)]

247
gas/testsuite/gas/arm/group-reloc-ldrs.d Normal file
View file

@ -0,0 +1,247 @@
#objdump: -dr --prefix-addresses --show-raw-insn
#name: Group relocation tests (ldrs)
.*: +file format .*arm.*
Disassembly of section .text:
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
0: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
4: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
8: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
c: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
10: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
14: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
18: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
1c: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
20: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
24: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
28: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
2c: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
30: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
34: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
38: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
3c: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
40: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
44: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
48: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
4c: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
50: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
54: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
58: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
5c: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
60: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
64: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
68: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
6c: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
70: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
74: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
78: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
7c: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
80: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
84: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
88: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
8c: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
90: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
94: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
98: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
9c: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
a0: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
a4: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
a8: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
ac: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
b0: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
b4: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
b8: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
bc: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
c0: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
c4: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
c8: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
cc: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
d0: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
d4: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
d8: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
dc: R_ARM_LDRS_PC_G1 f
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
e0: R_ARM_LDRS_PC_G2 f
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
e4: R_ARM_LDRS_SB_G0 f
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
e8: R_ARM_LDRS_SB_G1 f
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
ec: R_ARM_LDRS_SB_G2 f
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
f0: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
f4: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
f8: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
fc: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1c00fdf ldrd r0, \[r0, #255\]
100: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
104: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
108: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
10c: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
110: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1c00fff strd r0, \[r0, #255\]
114: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
118: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
11c: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
120: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
124: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1d00fbf ldrh r0, \[r0, #255\]
128: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
12c: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
130: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
134: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
138: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1c00fbf strh r0, \[r0, #255\]
13c: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
140: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
144: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
148: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
14c: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1d00fff ldrsh r0, \[r0, #255\]
150: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
154: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
158: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
15c: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
160: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1d00fdf ldrsb r0, \[r0, #255\]
164: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
168: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
16c: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
170: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
174: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1400fdf ldrd r0, \[r0, #-255\]
178: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
17c: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
180: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
184: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
188: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1400fff strd r0, \[r0, #-255\]
18c: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
190: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
194: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
198: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
19c: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1500fbf ldrh r0, \[r0, #-255\]
1a0: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
1a4: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
1a8: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
1ac: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
1b0: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1400fbf strh r0, \[r0, #-255\]
1b4: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
1b8: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
1bc: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
1c0: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
1c4: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1500fff ldrsh r0, \[r0, #-255\]
1c8: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
1cc: R_ARM_LDRS_PC_G1 localsym
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
1d0: R_ARM_LDRS_PC_G2 localsym
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
1d4: R_ARM_LDRS_SB_G0 localsym
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
1d8: R_ARM_LDRS_SB_G1 localsym
0[0-9a-f]+ <[^>]+> e1500fdf ldrsb r0, \[r0, #-255\]
1dc: R_ARM_LDRS_SB_G2 localsym
0[0-9a-f]+ <[^>]+> e3a00000 mov r0, #0 ; 0x0

54
gas/testsuite/gas/arm/group-reloc-ldrs.s Normal file
View file

@ -0,0 +1,54 @@
@ Tests for LDRS group relocations.
.text
.macro ldrtest2 load sym offset
\load r0, [r0, #:pc_g1:(\sym \offset)]
\load r0, [r0, #:pc_g2:(\sym \offset)]
\load r0, [r0, #:sb_g0:(\sym \offset)]
\load r0, [r0, #:sb_g1:(\sym \offset)]
\load r0, [r0, #:sb_g2:(\sym \offset)]
.endm
.macro ldrtest load store sym offset
ldrtest2 \load \sym \offset
\store r0, [r0, #:pc_g1:(\sym \offset)]
\store r0, [r0, #:pc_g2:(\sym \offset)]
\store r0, [r0, #:sb_g0:(\sym \offset)]
\store r0, [r0, #:sb_g1:(\sym \offset)]
\store r0, [r0, #:sb_g2:(\sym \offset)]
.endm
@ LDRD/STRD/LDRH/STRH/LDRSH/LDRSB only have 8 bits available for the
@ magnitude of the addend. So these should all (just) work.
ldrtest ldrd strd f "+ 255"
ldrtest ldrh strh f "+ 255"
ldrtest2 ldrsh f "+ 255"
ldrtest2 ldrsb f "+ 255"
ldrtest ldrd strd f "- 255"
ldrtest ldrh strh f "- 255"
ldrtest2 ldrsh f "- 255"
ldrtest2 ldrsb f "- 255"
@ The same as the above, but for a local symbol.
ldrtest ldrd strd localsym "+ 255"
ldrtest ldrh strh localsym "+ 255"
ldrtest2 ldrsh localsym "+ 255"
ldrtest2 ldrsb localsym "+ 255"
ldrtest ldrd strd localsym "- 255"
ldrtest ldrh strh localsym "- 255"
ldrtest2 ldrsh localsym "- 255"
ldrtest2 ldrsb localsym "- 255"
localsym:
mov r0, #0

7
include/elf/arm.h
View file

@ -169,9 +169,9 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
RELOC_NUMBER (R_ARM_LDRS_SB_G0, 78)
RELOC_NUMBER (R_ARM_LDRS_SB_G1, 79)
RELOC_NUMBER (R_ARM_LDRS_SB_G2, 80)
RELOC_NUMBER (R_ARM_LDC_G0, 81)
RELOC_NUMBER (R_ARM_LDC_G1, 82)
RELOC_NUMBER (R_ARM_LDC_G2, 83)
RELOC_NUMBER (R_ARM_LDC_SB_G0, 81)
RELOC_NUMBER (R_ARM_LDC_SB_G1, 82)
RELOC_NUMBER (R_ARM_LDC_SB_G2, 83)
RELOC_NUMBER (R_ARM_MOVW_BREL_NC, 84)
RELOC_NUMBER (R_ARM_MOVT_BREL, 85)
RELOC_NUMBER (R_ARM_MOVW_BREL, 86)
@ -221,7 +221,6 @@ START_RELOC_NUMBERS (elf_arm_reloc_type)
FAKE_RELOC (R_ARM_GOT32, R_ARM_GOT_BREL) /* 32 bit GOT entry. */
FAKE_RELOC (R_ARM_ROSEGREL32, R_ARM_SBREL31) /* ??? */
FAKE_RELOC (R_ARM_AMP_VCALL9, R_ARM_BREL_ADJ) /* Thumb-something. Not used. */
FAKE_RELOC (R_ARM_PC13, R_ARM_LDR_PC_G0) /* Unclear whether meaning is different. */
END_RELOC_NUMBERS (R_ARM_max)
#ifdef BFD_ARCH_SIZE

14
ld/testsuite/ChangeLog
View file

@ -1,3 +1,17 @@
2006-06-15 Mark Shinwell <shinwell@codesourcery.com>
* ld-arm/group-relocs-alu-bad.d: New test.
* ld-arm/group-relocs-alu-bad.s: New test.
* ld-arm/group-relocs.d: New test.
* ld-arm/group-relocs-ldc-bad.d: New test.
* ld-arm/group-relocs-ldc-bad.s: New test.
* ld-arm/group-relocs-ldr-bad.d: New test.
* ld-arm/group-relocs-ldr-bad.s: New test.
* ld-arm/group-relocs-ldrs-bad.d: New test.
* ld-arm/group-relocs-ldrs-bad.s: New test.
* ld-arm/group-relocs.s: New test.
* ld-arm/arm-elf.exp: Wire in new tests.
2006-06-14 Richard Sandiford <richard@codesourcery.com>
* ld-m68k/plt1.s, ld-m68k/plt1-empty.s, ld-m68k/plt1.ld: New files.

8
ld/testsuite/ld-arm/arm-elf.exp
View file

@ -59,6 +59,9 @@ if { ![is_elf_format] || ![istarget "arm*-*-*"] } {
# readelf: Apply readelf options on result. Compare with regex (last arg).
set armelftests {
{"Group relocations" "-Ttext 0x8000 --section-start zero=0x0 --section-start alpha=0xeef0 --section-start beta=0xffeef0" "" {group-relocs.s}
{{objdump -Dr group-relocs.d}}
"group-relocs"}
{"Simple non-PIC shared library" "-shared" "" {arm-lib.s}
{{objdump -fdw arm-lib.d} {objdump -Rw arm-lib.r}}
"arm-lib.so"}
@ -131,3 +134,8 @@ set armelftests {
}
run_ld_link_tests $armelftests
run_dump_test "group-relocs-alu-bad"
run_dump_test "group-relocs-ldr-bad"
run_dump_test "group-relocs-ldrs-bad"
run_dump_test "group-relocs-ldc-bad"

4
ld/testsuite/ld-arm/group-relocs-alu-bad.d Normal file
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@ -0,0 +1,4 @@
#name: ALU group relocations failure test
#source: group-relocs-alu-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x9010
#error: Overflow whilst splitting 0x1010 for group relocation

20
ld/testsuite/ld-arm/group-relocs-alu-bad.s Normal file
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@ -0,0 +1,20 @@
@ Test intended to fail for ALU group relocations.
@
@ Beware when editing this file: it is carefully crafted so that
@ a specific PC-relative offset arises.
@ We will place .text at 0x8000.
.text
.globl _start
_start:
add r0, r0, #:pc_g0:(bar)
@ We will place the section foo at 0x9004.
.section foo
bar:
mov r0, #0

4
ld/testsuite/ld-arm/group-relocs-ldc-bad.d Normal file
View file

@ -0,0 +1,4 @@
#name: LDC group relocations failure test
#source: group-relocs-ldc-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x118400
#error: Overflow whilst splitting 0x110400 for group relocation

19
ld/testsuite/ld-arm/group-relocs-ldc-bad.s Normal file
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@ -0,0 +1,19 @@
@ Test intended to fail for LDC group relocations.
@ We will place .text at 0x8000.
.text
.globl _start
_start:
add r0, r0, #:pc_g0_nc:(bar)
ldc 0, c0, [r0, #:pc_g1:(bar + 4)]
@ We will place the section foo at 0x118400.
@ (The relocations above would be OK if it were at 0x118200, for example.)
.section foo
bar:
mov r0, #0

4
ld/testsuite/ld-arm/group-relocs-ldr-bad.d Normal file
View file

@ -0,0 +1,4 @@
#name: LDR group relocations failure test
#source: group-relocs-ldr-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x8001000
#error: .*Overflow whilst splitting 0x8001000 for group relocation.*

18
ld/testsuite/ld-arm/group-relocs-ldr-bad.s Normal file
View file

@ -0,0 +1,18 @@
@ Test intended to fail for LDR group relocations.
@ We will place .text at 0x8000.
.text
.globl _start
_start:
add r0, r0, #:sb_g0_nc:(bar)
ldr r1, [r0, #:sb_g1:(bar)]
@ We will place the section foo at 0x8001000.
.section foo
bar:
mov r0, #0

4
ld/testsuite/ld-arm/group-relocs-ldrs-bad.d Normal file
View file

@ -0,0 +1,4 @@
#name: LDRS group relocations failure test
#source: group-relocs-ldrs-bad.s
#ld: -Ttext 0x8000 --section-start foo=0x8000100
#error: Overflow whilst splitting 0x8000100 for group relocation

17
ld/testsuite/ld-arm/group-relocs-ldrs-bad.s Normal file
View file

@ -0,0 +1,17 @@
@ Test intended to fail for LDRS group relocations.
@ We will place .text at 0x8000.
.text
.globl _start
_start:
add r0, r0, #:sb_g0_nc:(bar)
ldrd r2, [r0, #:sb_g1:(bar)]
@ We will place the section foo at 0x8000100.
.section foo
bar:
mov r0, #0

69
ld/testsuite/ld-arm/group-relocs.d Normal file
View file

@ -0,0 +1,69 @@
tmpdir/group-relocs: file format elf32-(little|big)arm
Disassembly of section .text:
00008000 <_start>:
8000: e28f00bc add r0, pc, #188 ; 0xbc
8004: e28f0c6e add r0, pc, #28160 ; 0x6e00
8008: e28000ec add r0, r0, #236 ; 0xec
800c: e28f08ff add r0, pc, #16711680 ; 0xff0000
8010: e2800c6e add r0, r0, #28160 ; 0x6e00
8014: e28000e4 add r0, r0, #228 ; 0xe4
8018: e2800000 add r0, r0, #0 ; 0x0
801c: e28f0cee add r0, pc, #60928 ; 0xee00
8020: e28000f0 add r0, r0, #240 ; 0xf0
8024: e28008ff add r0, r0, #16711680 ; 0xff0000
8028: e2800cee add r0, r0, #60928 ; 0xee00
802c: e28000f0 add r0, r0, #240 ; 0xf0
8030: e2800c6e add r0, r0, #28160 ; 0x6e00
8034: e59010c0 ldr r1, \[r0, #192\]
8038: e28008ff add r0, r0, #16711680 ; 0xff0000
803c: e2800c6e add r0, r0, #28160 ; 0x6e00
8040: e59010b8 ldr r1, \[r0, #184\]
8044: e5901000 ldr r1, \[r0\]
8048: e2800cee add r0, r0, #60928 ; 0xee00
804c: e59010f0 ldr r1, \[r0, #240\]
8050: e28008ff add r0, r0, #16711680 ; 0xff0000
8054: e2800cee add r0, r0, #60928 ; 0xee00
8058: e59010f0 ldr r1, \[r0, #240\]
805c: e1c026d0 ldrd r2, \[r0, #96\]
8060: e2800c6e add r0, r0, #28160 ; 0x6e00
8064: e1c029d0 ldrd r2, \[r0, #144\]
8068: e28008ff add r0, r0, #16711680 ; 0xff0000
806c: e2800c6e add r0, r0, #28160 ; 0x6e00
8070: e1c028d8 ldrd r2, \[r0, #136\]
8074: e1c020d0 ldrd r2, \[r0\]
8078: e2800cee add r0, r0, #60928 ; 0xee00
807c: e1c02fd0 ldrd r2, \[r0, #240\]
8080: e28008ff add r0, r0, #16711680 ; 0xff0000
8084: e2800cee add r0, r0, #60928 ; 0xee00
8088: e1c02fd0 ldrd r2, \[r0, #240\]
808c: ed90000c ldc 0, cr0, \[r0, #48\]
8090: e2800c6e add r0, r0, #28160 ; 0x6e00
8094: ed900018 ldc 0, cr0, \[r0, #96\]
8098: e28008ff add r0, r0, #16711680 ; 0xff0000
809c: e2800c6e add r0, r0, #28160 ; 0x6e00
80a0: ed900016 ldc 0, cr0, \[r0, #88\]
80a4: ed900000 ldc 0, cr0, \[r0\]
80a8: e2800cee add r0, r0, #60928 ; 0xee00
80ac: ed90003c ldc 0, cr0, \[r0, #240\]
80b0: e28008ff add r0, r0, #16711680 ; 0xff0000
80b4: e2800cee add r0, r0, #60928 ; 0xee00
80b8: ed90003c ldc 0, cr0, \[r0, #240\]
000080bc <one_group_needed_alu_pc>:
80bc: e3a00000 mov r0, #0 ; 0x0
Disassembly of section zero:
00000000 <one_group_needed_alu_sb>:
0: e3a00000 mov r0, #0 ; 0x0
Disassembly of section alpha:
0000eef0 <two_groups_needed_alu_pc>:
eef0: e3a00000 mov r0, #0 ; 0x0
Disassembly of section beta:
00ffeef0 <three_groups_needed_alu_pc>:
ffeef0: e3a00000 mov r0, #0 ; 0x0
#...

156
ld/testsuite/ld-arm/group-relocs.s Normal file
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@ -0,0 +1,156 @@
@ Tests for group relocations.
@
@ Beware when editing this file: it is carefully crafted so that
@ specific PC- and SB-relative offsets arise.
@
@ Note that the gas tests have already checked that group relocations are
@ handled in the same way for local and external symbols.
@ We will place .text at 0x8000.
.text
.globl _start
_start:
@ ALU, PC-relative
@ Instructions start at .text + 0x0
add r0, r15, #:pc_g0:(one_group_needed_alu_pc)
@ Instructions start at .text + 0x4
add r0, r15, #:pc_g0_nc:(two_groups_needed_alu_pc)
add r0, r0, #:pc_g1:(two_groups_needed_alu_pc + 4)
@ Instructions start at .text + 0xc
add r0, r15, #:pc_g0_nc:(three_groups_needed_alu_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_alu_pc + 4)
add r0, r0, #:pc_g2:(three_groups_needed_alu_pc + 8)
@ ALU, SB-relative
add r0, r0, #:sb_g0:(one_group_needed_alu_sb)
add r0, r15, #:sb_g0_nc:(two_groups_needed_alu_sb)
add r0, r0, #:sb_g1:(two_groups_needed_alu_sb)
add r0, r0, #:sb_g0_nc:(three_groups_needed_alu_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_alu_sb)
add r0, r0, #:sb_g2:(three_groups_needed_alu_sb)
@ LDR, PC-relative
@ Instructions start at .text + 0x30
add r0, r0, #:pc_g0_nc:(two_groups_needed_ldr_pc)
ldr r1, [r0, #:pc_g1:(two_groups_needed_ldr_pc + 4)]
@ Instructions start at .text + 0x38
add r0, r0, #:pc_g0_nc:(three_groups_needed_ldr_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_ldr_pc + 4)
ldr r1, [r0, #:pc_g2:(three_groups_needed_ldr_pc + 8)]
@ LDR, SB-relative
ldr r1, [r0, #:sb_g0:(one_group_needed_ldr_sb)]
add r0, r0, #:sb_g0_nc:(two_groups_needed_ldr_sb)
ldr r1, [r0, #:sb_g1:(two_groups_needed_ldr_sb)]
add r0, r0, #:sb_g0_nc:(three_groups_needed_ldr_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_ldr_sb)
ldr r1, [r0, #:sb_g2:(three_groups_needed_ldr_sb)]
@ LDRS, PC-relative
@ Instructions start at .text + 0x5c
ldrd r2, [r0, #:pc_g0:(one_group_needed_ldrs_pc)]
@ Instructions start at .text + 0x60
add r0, r0, #:pc_g0_nc:(two_groups_needed_ldrs_pc)
ldrd r2, [r0, #:pc_g1:(two_groups_needed_ldrs_pc + 4)]
@ Instructions start at .text + 0x68
add r0, r0, #:pc_g0_nc:(three_groups_needed_ldrs_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_ldrs_pc + 4)
ldrd r2, [r0, #:pc_g2:(three_groups_needed_ldrs_pc + 8)]
@ LDRS, SB-relative
ldrd r2, [r0, #:sb_g0:(one_group_needed_ldrs_sb)]
add r0, r0, #:sb_g0_nc:(two_groups_needed_ldrs_sb)
ldrd r2, [r0, #:sb_g1:(two_groups_needed_ldrs_sb)]
add r0, r0, #:sb_g0_nc:(three_groups_needed_ldrs_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_ldrs_sb)
ldrd r2, [r0, #:sb_g2:(three_groups_needed_ldrs_sb)]
@ LDC, PC-relative
@ Instructions start at .text + 0x8c
ldc 0, c0, [r0, #:pc_g0:(one_group_needed_ldc_pc)]
@ Instructions start at .text + 0x90
add r0, r0, #:pc_g0_nc:(two_groups_needed_ldc_pc)
ldc 0, c0, [r0, #:pc_g1:(two_groups_needed_ldc_pc + 4)]
@ Instructions start at .text + 0x98
add r0, r0, #:pc_g0_nc:(three_groups_needed_ldc_pc)
add r0, r0, #:pc_g1_nc:(three_groups_needed_ldc_pc + 4)
ldc 0, c0, [r0, #:pc_g2:(three_groups_needed_ldc_pc + 8)]
@ LDC, SB-relative
ldc 0, c0, [r0, #:sb_g0:(one_group_needed_ldc_sb)]
add r0, r0, #:sb_g0_nc:(two_groups_needed_ldc_sb)
ldc 0, c0, [r0, #:sb_g1:(two_groups_needed_ldc_sb)]
add r0, r0, #:sb_g0_nc:(three_groups_needed_ldc_sb)
add r0, r0, #:sb_g1_nc:(three_groups_needed_ldc_sb)
ldc 0, c0, [r0, #:sb_g2:(three_groups_needed_ldc_sb)]
@ This point in the file is .text + 0xbc.
one_group_needed_alu_pc:
one_group_needed_ldrs_pc:
one_group_needed_ldc_pc:
mov r0, #0
@ We will place the section zero at 0x0.
.section zero
one_group_needed_alu_sb:
one_group_needed_ldr_sb:
one_group_needed_ldrs_sb:
one_group_needed_ldc_sb:
mov r0, #0
@ We will place the section alpha at 0xeef0.
.section alpha
two_groups_needed_alu_sb:
two_groups_needed_ldr_sb:
two_groups_needed_ldrs_sb:
two_groups_needed_ldc_sb:
two_groups_needed_alu_pc:
two_groups_needed_ldr_pc:
two_groups_needed_ldrs_pc:
two_groups_needed_ldc_pc:
mov r0, #0
@ We will place the section beta at 0xffeef0.
.section beta
three_groups_needed_alu_sb:
three_groups_needed_ldr_sb:
three_groups_needed_ldrs_sb:
three_groups_needed_ldc_sb:
three_groups_needed_alu_pc:
three_groups_needed_ldr_pc:
three_groups_needed_ldrs_pc:
three_groups_needed_ldc_pc:
mov r0, #0