Add support for CRX co-processor opcodes
This commit is contained in:
Nick Clifton
parent
cea15572cd
commit
48c9f030c9
14 changed files with 294 additions and 136 deletions
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@ -1,3 +1,10 @@
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2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
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* config/tc-crx.c (preprocess_reglist): Handle Co-processor
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Special registers.
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(get_cinv_parameters): Add 'b' option to invalidate the
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branch-target cache.
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2004-10-05 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (unwind): New variable.
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@ -1724,7 +1724,7 @@ static int
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get_cinv_parameters (char * operand)
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{
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char *p = operand;
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int d_used = 0, i_used = 0, u_used = 0;
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int d_used = 0, i_used = 0, u_used = 0, b_used = 0;
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while (*++p != ']')
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{
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@ -1737,11 +1737,14 @@ get_cinv_parameters (char * operand)
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i_used = 1;
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else if (*p == 'u')
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u_used = 1;
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else if (*p == 'b')
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b_used = 1;
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else
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as_bad (_("Illegal `cinv' parameter: `%c'"), *p);
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}
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return ((d_used ? 4 : 0)
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return ((b_used ? 8 : 0)
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+ (d_used ? 4 : 0)
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+ (i_used ? 2 : 0)
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+ (u_used ? 1 : 0));
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}
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@ -2374,12 +2377,22 @@ preprocess_reglist (char *param, int *allocated)
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strncpy (reg_name, regP, paramP - regP);
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/* Coprocessor register c<N>. */
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if (IS_INSN_TYPE (COP_REG_INS))
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{
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if ((cr = get_copregister (reg_name)) == nullcopregister)
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as_bad (_("Illegal register `%s' in cop-register list"), reg_name);
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mask_reg (getreg_image (cr - c0), &mask);
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}
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/* Coprocessor Special register cs<N>. */
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else if (IS_INSN_TYPE (COPS_REG_INS))
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{
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if ((cr = get_copregister (reg_name)) == nullcopregister)
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as_bad (_("Illegal register `%s' in cop-special-register list"),
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reg_name);
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mask_reg (getreg_image (cr - cs0), &mask);
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}
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/* General purpose register r<N>. */
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else
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{
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if ((r = get_register (reg_name)) == nullregister)
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@ -1,3 +1,13 @@
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2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
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* gas/crx/cop_insn.s: New file.
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* gas/crx/cop_insn.d: Likewise.
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* gas/crx/load_stor_insn.s: Move Co-processor insns to a separate
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test.
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* gas/crx/misc_insn.s: Likewise.
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* gas/crx/load_stor_insn.d: Regenerate.
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* gas/crx/misc_insn.d: Likewise.
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2004-10-06 Aldy Hernandez <aldyh@redhat.com>
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* gas/ppc/e500.s: Add double-precision instructions.
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67
gas/testsuite/gas/crx/cop_insn.d
Normal file
67
gas/testsuite/gas/crx/cop_insn.d
Normal file
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@ -0,0 +1,67 @@
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#as:
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#objdump: -dr
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#name: cop_insn
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.*: +file format .*
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Disassembly of section .text:
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00000000 <mtcr>:
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0: 1f 30 1e 30 mtcr \$0xf, r1, c14
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00000004 <mfcr>:
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4: 13 30 72 31 mfcr \$0x3, c7, r2
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00000008 <mtcsr>:
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8: 12 30 51 32 mtcsr \$0x2, r5, cs1
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0000000c <mfcsr>:
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c: 11 30 ce 33 mfcsr \$0x1, cs12, r14
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00000010 <ldcr>:
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10: 11 30 38 34 ldcr \$0x1, r3, c8
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00000014 <stcr>:
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14: 12 30 4b 35 stcr \$0x2, r4, c11
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00000018 <ldcsr>:
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18: 14 30 6c 36 ldcsr \$0x4, r6, cs12
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0000001c <stcsr>:
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1c: 17 30 dd 37 stcsr \$0x7, r13, cs13
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00000020 <loadmcr>:
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20: 13 31 01 30 loadmcr \$0x3, r1, {c2,c3,c5}
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24: 2c 00
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00000026 <stormcr>:
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26: 1f 31 1e 30 stormcr \$0xf, r14, {c4,c7,c9,c10}
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2a: 90 06
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0000002c <loadmcsr>:
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2c: 1c 31 28 30 loadmcsr \$0xc, r8, {cs7,cs8,cs9,cs10,cs11}
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30: 80 0f
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00000032 <stormcsr>:
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32: 19 31 39 30 stormcsr \$0x9, r9, {cs4,cs7,cs10}
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36: 90 04
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00000038 <bcop>:
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38: 13 30 48 77 bcop \$0x7, \$0x3, \*\+0x90
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3c: 1c 31 fa 76 bcop \$0x6, \$0xc, \*\-0xbcdfe
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40: 01 19
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00000042 <cpdop>:
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42: 13 30 45 b2 cpdop \$0x3, \$0x2, r4, r5
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46: 17 31 12 ba cpdop \$0x7, \$0xa, r1, r2, \$0x1234
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4a: 34 12
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0000004c <mtpr>:
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4c: 09 30 10 00 mtpr r0, hi
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00000050 <mfpr>:
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50: 0a 30 05 11 mfpr lo, r5
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54: 0a 30 0a 90 mfpr uhi, r10
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00000058 <cinv>:
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58: 10 30 0f 00 cinv \[b,d,i,u\]
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77
gas/testsuite/gas/crx/cop_insn.s
Normal file
77
gas/testsuite/gas/crx/cop_insn.s
Normal file
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@ -0,0 +1,77 @@
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# Co-Processor instructions.
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.data
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foodata: .word 42
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.text
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footext:
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.global mtcr
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mtcr:
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mtcr $0xf, r1, c14
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.global mfcr
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mfcr:
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mfcr $3, c7, r2
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.global mtcsr
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mtcsr:
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mtcsr $0x2, r5, cs1
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.global mfcsr
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mfcsr:
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mfcsr $01, cs12, ra
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.global ldcr
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ldcr:
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ldcr $1, r3, c8
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.global stcr
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stcr:
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stcr $2, r4, c11
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.global ldcsr
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ldcsr:
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ldcsr $4, r6, cs12
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.global stcsr
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stcsr:
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stcsr $7, r13, cs13
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.global loadmcr
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loadmcr:
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loadmcr $3, r1, {c2,c3,c5}
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.global stormcr
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stormcr:
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stormcr $15, ra, {c10,c9,c7,c4}
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.global loadmcsr
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loadmcsr:
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loadmcsr $12, r8, {cs7, cs8, cs9, cs10, cs11}
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.global stormcsr
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stormcsr:
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stormcsr $9, r9, {cs10,cs7,cs4}
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.global bcop
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bcop:
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bcop $7, $3, 0x90
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bcop $6, $12, -0xbcdfe
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.global cpdop
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cpdop:
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cpdop $3, $2, r4, r5
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cpdop $7, $10, r1, r2, $0x1234
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.global mtpr
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mtpr:
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mtpr r0 , hi
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.global mfpr
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mfpr:
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mfpr lo , r5
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mfpr uhi , r10
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.global cinv
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cinv:
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cinv [i,d,u,b]
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@ -141,10 +141,3 @@ Disassembly of section .text:
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182: af 36 05 a0 stord \$0xf, 0x5\(r10\)\+
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186: a0 36 e4 bf stord \$0x0, 0xfe4\(r11\)\+
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0000018a <loadmcr>:
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18a: 13 31 01 30 loadmcr \$0x3, r1, {c2,c3,c5}
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18e: 2c 00
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00000190 <stormcr>:
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190: 1f 31 1e 30 stormcr \$0xf, r14, {c4,c7,c9,c10}
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194: 90 06
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@ -108,11 +108,3 @@ stord r14, -0657(r15,r7,1)
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stord $0xf, 05(r10)+
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stord $0x0, -034(r11)+
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# CO-processor registers
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.global loadmcr
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loadmcr:
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loadmcr $3, r1, {c2,c3,c5}
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.global stormcr
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stormcr:
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stormcr $15, ra, {c10,c9,c7,c4}
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@ -1,6 +1,6 @@
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#as:
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#objdump: -dr
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#name: load_stor_insn
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#name: misc_insn
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.*: +file format .*
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@ -213,48 +213,21 @@ Disassembly of section .text:
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0000010c <cntlsd>:
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10c: 08 30 2c ae cntlsd r2, r12
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00000110 <mtpr>:
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110: 09 30 10 00 mtpr r0, hi
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00000110 <excp>:
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110: f8 ff excp bpt
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112: f5 ff excp svc
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00000114 <mfpr>:
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114: 0a 30 05 11 mfpr lo, r5
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118: 0a 30 0a 90 mfpr uhi, r10
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00000114 <ram>:
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114: 61 3e ec 21 ram \$0x18, \$0x9, \$0x1, r14, r12
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0000011c <mtcr>:
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11c: 1f 30 1e 30 mtcr \$0xf, r1, c14
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00000118 <rim>:
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118: fd 3e 21 ee rim \$0x1f, \$0xf, \$0xe, r2, r1
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00000120 <mfcr>:
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120: 13 30 72 31 mfcr \$0x3, c7, r2
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0000011c <rotb>:
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11c: f1 fd rotb \$0x7, r1
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00000124 <mtcsr>:
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124: 12 30 51 32 mtcsr \$0x2, r5, cs1
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0000011e <rotw>:
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11e: d3 b9 rotw \$0xd, r3
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00000128 <mfcsr>:
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128: 11 30 ce 33 mfcsr \$0x1, cs12, r14
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0000012c <bcop>:
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12c: 13 30 48 77 bcop \$0x7, \$0x3, \*\+0x90
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130: 1c 31 fa 76 bcop \$0x6, \$0xc, \*\-0xbcdfe
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134: 01 19
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00000136 <excp>:
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136: f8 ff excp bpt
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138: f5 ff excp svc
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0000013a <cinv>:
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13a: 10 30 07 00 cinv \[d,i,u\]
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0000013e <ram>:
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13e: 61 3e ec 21 ram \$0x18, \$0x9, \$0x1, r14, r12
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00000142 <rim>:
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142: fd 3e 21 ee rim \$0x1f, \$0xf, \$0xe, r2, r1
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00000146 <rotb>:
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146: f1 fd rotb \$0x7, r1
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00000148 <rotw>:
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148: d3 b9 rotw \$0xd, r3
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0000014a <rotd>:
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14a: 08 30 b2 f1 rotd \$0x1b, r2
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00000120 <rotd>:
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120: 08 30 b2 f1 rotd \$0x1b, r2
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@ -284,45 +284,11 @@ subqd r0 , r10
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cntlsd:
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cntlsd r2 , r12
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.global mtpr
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mtpr:
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mtpr r0 , hi
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.global mfpr
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mfpr:
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mfpr lo , r5
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mfpr uhi , r10
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.global mtcr
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mtcr:
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mtcr $0xf, r1, c14
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.global mfcr
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mfcr:
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mfcr $3, c7, r2
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.global mtcsr
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mtcsr:
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mtcsr $0x2, r5, cs1
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.global mfcsr
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mfcsr:
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mfcsr $01, cs12, ra
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.global bcop
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bcop:
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bcop $7, $3, 0x90
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bcop $6, $12, -0xbcdfe
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.global excp
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excp:
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excp BPT
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excp svc
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.global cinv
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cinv:
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cinv [i,d,u]
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.global ram
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ram:
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ram $24, $9, $1, ra, r12
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@ -1,3 +1,8 @@
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2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
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* crx.h: Add COPS_REG_INS - Coprocessor Special register
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instruction type.
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2004-09-30 Paul Brook <paul@codesourcery.com>
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* arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define.
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@ -168,9 +168,10 @@ operand_type;
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#define DIV_INS 14
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#define COP_BRANCH_INS 15
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#define COP_REG_INS 16
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#define DCR_BRANCH_INS 17
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#define MMC_INS 18
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#define MMU_INS 19
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#define COPS_REG_INS 17
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#define DCR_BRANCH_INS 18
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#define MMC_INS 19
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#define MMU_INS 20
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/* Maximum value supported for instruction types. */
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#define CRX_INS_MAX (1 << 5)
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@ -1,3 +1,12 @@
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2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
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* crx-opc.c (crx_instruction): Support Co-processor insns.
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* crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
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(getregliststring): Change function to use the above enum.
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(print_arg): Handle CO-Processor insns.
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(crx_cinvs): Add 'b' option to invalidate the branch-target
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cache.
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2004-10-06 Aldy Hernandez <aldyh@redhat.com>
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* ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
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@ -59,10 +59,25 @@ cinv_entry;
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/* CRX 'cinv' options. */
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const cinv_entry crx_cinvs[] =
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{
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{"[i]", 2}, {"[i,u]", 3}, {"[d]", 4},
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{"[d,u]", 5}, {"[d,i]", 6}, {"[d,i,u]", 7}
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{"[i]", 2}, {"[i,u]", 3}, {"[d]", 4}, {"[d,u]", 5},
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{"[d,i]", 6}, {"[d,i,u]", 7}, {"[b]", 8},
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{"[b,i]", 10}, {"[b,i,u]", 11}, {"[b,d]", 12},
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{"[b,d,u]", 13}, {"[b,d,i]", 14}, {"[b,d,i,u]", 15}
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};
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/* Enum to distinguish CO-Processor [special] registers arguments
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from general purpose regidters. */
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typedef enum COP_ARG_TYPE
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{
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/* Not a CO-Processor argument (probably a general purpose reg.). */
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NO_COP_ARG = 0,
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/* A CO-Processor argument (c<N>). */
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COP_ARG,
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/* A CO-Processor special argument (cs<N>). */
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COPS_ARG
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}
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COP_ARG_TYPE;
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/* Number of valid 'cinv' instruction options. */
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int NUMCINVS = ((sizeof crx_cinvs)/(sizeof crx_cinvs[0]));
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/* Current opcode table entry we're disassembling. */
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@ -89,7 +104,7 @@ static char *getcopregname (copreg, reg_type);
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static char * getprocregname (int);
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static char *gettrapstring (unsigned);
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static char *getcinvstring (unsigned);
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static void getregliststring (int, char *, int);
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static void getregliststring (int, char *, enum COP_ARG_TYPE);
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static wordU get_word_at_PC (bfd_vma, struct disassemble_info *);
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static void get_words_at_PC (bfd_vma, struct disassemble_info *);
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static unsigned long build_mask (void);
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@ -225,7 +240,7 @@ powerof2 (int x)
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/* Transform a register bit mask to a register list. */
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void
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getregliststring (int trap, char *string, int core_cop)
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getregliststring (int trap, char *string, enum COP_ARG_TYPE core_cop)
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{
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char temp_string[5];
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int i;
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@ -236,11 +251,21 @@ getregliststring (int trap, char *string, int core_cop)
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for (i = 0; i < 16; i++)
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{
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if (trap & 0x1)
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{
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if (core_cop)
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sprintf (temp_string, "r%d", i);
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else
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sprintf (temp_string, "c%d", i);
|
||||
{
|
||||
switch (core_cop)
|
||||
{
|
||||
case NO_COP_ARG:
|
||||
sprintf (temp_string, "r%d", i);
|
||||
break;
|
||||
case COP_ARG:
|
||||
sprintf (temp_string, "c%d", i);
|
||||
break;
|
||||
case COPS_ARG:
|
||||
sprintf (temp_string, "cs%d", i);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
strcat (string, temp_string);
|
||||
if (trap & 0xfffe)
|
||||
strcat (string, ",");
|
||||
|
|
@ -490,21 +515,25 @@ print_arg (argument *a, struct disassemble_info *info)
|
|||
|
||||
else if (INST_HAS_REG_LIST)
|
||||
{
|
||||
if (!IS_INSN_TYPE (COP_REG_INS))
|
||||
{
|
||||
getregliststring (a->constant, string, 1);
|
||||
func (stream, "%s", string);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check for proper argument number. */
|
||||
if (processing_argument_number == 2)
|
||||
{
|
||||
getregliststring (a->constant, string, 0);
|
||||
func (stream, "%s", string);
|
||||
}
|
||||
else
|
||||
COP_ARG_TYPE cop_ins = IS_INSN_TYPE (COP_REG_INS) ?
|
||||
COP_ARG : IS_INSN_TYPE (COPS_REG_INS) ?
|
||||
COPS_ARG : NO_COP_ARG;
|
||||
|
||||
if (cop_ins != NO_COP_ARG)
|
||||
{
|
||||
/* Check for proper argument number. */
|
||||
if (processing_argument_number == 2)
|
||||
{
|
||||
getregliststring (a->constant, string, cop_ins);
|
||||
func (stream, "%s", string);
|
||||
}
|
||||
else
|
||||
func (stream, "$0x%x", a->constant);
|
||||
}
|
||||
else
|
||||
{
|
||||
getregliststring (a->constant, string, cop_ins);
|
||||
func (stream, "%s", string);
|
||||
}
|
||||
}
|
||||
else
|
||||
|
|
|
|||
|
|
@ -488,39 +488,55 @@ const inst crx_instruction[] =
|
|||
|
||||
BR_INST ("bal", 0x307, 0x317, 0),
|
||||
|
||||
/* Decrement and Branch instructions */
|
||||
/* Decrement and Branch instructions. */
|
||||
BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS),
|
||||
BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS),
|
||||
BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS),
|
||||
|
||||
/* Jump and link instructions */
|
||||
/* Jump and link instructions. */
|
||||
REG1_INST ("jal", 0xFF8),
|
||||
REG2_INST ("jal", 0x37),
|
||||
REG2_INST ("jalid", 0x33),
|
||||
|
||||
/* opc12 c4 opc12 r mask16 */
|
||||
{"loadmcr", 3, 0x3110300, 4, COP_REG_INS | REG_LIST | FMT_5, {{i4,16}, {regr,0}, {i16,0}}},
|
||||
{"stormcr", 3, 0x3110301, 4, COP_REG_INS | REG_LIST | FMT_5, {{i4,16}, {regr,0}, {i16,0}}},
|
||||
/* Create a CO-processor instruction. */
|
||||
#define COP_INST(NAME, OPC, TYPE, REG1, REG2) \
|
||||
/* opc12 c4 opc8 REG1 REG2 */ \
|
||||
{NAME, 2, 0x301030+OPC, 8, TYPE | FMT_2, {{i4,16}, {REG1,4}, {REG2,0}}}
|
||||
|
||||
/* esc16 r procreg */
|
||||
{"mtpr", 2, 0x3009, 16, 0, {{regr8,8}, {regr8,0}}},
|
||||
/* esc16 procreg r */
|
||||
{"mfpr", 2, 0x300A, 16, 0, {{regr8,8}, {regr8,0}}},
|
||||
/* opc12 c4 opc8 r copreg */
|
||||
{"mtcr", 2, 0x301030, 8, COP_REG_INS | FMT_2, {{i4,16}, {regr,4}, {copregr,0}}},
|
||||
/* opc12 c4 opc8 copreg r */
|
||||
{"mfcr", 2, 0x301031, 8, COP_REG_INS | FMT_2, {{i4,16}, {copregr,4}, {regr,0}}},
|
||||
/* opc12 c4 opc8 r copsreg */
|
||||
{"mtcsr", 2, 0x301032, 8, COP_REG_INS | FMT_2, {{i4,16}, {regr,4}, {copsregr,0}}},
|
||||
/* opc12 c4 opc8 copsreg r */
|
||||
{"mfcsr", 2, 0x301033, 8, COP_REG_INS | FMT_2, {{i4,16}, {copsregr,4}, {regr,0}}},
|
||||
COP_INST ("mtcr", 0, COP_REG_INS, regr, copregr),
|
||||
COP_INST ("mfcr", 1, COP_REG_INS, copregr, regr),
|
||||
COP_INST ("mtcsr", 2, COPS_REG_INS, regr, copsregr),
|
||||
COP_INST ("mfcsr", 3, COPS_REG_INS, copsregr, regr),
|
||||
COP_INST ("ldcr", 4, COP_REG_INS, regr, copregr),
|
||||
COP_INST ("stcr", 5, COP_REG_INS, regr, copregr),
|
||||
COP_INST ("ldcsr", 6, COPS_REG_INS, regr, copsregr),
|
||||
COP_INST ("stcsr", 7, COPS_REG_INS, regr, copsregr),
|
||||
|
||||
/* CO-processor extensions */
|
||||
/* Create a memory-related CO-processor instruction. */
|
||||
#define COPMEM_INST(NAME, OPC, TYPE) \
|
||||
/* opc12 c4 opc12 r mask16 */ \
|
||||
{NAME, 3, 0x3110300+OPC, 4, TYPE | REG_LIST | FMT_5, {{i4,16}, {regr,0}, {i16,0}}}
|
||||
|
||||
COPMEM_INST("loadmcr", 0, COP_REG_INS),
|
||||
COPMEM_INST("stormcr", 1, COP_REG_INS),
|
||||
COPMEM_INST("loadmcsr", 2, COPS_REG_INS),
|
||||
COPMEM_INST("stormcsr", 3, COPS_REG_INS),
|
||||
|
||||
/* CO-processor extensions. */
|
||||
/* opc12 c4 opc4 i4 disps9 */
|
||||
{"bcop", 2, 0x30107, 12, COP_BRANCH_INS | FMT_4, {{i4,16}, {i4,8}, {d9,0}}},
|
||||
/* opc12 c4 opc4 i4 disps25 */
|
||||
{"bcop", 3, 0x31107, 12, COP_BRANCH_INS | FMT_4, {{i4,16}, {i4,8}, {d25,0}}},
|
||||
/* opc12 c4 opc4 cpdo r r */
|
||||
{"cpdop", 2, 0x3010B, 12, COP_REG_INS | FMT_4, {{i4,16}, {i4,8}, {regr,4}, {regr,0}}},
|
||||
/* opc12 c4 opc4 cpdo r r cpdo16 */
|
||||
{"cpdop", 3, 0x3110B, 12, COP_REG_INS | FMT_4, {{i4,16}, {i4,8}, {regr,4}, {regr,0}, {i16,0}}},
|
||||
/* esc16 r procreg */
|
||||
{"mtpr", 2, 0x3009, 16, 0, {{regr8,8}, {regr8,0}}},
|
||||
/* esc16 procreg r */
|
||||
{"mfpr", 2, 0x300A, 16, 0, {{regr8,8}, {regr8,0}}},
|
||||
|
||||
/* Miscellaneous. */
|
||||
/* opc12 i4 */
|
||||
{"excp", 1, 0xFFF, 20, 0, {{i4,16}}},
|
||||
/* opc28 i4 */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue