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[gas/]

Browse source 
* config/tc-mips.c (macro2): Implement rotates by zero using shifts
        by zero.

[gas/testsuite]
	* gas/mips/rol.s: Add rotate by zero tests.
	* gas/mips/rol.d: Update accordingly.
	* gas/mips/rol64.d: Expect rotates by zero to use dsrl.
This commit is contained in:
Richard Sandiford 2002-08-20 08:28:35 +00:00
parent a08bafb59b
commit 483fc7cd61
6 changed files with 130 additions and 91 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2002-08-20 Richard Sandiford <rsandifo@redhat.com>
* config/tc-mips.c (macro2): Implement rotates by zero using shifts
by zero.
2002-08-19 Elena Zannoni <ezannoni@redhat.com> 2002-08-19 Elena Zannoni <ezannoni@redhat.com>
From matthew green <mrg@redhat.com> From matthew green <mrg@redhat.com>

98
gas/config/tc-mips.c
View file

@ -6653,22 +6653,27 @@ macro2 (ip)
case M_DROL_I: case M_DROL_I:
{ {
unsigned int rot; unsigned int rot;
char *l, *r;
if (imm_expr.X_op != O_constant) if (imm_expr.X_op != O_constant)
as_bad (_("rotate count too large")); as_bad (_("rotate count too large"));
rot = imm_expr.X_add_number & 0x3f; rot = imm_expr.X_add_number & 0x3f;
if (! rot) if (rot == 0)
break; macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
l = (rot < 0x20) ? "dsll" : "dsll32"; "d,w,<", dreg, sreg, 0);
r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32"; else
rot &= 0x1f; {
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, char *l, *r;
"d,w,<", AT, sreg, rot);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, l = (rot < 0x20) ? "dsll" : "dsll32";
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); r = ((0x40 - rot) < 0x20) ? "dsrl" : "dsrl32";
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", rot &= 0x1f;
"d,v,t", dreg, dreg, AT); macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
"d,w,<", AT, sreg, rot);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
"d,v,t", dreg, dreg, AT);
}
} }
break; break;
@ -6679,14 +6684,18 @@ macro2 (ip)
if (imm_expr.X_op != O_constant) if (imm_expr.X_op != O_constant)
as_bad (_("rotate count too large")); as_bad (_("rotate count too large"));
rot = imm_expr.X_add_number & 0x1f; rot = imm_expr.X_add_number & 0x1f;
if (! rot) if (rot == 0)
break; macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", "d,w,<", dreg, sreg, 0);
"d,w,<", AT, sreg, rot); else
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", {
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,w,<", AT, sreg, rot);
"d,v,t", dreg, dreg, AT); macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
"d,v,t", dreg, dreg, AT);
}
} }
break; break;
@ -6715,22 +6724,27 @@ macro2 (ip)
case M_DROR_I: case M_DROR_I:
{ {
unsigned int rot; unsigned int rot;
char *l, *r;
if (imm_expr.X_op != O_constant) if (imm_expr.X_op != O_constant)
as_bad (_("rotate count too large")); as_bad (_("rotate count too large"));
rot = imm_expr.X_add_number & 0x3f; rot = imm_expr.X_add_number & 0x3f;
if (! rot) if (rot == 0)
break; macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "dsrl",
r = (rot < 0x20) ? "dsrl" : "dsrl32"; "d,w,<", dreg, sreg, 0);
l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32"; else
rot &= 0x1f; {
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r, char *l, *r;
"d,w,<", AT, sreg, rot);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l, r = (rot < 0x20) ? "dsrl" : "dsrl32";
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); l = ((0x40 - rot) < 0x20) ? "dsll" : "dsll32";
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", rot &= 0x1f;
"d,v,t", dreg, dreg, AT); macro_build ((char *) NULL, &icnt, (expressionS *) NULL, r,
"d,w,<", AT, sreg, rot);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, l,
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
"d,v,t", dreg, dreg, AT);
}
} }
break; break;
@ -6741,14 +6755,18 @@ macro2 (ip)
if (imm_expr.X_op != O_constant) if (imm_expr.X_op != O_constant)
as_bad (_("rotate count too large")); as_bad (_("rotate count too large"));
rot = imm_expr.X_add_number & 0x1f; rot = imm_expr.X_add_number & 0x1f;
if (! rot) if (rot == 0)
break; macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl", "d,w,<", dreg, sreg, 0);
"d,w,<", AT, sreg, rot); else
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll", {
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f); macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "srl",
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or", "d,w,<", AT, sreg, rot);
"d,v,t", dreg, dreg, AT); macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "sll",
"d,w,<", dreg, sreg, (0x20 - rot) & 0x1f);
macro_build ((char *) NULL, &icnt, (expressionS *) NULL, "or",
"d,v,t", dreg, dreg, AT);
}
} }
break; break;

6
gas/testsuite/ChangeLog
View file

@ -1,3 +1,9 @@
2002-08-20 Richard Sandiford <rsandifo@redhat.com>
* gas/mips/rol.s: Add rotate by zero tests.
* gas/mips/rol.d: Update accordingly.
* gas/mips/rol64.d: Expect rotates by zero to use dsrl.
2002-08-19 Elena Zannoni <ezannoni@redhat.com> 2002-08-19 Elena Zannoni <ezannoni@redhat.com>
From matthew green <mrg@redhat.com> From matthew green <mrg@redhat.com>

31
gas/testsuite/gas/mips/rol.d
View file

@ -21,17 +21,20 @@ Disassembly of section .text:
0+002c <[^>]*> sll at,a1,0x1 0+002c <[^>]*> sll at,a1,0x1
0+0030 <[^>]*> srl a0,a1,0x1f 0+0030 <[^>]*> srl a0,a1,0x1f
0+0034 <[^>]*> or a0,a0,at 0+0034 <[^>]*> or a0,a0,at
0+0038 <[^>]*> negu at,a1 0+0038 <[^>]*> srl a0,a1,0x0
0+003c <[^>]*> sllv at,a0,at 0+003c <[^>]*> negu at,a1
0+0040 <[^>]*> srlv a0,a0,a1 0+0040 <[^>]*> sllv at,a0,at
0+0044 <[^>]*> or a0,a0,at 0+0044 <[^>]*> srlv a0,a0,a1
0+0048 <[^>]*> negu at,a2 0+0048 <[^>]*> or a0,a0,at
0+004c <[^>]*> sllv at,a1,at 0+004c <[^>]*> negu at,a2
0+0050 <[^>]*> srlv a0,a1,a2 0+0050 <[^>]*> sllv at,a1,at
0+0054 <[^>]*> or a0,a0,at 0+0054 <[^>]*> srlv a0,a1,a2
0+0058 <[^>]*> srl at,a0,0x1 0+0058 <[^>]*> or a0,a0,at
0+005c <[^>]*> sll a0,a0,0x1f 0+005c <[^>]*> srl at,a0,0x1
0+0060 <[^>]*> or a0,a0,at 0+0060 <[^>]*> sll a0,a0,0x1f
0+0064 <[^>]*> srl at,a1,0x1 0+0064 <[^>]*> or a0,a0,at
0+0068 <[^>]*> sll a0,a1,0x1f 0+0068 <[^>]*> srl at,a1,0x1
0+006c <[^>]*> or a0,a0,at 0+006c <[^>]*> sll a0,a1,0x1f
0+0070 <[^>]*> or a0,a0,at
0+0074 <[^>]*> srl a0,a1,0x0
...

3
gas/testsuite/gas/mips/rol.s
View file

@ -5,8 +5,11 @@ foo:
rol $4,$5,$6 rol $4,$5,$6
rol $4,1 rol $4,1
rol $4,$5,1 rol $4,$5,1
rol $4,$5,0
ror $4,$5 ror $4,$5
ror $4,$5,$6 ror $4,$5,$6
ror $4,1 ror $4,1
ror $4,$5,1 ror $4,$5,1
ror $4,$5,0
.space 8

78
gas/testsuite/gas/mips/rol64.d
View file

@ -18,45 +18,49 @@ Disassembly of section .text:
0+0020 <[^>]*> dsll at,a0,0x1 0+0020 <[^>]*> dsll at,a0,0x1
0+0024 <[^>]*> dsrl32 a0,a0,0x1f 0+0024 <[^>]*> dsrl32 a0,a0,0x1f
0+0028 <[^>]*> or a0,a0,at 0+0028 <[^>]*> or a0,a0,at
0+002c <[^>]*> dsll at,a1,0x1 0+002c <[^>]*> dsrl a0,a1,0x0
0+0030 <[^>]*> dsrl32 a0,a1,0x1f 0+0030 <[^>]*> dsll at,a1,0x1
0+0034 <[^>]*> or a0,a0,at 0+0034 <[^>]*> dsrl32 a0,a1,0x1f
0+0038 <[^>]*> dsll at,a1,0x1f 0+0038 <[^>]*> or a0,a0,at
0+003c <[^>]*> dsrl32 a0,a1,0x1 0+003c <[^>]*> dsll at,a1,0x1f
0+0040 <[^>]*> or a0,a0,at 0+0040 <[^>]*> dsrl32 a0,a1,0x1
0+0044 <[^>]*> dsll32 at,a1,0x0 0+0044 <[^>]*> or a0,a0,at
0+0048 <[^>]*> dsrl32 a0,a1,0x0 0+0048 <[^>]*> dsll32 at,a1,0x0
0+004c <[^>]*> or a0,a0,at 0+004c <[^>]*> dsrl32 a0,a1,0x0
0+0050 <[^>]*> dsll32 at,a1,0x1 0+0050 <[^>]*> or a0,a0,at
0+0054 <[^>]*> dsrl a0,a1,0x1f 0+0054 <[^>]*> dsll32 at,a1,0x1
0+0058 <[^>]*> or a0,a0,at 0+0058 <[^>]*> dsrl a0,a1,0x1f
0+005c <[^>]*> dsll32 at,a1,0x1f 0+005c <[^>]*> or a0,a0,at
0+0060 <[^>]*> dsrl a0,a1,0x1 0+0060 <[^>]*> dsll32 at,a1,0x1f
0+0064 <[^>]*> or a0,a0,at 0+0064 <[^>]*> dsrl a0,a1,0x1
0+0068 <[^>]*> dnegu at,a1 0+0068 <[^>]*> or a0,a0,at
0+006c <[^>]*> dsllv at,a0,at 0+006c <[^>]*> dsrl a0,a1,0x0
0+0070 <[^>]*> dsrlv a0,a0,a1 0+0070 <[^>]*> dnegu at,a1
0+0074 <[^>]*> or a0,a0,at 0+0074 <[^>]*> dsllv at,a0,at
0+0078 <[^>]*> dnegu at,a2 0+0078 <[^>]*> dsrlv a0,a0,a1
0+007c <[^>]*> dsllv at,a1,at 0+007c <[^>]*> or a0,a0,at
0+0080 <[^>]*> dsrlv a0,a1,a2 0+0080 <[^>]*> dnegu at,a2
0+0084 <[^>]*> or a0,a0,at 0+0084 <[^>]*> dsllv at,a1,at
0+0088 <[^>]*> dsrl at,a0,0x1 0+0088 <[^>]*> dsrlv a0,a1,a2
0+008c <[^>]*> dsll32 a0,a0,0x1f 0+008c <[^>]*> or a0,a0,at
0+0090 <[^>]*> or a0,a0,at 0+0090 <[^>]*> dsrl at,a0,0x1
0+0094 <[^>]*> dsrl at,a1,0x1 0+0094 <[^>]*> dsll32 a0,a0,0x1f
0+0098 <[^>]*> dsll32 a0,a1,0x1f 0+0098 <[^>]*> or a0,a0,at
0+009c <[^>]*> or a0,a0,at 0+009c <[^>]*> dsrl a0,a1,0x0
0+00a0 <[^>]*> dsrl at,a1,0x1f 0+00a0 <[^>]*> dsrl at,a1,0x1
0+00a4 <[^>]*> dsll32 a0,a1,0x1 0+00a4 <[^>]*> dsll32 a0,a1,0x1f
0+00a8 <[^>]*> or a0,a0,at 0+00a8 <[^>]*> or a0,a0,at
0+00ac <[^>]*> dsrl32 at,a1,0x0 0+00ac <[^>]*> dsrl at,a1,0x1f
0+00b0 <[^>]*> dsll32 a0,a1,0x0 0+00b0 <[^>]*> dsll32 a0,a1,0x1
0+00b4 <[^>]*> or a0,a0,at 0+00b4 <[^>]*> or a0,a0,at
0+00b8 <[^>]*> dsrl32 at,a1,0x1 0+00b8 <[^>]*> dsrl32 at,a1,0x0
0+00bc <[^>]*> dsll a0,a1,0x1f 0+00bc <[^>]*> dsll32 a0,a1,0x0
0+00c0 <[^>]*> or a0,a0,at 0+00c0 <[^>]*> or a0,a0,at
0+00c4 <[^>]*> dsrl32 at,a1,0x1f 0+00c4 <[^>]*> dsrl32 at,a1,0x1
0+00c8 <[^>]*> dsll a0,a1,0x1 0+00c8 <[^>]*> dsll a0,a1,0x1f
0+00cc <[^>]*> or a0,a0,at 0+00cc <[^>]*> or a0,a0,at
0+00d0 <[^>]*> dsrl32 at,a1,0x1f
0+00d4 <[^>]*> dsll a0,a1,0x1
0+00d8 <[^>]*> or a0,a0,at
0+00dc <[^>]*> dsrl a0,a1,0x0
... ...