aarch64: Add support for (M)ADDPT and (M)SUBPT instructions
The following instructions are added in this patch: - ADDPT and SUBPT - Add/Subtract checked pointer - MADDPT and MSUBPT - Multiply Add/Subtract checked pointer These instructions are part of Checked Pointer Arithmetic extension. This patch adds assembler and disassembler support for these instructions with relevant checks. Tests are included as well. A new flag "+cpa" added to documentation. This flag enables CPA extension. Regression tested on the aarch64-none-linux-gnu target and no regressions have been found.
This commit is contained in:
Yury Khrustalev
Nick Clifton
parent
ee0fa66270
commit
4792a423d2
16 changed files with 313 additions and 1 deletions
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@ -3748,6 +3748,41 @@ parse_shifter_operand (char **str, aarch64_opnd_info *operand,
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return parse_shifter_operand_imm (str, operand, mode);
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}
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static bool
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parse_reg_lsl_shifter_operand (char **str, aarch64_opnd_info *operand)
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{
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aarch64_opnd_qualifier_t qualifier;
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const reg_entry *reg = aarch64_reg_parse_32_64 (str, &qualifier);
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if (reg)
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{
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if (!aarch64_check_reg_type (reg, REG_TYPE_R_ZR))
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{
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set_expected_reg_error (REG_TYPE_R_ZR, reg, 0);
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return false;
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}
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operand->reg.regno = reg->number;
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operand->qualifier = qualifier;
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/* Accept optional LSL shift operation on register. */
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if (!skip_past_comma (str))
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return true;
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if (!parse_shift (str, operand, SHIFTED_LSL))
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return false;
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return true;
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}
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else
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{
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set_syntax_error
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(_("integer register expected in the shifted operand "
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"register"));
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return false;
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}
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}
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/* Return TRUE on success; return FALSE otherwise. */
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static bool
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@ -6593,6 +6628,17 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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}
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break;
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case AARCH64_OPND_Rm_LSL:
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po_misc_or_fail (parse_reg_lsl_shifter_operand (&str, info));
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if (!info->shifter.operator_present)
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{
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/* Default to LSL #0 if not present. */
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gas_assert (info->shifter.kind == AARCH64_MOD_NONE);
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info->shifter.kind = AARCH64_MOD_LSL;
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info->shifter.amount = 0;
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}
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break;
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case AARCH64_OPND_Fd:
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case AARCH64_OPND_Fn:
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case AARCH64_OPND_Fm:
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@ -10429,6 +10475,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
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{"sme2p1", AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SME2)},
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{"sve2p1", AARCH64_FEATURE (SVE2p1), AARCH64_FEATURE (SVE2)},
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{"rcpc3", AARCH64_FEATURE (RCPC3), AARCH64_FEATURE (RCPC2)},
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{"cpa", AARCH64_FEATURE (CPA), AARCH64_NO_FEATURES},
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{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
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};
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@ -289,6 +289,8 @@ automatically cause those extensions to be disabled.
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@tab Enable @code{wfet} and @code{wfit} instructions.
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@item @code{xs} @tab
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@tab Enable the XS memory attribute extension.
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@item @code{cpa} @tab
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@tab Enable the Checked Pointer Arithmetic extension.
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@end multitable
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@multitable @columnfractions .20 .80
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4
gas/testsuite/gas/aarch64/cpa-addsub-bad.d
Normal file
4
gas/testsuite/gas/aarch64/cpa-addsub-bad.d
Normal file
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@ -0,0 +1,4 @@
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#name: Incorrect input test for CPA instructions ((M)ADDPT and (M)SUBPT).
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#as: -march=armv8-a+cpa
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#source: cpa-addsub-bad.s
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#error_output: cpa-addsub-bad.l
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50
gas/testsuite/gas/aarch64/cpa-addsub-bad.l
Normal file
50
gas/testsuite/gas/aarch64/cpa-addsub-bad.l
Normal file
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@ -0,0 +1,50 @@
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.*: Assembler messages:
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.*: Error: operand mismatch -- `addpt w5,w8,w0'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+addpt x5, x8, x0
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.*: Error: only 'LSL' shift is permitted at operand 3 -- `addpt x5,x8,x0,asr#6'
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.*: Error: shift amount out of range 0 to 7 at operand 3 -- `addpt x5,x8,x0,lsl#9'
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.*: Error: expected an integer or zero register at operand 3 -- `addpt x5,x8,sp,lsl#5'
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.*: Error: expected an integer or stack pointer register at operand 1 -- `addpt xzr,x8,x0,lsl#3'
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.*: Error: operand mismatch -- `subpt w5,w8,w0'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+subpt x5, x8, x0
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.*: Error: only 'LSL' shift is permitted at operand 3 -- `subpt x5,x8,x0,asr#6'
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.*: Error: shift amount out of range 0 to 7 at operand 3 -- `subpt x5,x8,x0,lsl#9'
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.*: Error: expected an integer or zero register at operand 3 -- `subpt x5,x8,sp,lsl#5'
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.*: Error: expected an integer or stack pointer register at operand 1 -- `subpt xzr,x8,x0,lsl#3'
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.*: Error: operand mismatch -- `maddpt w1,x2,x3,x4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+maddpt x1, x2, x3, x4
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.*: Error: operand mismatch -- `maddpt x1,w2,x3,x4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+maddpt x1, x2, x3, x4
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.*: Error: operand mismatch -- `maddpt x1,x2,w3,x4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+maddpt x1, x2, x3, x4
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.*: Error: operand mismatch -- `maddpt x1,x2,x3,w4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+maddpt x1, x2, x3, x4
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.*: Error: expected an integer or zero register at operand 1 -- `maddpt sp,x2,x3,x4'
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.*: Error: expected an integer or zero register at operand 2 -- `maddpt x1,sp,x3,x4'
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.*: Error: expected an integer or zero register at operand 3 -- `maddpt x1,x2,sp,x4'
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.*: Error: expected an integer or zero register at operand 4 -- `maddpt x1,x2,x3,sp'
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.*: Error: operand mismatch -- `msubpt w1,x2,x3,x4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+msubpt x1, x2, x3, x4
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.*: Error: operand mismatch -- `msubpt x1,w2,x3,x4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+msubpt x1, x2, x3, x4
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.*: Error: operand mismatch -- `msubpt x1,x2,w3,x4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+msubpt x1, x2, x3, x4
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.*: Error: operand mismatch -- `msubpt x1,x2,x3,w4'
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.*: Info:\s+did you mean this\?
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.*: Info:\s+msubpt x1, x2, x3, x4
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.*: Error: expected an integer or zero register at operand 1 -- `msubpt sp,x2,x3,x4'
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.*: Error: expected an integer or zero register at operand 2 -- `msubpt x1,sp,x3,x4'
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.*: Error: expected an integer or zero register at operand 3 -- `msubpt x1,x2,sp,x4'
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.*: Error: expected an integer or zero register at operand 4 -- `msubpt x1,x2,x3,sp'
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29
gas/testsuite/gas/aarch64/cpa-addsub-bad.s
Normal file
29
gas/testsuite/gas/aarch64/cpa-addsub-bad.s
Normal file
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@ -0,0 +1,29 @@
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addpt w5, w8, w0
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addpt x5, x8, x0, asr #6
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addpt x5, x8, x0, lsl #9
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addpt x5, x8, sp, lsl #5
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addpt xzr, x8, x0, lsl #3
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subpt w5, w8, w0
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subpt x5, x8, x0, asr #6
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subpt x5, x8, x0, lsl #9
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subpt x5, x8, sp, lsl #5
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subpt xzr, x8, x0, lsl #3
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maddpt w1, x2, x3, x4
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maddpt x1, w2, x3, x4
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maddpt x1, x2, w3, x4
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maddpt x1, x2, x3, w4
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maddpt sp, x2, x3, x4
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maddpt x1, sp, x3, x4
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maddpt x1, x2, sp, x4
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maddpt x1, x2, x3, sp
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msubpt w1, x2, x3, x4
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msubpt x1, w2, x3, x4
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msubpt x1, x2, w3, x4
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msubpt x1, x2, x3, w4
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msubpt sp, x2, x3, x4
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msubpt x1, sp, x3, x4
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msubpt x1, x2, sp, x4
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msubpt x1, x2, x3, sp
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5
gas/testsuite/gas/aarch64/cpa-addsub-neg.d
Normal file
5
gas/testsuite/gas/aarch64/cpa-addsub-neg.d
Normal file
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@ -0,0 +1,5 @@
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#name: Negative test for CPA instructions ((M)ADDPT and (M)SUBPT).
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#as: -march=armv8-a
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#as: -march=armv9-a
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#source: cpa-addsub.s
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#error_output: cpa-addsub-neg.l
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27
gas/testsuite/gas/aarch64/cpa-addsub-neg.l
Normal file
27
gas/testsuite/gas/aarch64/cpa-addsub-neg.l
Normal file
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@ -0,0 +1,27 @@
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.*: Assembler messages:
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.*: Error: selected processor does not support `addpt x0,x0,x0'
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.*: Error: selected processor does not support `addpt sp,x0,x0'
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.*: Error: selected processor does not support `addpt x0,sp,x0'
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.*: Error: selected processor does not support `addpt x0,x0,xzr'
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.*: Error: selected processor does not support `addpt x0,x0,x0,lsl#0'
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.*: Error: selected processor does not support `addpt x0,x0,x0,lsl#7'
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.*: Error: selected processor does not support `addpt x8,x13,x29,lsl#5'
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.*: Error: selected processor does not support `subpt x0,x0,x0'
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.*: Error: selected processor does not support `subpt sp,x0,x0'
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.*: Error: selected processor does not support `subpt x0,sp,x0'
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.*: Error: selected processor does not support `subpt x0,x0,xzr'
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.*: Error: selected processor does not support `subpt x0,x0,x0,lsl#0'
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.*: Error: selected processor does not support `subpt x0,x0,x0,lsl#7'
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.*: Error: selected processor does not support `subpt x1,x10,x22,lsl#2'
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.*: Error: selected processor does not support `maddpt x0,x0,x0,x0'
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.*: Error: selected processor does not support `maddpt xzr,x0,x0,x0'
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.*: Error: selected processor does not support `maddpt x0,xzr,x0,x0'
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.*: Error: selected processor does not support `maddpt x0,x0,xzr,x0'
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.*: Error: selected processor does not support `maddpt x0,x0,x0,xzr'
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.*: Error: selected processor does not support `maddpt x19,x10,x1,x28'
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.*: Error: selected processor does not support `msubpt x0,x0,x0,x0'
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.*: Error: selected processor does not support `msubpt xzr,x0,x0,x0'
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.*: Error: selected processor does not support `msubpt x0,xzr,x0,x0'
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.*: Error: selected processor does not support `msubpt x0,x0,xzr,x0'
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.*: Error: selected processor does not support `msubpt x0,x0,x0,xzr'
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.*: Error: selected processor does not support `msubpt x4,x13,x9,x21'
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39
gas/testsuite/gas/aarch64/cpa-addsub.d
Normal file
39
gas/testsuite/gas/aarch64/cpa-addsub.d
Normal file
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@ -0,0 +1,39 @@
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#name: Tests for CPA instructions ((M)ADDPT and (M)SUBPT).
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#as: -march=armv8-a+cpa
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#objdump: -dr
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[^:]+: file format .*
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[^:]+:
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[^:]+:
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.*: 9a002000 addpt x0, x0, x0
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.*: 9a00201f addpt sp, x0, x0
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.*: 9a0023e0 addpt x0, sp, x0
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.*: 9a1f2000 addpt x0, x0, xzr
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.*: 9a002000 addpt x0, x0, x0
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.*: 9a003c00 addpt x0, x0, x0, lsl #7
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.*: 9a1d35a8 addpt x8, x13, x29, lsl #5
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.*: da002000 subpt x0, x0, x0
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.*: da00201f subpt sp, x0, x0
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.*: da0023e0 subpt x0, sp, x0
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.*: da1f2000 subpt x0, x0, xzr
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.*: da002000 subpt x0, x0, x0
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.*: da003c00 subpt x0, x0, x0, lsl #7
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.*: da162941 subpt x1, x10, x22, lsl #2
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.*: 9b600000 maddpt x0, x0, x0, x0
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.*: 9b60001f maddpt xzr, x0, x0, x0
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.*: 9b6003e0 maddpt x0, xzr, x0, x0
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.*: 9b7f0000 maddpt x0, x0, xzr, x0
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.*: 9b607c00 maddpt x0, x0, x0, xzr
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.*: 9b617153 maddpt x19, x10, x1, x28
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.*: 9b608000 msubpt x0, x0, x0, x0
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.*: 9b60801f msubpt xzr, x0, x0, x0
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.*: 9b6083e0 msubpt x0, xzr, x0, x0
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.*: 9b7f8000 msubpt x0, x0, xzr, x0
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.*: 9b60fc00 msubpt x0, x0, x0, xzr
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.*: 9b69d5a4 msubpt x4, x13, x9, x21
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29
gas/testsuite/gas/aarch64/cpa-addsub.s
Normal file
29
gas/testsuite/gas/aarch64/cpa-addsub.s
Normal file
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@ -0,0 +1,29 @@
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addpt x0, x0, x0
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addpt sp, x0, x0
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addpt x0, sp, x0
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addpt x0, x0, xzr
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addpt x0, x0, x0, lsl #0
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addpt x0, x0, x0, lsl #7
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addpt x8, x13, x29, lsl #5
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subpt x0, x0, x0
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subpt sp, x0, x0
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subpt x0, sp, x0
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subpt x0, x0, xzr
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subpt x0, x0, x0, lsl #0
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subpt x0, x0, x0, lsl #7
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subpt x1, x10, x22, lsl #2
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maddpt x0, x0, x0, x0
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maddpt xzr, x0, x0, x0
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maddpt x0, xzr, x0, x0
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maddpt x0, x0, xzr, x0
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maddpt x0, x0, x0, xzr
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maddpt x19, x10, x1, x28
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msubpt x0, x0, x0, x0
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msubpt xzr, x0, x0, x0
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msubpt x0, xzr, x0, x0
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msubpt x0, x0, xzr, x0
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msubpt x0, x0, x0, xzr
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msubpt x4, x13, x9, x21
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@ -228,6 +228,8 @@ enum aarch64_feature_bit {
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AARCH64_FEATURE_SVE2p1,
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/* RCPC3 instructions. */
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AARCH64_FEATURE_RCPC3,
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/* Checked Pointer Arithmetic instructions. */
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AARCH64_FEATURE_CPA,
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AARCH64_NUM_FEATURES
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};
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@ -490,6 +492,7 @@ enum aarch64_opnd
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AARCH64_OPND_PAIRREG_OR_XZR, /* Paired register operand, optionally xzr. */
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AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
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AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
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AARCH64_OPND_Rm_LSL, /* Integer Rm shifted (LSL-only). */
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AARCH64_OPND_Fd, /* Floating-point Fd. */
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AARCH64_OPND_Fn, /* Floating-point Fn. */
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@ -1020,6 +1020,21 @@ aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
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return true;
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}
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/* Encode the LSL-shifted register operand for e.g.
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ADDPT <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>}. */
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bool
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aarch64_ins_reg_lsl_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
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const aarch64_opnd_info *info, aarch64_insn *code,
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const aarch64_inst *inst ATTRIBUTE_UNUSED,
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aarch64_operand_error *errors ATTRIBUTE_UNUSED)
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{
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/* Rm */
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insert_field (FLD_Rm, code, info->reg.regno, 0);
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/* imm3 */
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insert_field (FLD_imm3_10, code, info->shifter.amount, 0);
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return true;
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}
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/* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
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where <simm4> is a 4-bit signed value and where <factor> is 1 plus
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SELF's operand-dependent value. fields[0] specifies the field that
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@ -75,6 +75,7 @@ AARCH64_DECL_OPD_INSERTER (ins_hint);
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AARCH64_DECL_OPD_INSERTER (ins_prfop);
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AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
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AARCH64_DECL_OPD_INSERTER (ins_reg_shifted);
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AARCH64_DECL_OPD_INSERTER (ins_reg_lsl_shifted);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s4xvl);
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AARCH64_DECL_OPD_INSERTER (ins_sve_addr_ri_s6xvl);
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@ -1526,6 +1526,23 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
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return true;
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}
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/* Decode the LSL-shifted register operand for e.g.
|
||||
ADDPT <Xd|SP>, <Xn|SP>, <Xm>{, LSL #<amount>}. */
|
||||
bool
|
||||
aarch64_ext_reg_lsl_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
|
||||
aarch64_opnd_info *info,
|
||||
aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
/* Rm */
|
||||
info->reg.regno = extract_field (FLD_Rm, code, 0);
|
||||
/* imm3 */
|
||||
info->shifter.kind = AARCH64_MOD_LSL;
|
||||
info->shifter.amount = extract_field (FLD_imm3_10, code, 0);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
|
||||
where <offset> is given by the OFFSET parameter and where <factor> is
|
||||
1 plus SELF's operand-dependent value. fields[0] specifies the field
|
||||
|
|
|
|||
|
|
@ -99,6 +99,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
|
|||
AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_shifted);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_reg_lsl_shifted);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s4xvl);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_addr_ri_s6xvl);
|
||||
|
|
|
|||
|
|
@ -3270,6 +3270,17 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_Rm_LSL:
|
||||
/* We expect here that opnd->shifter.kind != AARCH64_MOD_LSL
|
||||
because the parser already restricts the type of shift to LSL only,
|
||||
so another check of shift kind would be redundant. */
|
||||
if (!value_in_range_p (opnd->shifter.amount, 0, 7))
|
||||
{
|
||||
set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 7);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
|
@ -4005,6 +4016,20 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_Rm_LSL:
|
||||
assert (opnd->qualifier == AARCH64_OPND_QLF_X);
|
||||
assert (opnd->shifter.kind == AARCH64_MOD_LSL);
|
||||
if (opnd->shifter.amount == 0)
|
||||
snprintf (buf, size, "%s",
|
||||
style_reg (styler, get_int_reg_name (opnd->reg.regno,
|
||||
opnd->qualifier, 0)));
|
||||
else
|
||||
snprintf (buf, size, "%s, %s %s",
|
||||
style_reg (styler, get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0)),
|
||||
style_sub_mnem (styler, aarch64_operand_modifiers[opnd->shifter.kind].name),
|
||||
style_imm (styler, "#%" PRIi64, opnd->shifter.amount));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_Fd:
|
||||
case AARCH64_OPND_Fn:
|
||||
case AARCH64_OPND_Fm:
|
||||
|
|
|
|||
|
|
@ -240,6 +240,12 @@
|
|||
QLF4(X,X,X,X), \
|
||||
}
|
||||
|
||||
/* e.g. MADDPT <Xd>, <Xn>, <Xm>, <Xa>. */
|
||||
#define QL_I4SAMEX \
|
||||
{ \
|
||||
QLF4(X,X,X,X), \
|
||||
}
|
||||
|
||||
/* e.g. SMADDL <Xd>, <Wn>, <Wm>, <Xa>. */
|
||||
#define QL_I3SAMEL \
|
||||
{ \
|
||||
|
|
@ -2649,7 +2655,8 @@ static const aarch64_feature_set aarch64_feature_sve2p1 =
|
|||
AARCH64_FEATURE (SVE2p1);
|
||||
static const aarch64_feature_set aarch64_feature_rcpc3 =
|
||||
AARCH64_FEATURE (RCPC3);
|
||||
|
||||
static const aarch64_feature_set aarch64_feature_cpa =
|
||||
AARCH64_FEATURE (CPA);
|
||||
|
||||
#define CORE &aarch64_feature_v8
|
||||
#define FP &aarch64_feature_fp
|
||||
|
|
@ -2716,6 +2723,7 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
|
|||
#define SME2p1 &aarch64_feature_sme2p1
|
||||
#define SVE2p1 &aarch64_feature_sve2p1
|
||||
#define RCPC3 &aarch64_feature_rcpc3
|
||||
#define CPA &aarch64_feature_cpa
|
||||
|
||||
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
|
|
@ -2888,6 +2896,8 @@ static const aarch64_feature_set aarch64_feature_rcpc3 =
|
|||
{ NAME, OPCODE, MASK, the, 0, D128_THE, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define RCPC3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, RCPC3, OPS, QUALS, FLAGS, 0, 0, NULL }
|
||||
#define CPA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS) \
|
||||
{ NAME, OPCODE, MASK, CLASS, 0, CPA, OPS, QUALS, 0, 0, 0, NULL }
|
||||
|
||||
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
|
||||
MOPS_INSN (NAME, OPCODE, MASK, 0, \
|
||||
|
|
@ -6392,6 +6402,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
SVE2p1_INSNC("st3q",0xe4a00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt3, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
|
||||
SVE2p1_INSNC("st4q",0xe4e00000, 0xffe0e000, sve_misc, 0, OP3 (SME_Zt4, SVE_Pg3, SVE_ADDR_RR_LSL4), OP_SVE_QUU, 0, C_SCAN_MOVPRFX, 0),
|
||||
|
||||
/* Checked Pointer Arithmetic Instructions. */
|
||||
CPA_INSN ("addpt", 0x9a002000, 0xffe0e000, aarch64_misc, OP3 (Rd_SP, Rn_SP, Rm_LSL), QL_I3SAMEX),
|
||||
CPA_INSN ("subpt", 0xda002000, 0xffe0e000, aarch64_misc, OP3 (Rd_SP, Rn_SP, Rm_LSL), QL_I3SAMEX),
|
||||
CPA_INSN ("maddpt", 0x9b600000, 0xffe08000, aarch64_misc, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEX),
|
||||
CPA_INSN ("msubpt", 0x9b608000, 0xffe08000, aarch64_misc, OP4 (Rd, Rn, Rm, Ra), QL_I4SAMEX),
|
||||
|
||||
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
|
||||
};
|
||||
|
||||
|
|
@ -6440,6 +6456,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
"an integer register with optional extension") \
|
||||
Y(MODIFIED_REG, reg_shifted, "Rm_SFT", 0, F(), \
|
||||
"an integer register with optional shift") \
|
||||
Y(MODIFIED_REG, reg_lsl_shifted, "Rm_LSL", 0, F(), \
|
||||
"an integer register with optional LSL shift") \
|
||||
Y(FP_REG, regno, "Fd", 0, F(FLD_Rd), "a floating-point register") \
|
||||
Y(FP_REG, regno, "Fn", 0, F(FLD_Rn), "a floating-point register") \
|
||||
Y(FP_REG, regno, "Fm", 0, F(FLD_Rm), "a floating-point register") \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue