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RISC-V: Change CALL macro to use ra as the temporary address register

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e.g.

    1:  auipc ra, %pcrel_hi(symbol)
        jalr  ra, %pcrel_lo(1b)(ra)

The use of ra instead of t1 for address construction provides an
opportunity for a microarchitecture to elide the write of the
destination address, and instead read the target address as an
immediate spread across the fused auipc+jalr pair. The link
register ra in the jalr overwrites the target address temporary.

2017-05-01  Michael Clark  <michaeljclark@mac.com>

	* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
	register.
This commit is contained in:
Michael Clark 2017-04-27 16:08:46 +12:00 • committed by Palmer Dabbelt
parent 763a5fa4f3
commit 43e379d74c
2 changed files with 6 additions and 1 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2017-05-01 Michael Clark <michaeljclark@mac.com>
* riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
register.
2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps

2
opcodes/riscv-opc.c
View file

@ -147,7 +147,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"jal", "32C", "Ca", MATCH_C_JAL, MASK_C_JAL, match_opcode, INSN_ALIAS },
{"jal", "I", "a", MATCH_JAL | (X_RA << OP_SH_RD), MASK_JAL | MASK_RD, match_opcode, INSN_ALIAS },
{"call", "I", "d,c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
{"call", "I", "c", (X_T1 << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
{"call", "I", "c", (X_RA << OP_SH_RS1) | (X_RA << OP_SH_RD), (int) M_CALL, match_never, INSN_MACRO },
{"tail", "I", "c", (X_T1 << OP_SH_RS1), (int) M_CALL, match_never, INSN_MACRO },
{"jump", "I", "c,s", 0, (int) M_CALL, match_never, INSN_MACRO },
{"nop", "C", "", MATCH_C_ADDI, 0xffff, match_opcode, INSN_ALIAS },