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Pass noaliases_p to aarch64_decode_insn

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Nowadays aarch64_decode_insn is a public interface used by both
opcodes and gdb.  However, its behaviour relies on a global variable
no_aliases, which isn't a good practise.  On the other hand, In default,
no_aliases is zero, but in GDB, we do want no alias when decoding
instructions for prologue analysis (patches to be posted), so that we
can handle both instructions "add" and "mov" (an alias of "add") as
"add".  The code in GDB can be simplified.

This patch adds a new argument in aarch64_decode_insn, and pass no_aliases
to it.  In GDB side, always pass 1 to it.

include/opcode:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64.h (aarch64_decode_insn): Update declaration.

opcodes:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-dis.c	(aarch64_decode_insn): Add one argument
	noaliases_p.  Update comments.  Pass noaliases_p rather than
	no_aliases to aarch64_opcode_decode.
	(print_insn_aarch64_word): Pass no_aliases to
	aarch64_decode_insn.

gdb:

2015-10-28  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
	aarch64_decode_insn.
This commit is contained in:
Yao Qi 2015-10-05 11:15:58 +01:00
parent 82188b295d
commit 43cdf5aeb8
6 changed files with 27 additions and 8 deletions
Download patch file Download diff file Expand all files Collapse all files

5
gdb/ChangeLog
View file

@ -1,3 +1,8 @@
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_software_single_step): Pass 1 to
aarch64_decode_insn.
2015-10-27 Pedro Alves <palves@redhat.com> 2015-10-27 Pedro Alves <palves@redhat.com>
* common/print-utils.c (host_address_to_string): Rename to ... * common/print-utils.c (host_address_to_string): Rename to ...

4
gdb/aarch64-tdep.c
View file

@ -2499,7 +2499,7 @@ aarch64_software_single_step (struct frame_info *frame)
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
aarch64_inst inst; aarch64_inst inst;
if (aarch64_decode_insn (insn, &inst) != 0) if (aarch64_decode_insn (insn, &inst, 1) != 0)
return 0; return 0;
/* Look for a Load Exclusive instruction which begins the sequence. */ /* Look for a Load Exclusive instruction which begins the sequence. */
@ -2512,7 +2512,7 @@ aarch64_software_single_step (struct frame_info *frame)
insn = read_memory_unsigned_integer (loc, insn_size, insn = read_memory_unsigned_integer (loc, insn_size,
byte_order_for_code); byte_order_for_code);
if (aarch64_decode_insn (insn, &inst) != 0) if (aarch64_decode_insn (insn, &inst, 1) != 0)
return 0; return 0;
/* Check if the instruction is a conditional branch. */ /* Check if the instruction is a conditional branch. */
if (inst.opcode->iclass == condbranch) if (inst.opcode->iclass == condbranch)

4
include/opcode/ChangeLog
View file

@ -1,3 +1,7 @@
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_decode_insn): Update declaration.
2015-10-07 Yao Qi <yao.qi@linaro.org> 2015-10-07 Yao Qi <yao.qi@linaro.org>
* aarch64.h (aarch64_sys_ins_reg) <template>: Removed. * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.

2
include/opcode/aarch64.h
View file

@ -930,7 +930,7 @@ extern int
aarch64_zero_register_p (const aarch64_opnd_info *); aarch64_zero_register_p (const aarch64_opnd_info *);
extern int extern int
aarch64_decode_insn (aarch64_insn, aarch64_inst *); aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
/* Given an operand qualifier, return the expected data element size /* Given an operand qualifier, return the expected data element size
of a qualified operand. */ of a qualified operand. */

8
opcodes/ChangeLog
View file

@ -1,3 +1,11 @@
2015-10-28 Yao Qi <yao.qi@linaro.org>
* aarch64-dis.c (aarch64_decode_insn): Add one argument
noaliases_p. Update comments. Pass noaliases_p rather than
no_aliases to aarch64_opcode_decode.
(print_insn_aarch64_word): Pass no_aliases to
aarch64_decode_insn.
2015-10-27 Vinay <Vinay.G@kpit.com> 2015-10-27 Vinay <Vinay.G@kpit.com>
PR binutils/19159 PR binutils/19159

12
opcodes/aarch64-dis.c
View file

@ -2029,11 +2029,13 @@ user_friendly_fixup (aarch64_inst *inst)
} }
} }
/* Decode INSN and fill in *INST the instruction information. Return zero /* Decode INSN and fill in *INST the instruction information. An alias
on success. */ opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
success. */
int int
aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst) aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
bfd_boolean noaliases_p)
{ {
const aarch64_opcode *opcode = aarch64_opcode_lookup (insn); const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
@ -2060,7 +2062,7 @@ aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst)
{ {
/* But only one opcode can be decoded successfully for, as the /* But only one opcode can be decoded successfully for, as the
decoding routine will check the constraint carefully. */ decoding routine will check the constraint carefully. */
if (aarch64_opcode_decode (opcode, insn, inst, no_aliases) == 1) if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p) == 1)
return ERR_OK; return ERR_OK;
opcode = aarch64_find_next_opcode (opcode); opcode = aarch64_find_next_opcode (opcode);
} }
@ -2172,7 +2174,7 @@ print_insn_aarch64_word (bfd_vma pc,
addresses, since the addend is not currently pc-relative. */ addresses, since the addend is not currently pc-relative. */
pc = 0; pc = 0;
ret = aarch64_decode_insn (word, &inst); ret = aarch64_decode_insn (word, &inst, no_aliases);
if (((word >> 21) & 0x3ff) == 1) if (((word >> 21) & 0x3ff) == 1)
{ {