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gdb/riscv: Partial support for instructions up to 176-bit

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Because riscv_insn_length started to support instructions up to 176-bit,
we need to increase buf size to 176-bit in size.

Also, that would break an assumption in riscv_insn::decode so this commit
fixes it, noting that instructions longer than 64-bit are not fully
supported yet.
This commit is contained in:
Tsukasa OI 2022-10-04 08:42:35 +00:00
parent 73e30e726c
commit 436a7b5ef2
1 changed files with 5 additions and 4 deletions
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9
gdb/riscv-tdep.c
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@ -1770,7 +1770,7 @@ riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
CORE_ADDR addr, int *len)
{
enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
gdb_byte buf[8];
gdb_byte buf[RISCV_MAX_INSN_LEN];
int instlen, status;
/* All insns are at least 16 bits. */
@ -1933,9 +1933,10 @@ riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
}
else
{
/* This must be a 6 or 8 byte instruction, we don't currently decode
any of these, so just ignore it. */
gdb_assert (m_length == 6 || m_length == 8);
/* 6 bytes or more. If the instruction is longer than 8 bytes, we don't
have full instruction bits in ival. At least, such long instructions
are not defined yet, so just ignore it. */
gdb_assert (m_length > 0 && m_length % 2 == 0);
m_opcode = OTHER;
}
}