FreeChainXenon/binutils-gdb
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

[AArch64][PATCH 1/14] Support ARMv8.2 FP16 Adv.SIMD instructions.

Browse source 
ARMv8.2 adds 16-bit floating point operations as an optional extension
to floating point and Adv.SIMD support. This patch set adds the 16-bit
Adv.SIMD vector and scalar instructions to binutils, making them
available when both +simd and +fp16 architecture extensions are enabled.
The series also adds support for a new vector type, 2H, used by the FP16
scalar pairwise instructions.

The patches in this series:
- Add a FP16 Adv.SIMD feature macro for use by the encoding/decoding
  routines.
- Add FP16 instructions in the group Vector Three Register Same.
- Add FP16 instructions in the group Scalar Three Register Same.
- Add FP16 instructions in the group Vector Two Register Misc.
- Add FP16 instructions in the group Scalar Two Register Misc.
- Add FP16 instructions in the group Vector Indexed Element.
- Add FP16 instructions in the group Scalar Indexed Element.
- Add FP16 instructions in the group Adv.SIMD Across Lanes.
- Add FP16 instructions in the group Adv.SIMD Modified Immediate.
- Rework some code for handling vector types to weaken its assumptions
  about available vector-types.
- Add support for the 2H vector type.
- Add FP16 instructions in the group Adv.SIMD Scalar Pairwise.
- Add FP16 instructions in the group Adv.SIMD Shift By Immediate.
- Add a FP16 instructions in the group Adv.SIMD Scalar Shift By
  Immediate.

This patch adds the feature macro SIMD_F16 to the AArch64
encoding/decoding routines. It is used to decide when the new
instructions are available to the assembler and is true when both +simd
and +fp16 are selected.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_simd_f16): New.
	(SIMD_F16): New.

Change-Id: Iee5a37928418f15e51dfaa927b24cafef7295e8f
This commit is contained in:
Matthew Wahab 2015-12-14 16:34:47 +00:00
parent 6351190792
commit 40d16a76c7
2 changed files with 8 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

5
opcodes/ChangeLog
View file

@ -1,3 +1,8 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_simd_f16): New.
(SIMD_F16): New.
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly

3
opcodes/aarch64-tbl.h
View file

@ -1303,6 +1303,8 @@ static const aarch64_feature_set aarch64_feature_v8_2 =
AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
static const aarch64_feature_set aarch64_feature_fp_f16 =
AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
static const aarch64_feature_set aarch64_feature_simd_f16 =
AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
static const aarch64_feature_set aarch64_feature_stat_profile =
AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
@ -1315,6 +1317,7 @@ static const aarch64_feature_set aarch64_feature_stat_profile =
#define LOR &aarch64_feature_lor
#define RDMA &aarch64_feature_rdma
#define FP_F16 &aarch64_feature_fp_f16
#define SIMD_F16 &aarch64_feature_simd_f16
#define RAS &aarch64_feature_ras
#define STAT_PROFILE &aarch64_feature_stat_profile
#define ARMV8_2 &aarch64_feature_v8_2