* sem-switch.c: Regenerate. Redo computed goto label handling.
* sem.c: Regenerate. Call PROFILE_COUNT_INSN. * readx.c: Regenerate. Redo computed goto label handling. * semx.c: Regenerate. Call PROFILE_COUNT_INSN. Finish profiling support. * Makefile.in (stamp-xcpu): Turn on profiling support.
This commit is contained in:
Doug Evans
parent
177dedfb88
commit
40c680ba80
2 changed files with 631 additions and 248 deletions
256
sim/m32r/readx.c
256
sim/m32r/readx.c
|
|
@ -27,138 +27,138 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
||||||
|
|
||||||
/* The labels have the case they have because the enum of insn types
|
/* The labels have the case they have because the enum of insn types
|
||||||
is all uppercase and in the non-stdc case the fmt symbol is built
|
is all uppercase and in the non-stdc case the fmt symbol is built
|
||||||
into the enum name.
|
into the enum name. */
|
||||||
|
|
||||||
The order here must match the order in m32rx_decode_vars in decode.c. */
|
static struct {
|
||||||
|
int index;
|
||||||
static void *labels[] = {
|
void *label;
|
||||||
&& case_read_READ_ILLEGAL,
|
} labels[] = {
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_ILLEGAL, && case_read_READ_ILLEGAL },
|
||||||
&& case_read_READ_FMT_ADD3,
|
{ M32RX_XINSN_ADD, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_ADD3, && case_read_READ_FMT_ADD3 },
|
||||||
&& case_read_READ_FMT_AND3,
|
{ M32RX_XINSN_AND, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_AND3, && case_read_READ_FMT_AND3 },
|
||||||
&& case_read_READ_FMT_OR3,
|
{ M32RX_XINSN_OR, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_OR3, && case_read_READ_FMT_OR3 },
|
||||||
&& case_read_READ_FMT_AND3,
|
{ M32RX_XINSN_XOR, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_ADDI,
|
{ M32RX_XINSN_XOR3, && case_read_READ_FMT_AND3 },
|
||||||
&& case_read_READ_FMT_ADDV,
|
{ M32RX_XINSN_ADDI, && case_read_READ_FMT_ADDI },
|
||||||
&& case_read_READ_FMT_ADDV3,
|
{ M32RX_XINSN_ADDV, && case_read_READ_FMT_ADDV },
|
||||||
&& case_read_READ_FMT_ADDX,
|
{ M32RX_XINSN_ADDV3, && case_read_READ_FMT_ADDV3 },
|
||||||
&& case_read_READ_FMT_BC8,
|
{ M32RX_XINSN_ADDX, && case_read_READ_FMT_ADDX },
|
||||||
&& case_read_READ_FMT_BC24,
|
{ M32RX_XINSN_BC8, && case_read_READ_FMT_BC8 },
|
||||||
&& case_read_READ_FMT_BEQ,
|
{ M32RX_XINSN_BC24, && case_read_READ_FMT_BC24 },
|
||||||
&& case_read_READ_FMT_BEQZ,
|
{ M32RX_XINSN_BEQ, && case_read_READ_FMT_BEQ },
|
||||||
&& case_read_READ_FMT_BEQZ,
|
{ M32RX_XINSN_BEQZ, && case_read_READ_FMT_BEQZ },
|
||||||
&& case_read_READ_FMT_BEQZ,
|
{ M32RX_XINSN_BGEZ, && case_read_READ_FMT_BEQZ },
|
||||||
&& case_read_READ_FMT_BEQZ,
|
{ M32RX_XINSN_BGTZ, && case_read_READ_FMT_BEQZ },
|
||||||
&& case_read_READ_FMT_BEQZ,
|
{ M32RX_XINSN_BLEZ, && case_read_READ_FMT_BEQZ },
|
||||||
&& case_read_READ_FMT_BEQZ,
|
{ M32RX_XINSN_BLTZ, && case_read_READ_FMT_BEQZ },
|
||||||
&& case_read_READ_FMT_BL8,
|
{ M32RX_XINSN_BNEZ, && case_read_READ_FMT_BEQZ },
|
||||||
&& case_read_READ_FMT_BL24,
|
{ M32RX_XINSN_BL8, && case_read_READ_FMT_BL8 },
|
||||||
&& case_read_READ_FMT_BCL8,
|
{ M32RX_XINSN_BL24, && case_read_READ_FMT_BL24 },
|
||||||
&& case_read_READ_FMT_BCL24,
|
{ M32RX_XINSN_BCL8, && case_read_READ_FMT_BCL8 },
|
||||||
&& case_read_READ_FMT_BC8,
|
{ M32RX_XINSN_BCL24, && case_read_READ_FMT_BCL24 },
|
||||||
&& case_read_READ_FMT_BC24,
|
{ M32RX_XINSN_BNC8, && case_read_READ_FMT_BC8 },
|
||||||
&& case_read_READ_FMT_BEQ,
|
{ M32RX_XINSN_BNC24, && case_read_READ_FMT_BC24 },
|
||||||
&& case_read_READ_FMT_BRA8,
|
{ M32RX_XINSN_BNE, && case_read_READ_FMT_BEQ },
|
||||||
&& case_read_READ_FMT_BRA24,
|
{ M32RX_XINSN_BRA8, && case_read_READ_FMT_BRA8 },
|
||||||
&& case_read_READ_FMT_BCL8,
|
{ M32RX_XINSN_BRA24, && case_read_READ_FMT_BRA24 },
|
||||||
&& case_read_READ_FMT_BCL24,
|
{ M32RX_XINSN_BNCL8, && case_read_READ_FMT_BCL8 },
|
||||||
&& case_read_READ_FMT_CMP,
|
{ M32RX_XINSN_BNCL24, && case_read_READ_FMT_BCL24 },
|
||||||
&& case_read_READ_FMT_CMPI,
|
{ M32RX_XINSN_CMP, && case_read_READ_FMT_CMP },
|
||||||
&& case_read_READ_FMT_CMP,
|
{ M32RX_XINSN_CMPI, && case_read_READ_FMT_CMPI },
|
||||||
&& case_read_READ_FMT_CMPI,
|
{ M32RX_XINSN_CMPU, && case_read_READ_FMT_CMP },
|
||||||
&& case_read_READ_FMT_CMP,
|
{ M32RX_XINSN_CMPUI, && case_read_READ_FMT_CMPI },
|
||||||
&& case_read_READ_FMT_CMPZ,
|
{ M32RX_XINSN_CMPEQ, && case_read_READ_FMT_CMP },
|
||||||
&& case_read_READ_FMT_DIV,
|
{ M32RX_XINSN_CMPZ, && case_read_READ_FMT_CMPZ },
|
||||||
&& case_read_READ_FMT_DIV,
|
{ M32RX_XINSN_DIV, && case_read_READ_FMT_DIV },
|
||||||
&& case_read_READ_FMT_DIV,
|
{ M32RX_XINSN_DIVU, && case_read_READ_FMT_DIV },
|
||||||
&& case_read_READ_FMT_DIV,
|
{ M32RX_XINSN_REM, && case_read_READ_FMT_DIV },
|
||||||
&& case_read_READ_FMT_DIV,
|
{ M32RX_XINSN_REMU, && case_read_READ_FMT_DIV },
|
||||||
&& case_read_READ_FMT_JC,
|
{ M32RX_XINSN_DIVH, && case_read_READ_FMT_DIV },
|
||||||
&& case_read_READ_FMT_JC,
|
{ M32RX_XINSN_JC, && case_read_READ_FMT_JC },
|
||||||
&& case_read_READ_FMT_JL,
|
{ M32RX_XINSN_JNC, && case_read_READ_FMT_JC },
|
||||||
&& case_read_READ_FMT_JMP,
|
{ M32RX_XINSN_JL, && case_read_READ_FMT_JL },
|
||||||
&& case_read_READ_FMT_LD,
|
{ M32RX_XINSN_JMP, && case_read_READ_FMT_JMP },
|
||||||
&& case_read_READ_FMT_LD_D,
|
{ M32RX_XINSN_LD, && case_read_READ_FMT_LD },
|
||||||
&& case_read_READ_FMT_LDB,
|
{ M32RX_XINSN_LD_D, && case_read_READ_FMT_LD_D },
|
||||||
&& case_read_READ_FMT_LDB_D,
|
{ M32RX_XINSN_LDB, && case_read_READ_FMT_LDB },
|
||||||
&& case_read_READ_FMT_LDH,
|
{ M32RX_XINSN_LDB_D, && case_read_READ_FMT_LDB_D },
|
||||||
&& case_read_READ_FMT_LDH_D,
|
{ M32RX_XINSN_LDH, && case_read_READ_FMT_LDH },
|
||||||
&& case_read_READ_FMT_LDB,
|
{ M32RX_XINSN_LDH_D, && case_read_READ_FMT_LDH_D },
|
||||||
&& case_read_READ_FMT_LDB_D,
|
{ M32RX_XINSN_LDUB, && case_read_READ_FMT_LDB },
|
||||||
&& case_read_READ_FMT_LDH,
|
{ M32RX_XINSN_LDUB_D, && case_read_READ_FMT_LDB_D },
|
||||||
&& case_read_READ_FMT_LDH_D,
|
{ M32RX_XINSN_LDUH, && case_read_READ_FMT_LDH },
|
||||||
&& case_read_READ_FMT_LD_PLUS,
|
{ M32RX_XINSN_LDUH_D, && case_read_READ_FMT_LDH_D },
|
||||||
&& case_read_READ_FMT_LD24,
|
{ M32RX_XINSN_LD_PLUS, && case_read_READ_FMT_LD_PLUS },
|
||||||
&& case_read_READ_FMT_LDI8,
|
{ M32RX_XINSN_LD24, && case_read_READ_FMT_LD24 },
|
||||||
&& case_read_READ_FMT_LDI16,
|
{ M32RX_XINSN_LDI8, && case_read_READ_FMT_LDI8 },
|
||||||
&& case_read_READ_FMT_LOCK,
|
{ M32RX_XINSN_LDI16, && case_read_READ_FMT_LDI16 },
|
||||||
&& case_read_READ_FMT_MACHI_A,
|
{ M32RX_XINSN_LOCK, && case_read_READ_FMT_LOCK },
|
||||||
&& case_read_READ_FMT_MACHI_A,
|
{ M32RX_XINSN_MACHI_A, && case_read_READ_FMT_MACHI_A },
|
||||||
&& case_read_READ_FMT_MACWHI,
|
{ M32RX_XINSN_MACLO_A, && case_read_READ_FMT_MACHI_A },
|
||||||
&& case_read_READ_FMT_MACWHI,
|
{ M32RX_XINSN_MACWHI, && case_read_READ_FMT_MACWHI },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_MACWLO, && case_read_READ_FMT_MACWHI },
|
||||||
&& case_read_READ_FMT_MULHI_A,
|
{ M32RX_XINSN_MUL, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_MULHI_A,
|
{ M32RX_XINSN_MULHI_A, && case_read_READ_FMT_MULHI_A },
|
||||||
&& case_read_READ_FMT_MULWHI,
|
{ M32RX_XINSN_MULLO_A, && case_read_READ_FMT_MULHI_A },
|
||||||
&& case_read_READ_FMT_MULWHI,
|
{ M32RX_XINSN_MULWHI, && case_read_READ_FMT_MULWHI },
|
||||||
&& case_read_READ_FMT_MV,
|
{ M32RX_XINSN_MULWLO, && case_read_READ_FMT_MULWHI },
|
||||||
&& case_read_READ_FMT_MVFACHI_A,
|
{ M32RX_XINSN_MV, && case_read_READ_FMT_MV },
|
||||||
&& case_read_READ_FMT_MVFACHI_A,
|
{ M32RX_XINSN_MVFACHI_A, && case_read_READ_FMT_MVFACHI_A },
|
||||||
&& case_read_READ_FMT_MVFACHI_A,
|
{ M32RX_XINSN_MVFACLO_A, && case_read_READ_FMT_MVFACHI_A },
|
||||||
&& case_read_READ_FMT_MVFC,
|
{ M32RX_XINSN_MVFACMI_A, && case_read_READ_FMT_MVFACHI_A },
|
||||||
&& case_read_READ_FMT_MVTACHI_A,
|
{ M32RX_XINSN_MVFC, && case_read_READ_FMT_MVFC },
|
||||||
&& case_read_READ_FMT_MVTACHI_A,
|
{ M32RX_XINSN_MVTACHI_A, && case_read_READ_FMT_MVTACHI_A },
|
||||||
&& case_read_READ_FMT_MVTC,
|
{ M32RX_XINSN_MVTACLO_A, && case_read_READ_FMT_MVTACHI_A },
|
||||||
&& case_read_READ_FMT_MV,
|
{ M32RX_XINSN_MVTC, && case_read_READ_FMT_MVTC },
|
||||||
&& case_read_READ_FMT_NOP,
|
{ M32RX_XINSN_NEG, && case_read_READ_FMT_MV },
|
||||||
&& case_read_READ_FMT_MV,
|
{ M32RX_XINSN_NOP, && case_read_READ_FMT_NOP },
|
||||||
&& case_read_READ_FMT_RAC_DSI,
|
{ M32RX_XINSN_NOT, && case_read_READ_FMT_MV },
|
||||||
&& case_read_READ_FMT_RAC_DSI,
|
{ M32RX_XINSN_RAC_DSI, && case_read_READ_FMT_RAC_DSI },
|
||||||
&& case_read_READ_FMT_RTE,
|
{ M32RX_XINSN_RACH_DSI, && case_read_READ_FMT_RAC_DSI },
|
||||||
&& case_read_READ_FMT_SETH,
|
{ M32RX_XINSN_RTE, && case_read_READ_FMT_RTE },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_SETH, && case_read_READ_FMT_SETH },
|
||||||
&& case_read_READ_FMT_SLL3,
|
{ M32RX_XINSN_SLL, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_SLLI,
|
{ M32RX_XINSN_SLL3, && case_read_READ_FMT_SLL3 },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_SLLI, && case_read_READ_FMT_SLLI },
|
||||||
&& case_read_READ_FMT_SLL3,
|
{ M32RX_XINSN_SRA, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_SLLI,
|
{ M32RX_XINSN_SRA3, && case_read_READ_FMT_SLL3 },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_SRAI, && case_read_READ_FMT_SLLI },
|
||||||
&& case_read_READ_FMT_SLL3,
|
{ M32RX_XINSN_SRL, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_SLLI,
|
{ M32RX_XINSN_SRL3, && case_read_READ_FMT_SLL3 },
|
||||||
&& case_read_READ_FMT_ST,
|
{ M32RX_XINSN_SRLI, && case_read_READ_FMT_SLLI },
|
||||||
&& case_read_READ_FMT_ST_D,
|
{ M32RX_XINSN_ST, && case_read_READ_FMT_ST },
|
||||||
&& case_read_READ_FMT_STB,
|
{ M32RX_XINSN_ST_D, && case_read_READ_FMT_ST_D },
|
||||||
&& case_read_READ_FMT_STB_D,
|
{ M32RX_XINSN_STB, && case_read_READ_FMT_STB },
|
||||||
&& case_read_READ_FMT_STH,
|
{ M32RX_XINSN_STB_D, && case_read_READ_FMT_STB_D },
|
||||||
&& case_read_READ_FMT_STH_D,
|
{ M32RX_XINSN_STH, && case_read_READ_FMT_STH },
|
||||||
&& case_read_READ_FMT_ST_PLUS,
|
{ M32RX_XINSN_STH_D, && case_read_READ_FMT_STH_D },
|
||||||
&& case_read_READ_FMT_ST_PLUS,
|
{ M32RX_XINSN_ST_PLUS, && case_read_READ_FMT_ST_PLUS },
|
||||||
&& case_read_READ_FMT_ADD,
|
{ M32RX_XINSN_ST_MINUS, && case_read_READ_FMT_ST_PLUS },
|
||||||
&& case_read_READ_FMT_ADDV,
|
{ M32RX_XINSN_SUB, && case_read_READ_FMT_ADD },
|
||||||
&& case_read_READ_FMT_ADDX,
|
{ M32RX_XINSN_SUBV, && case_read_READ_FMT_ADDV },
|
||||||
&& case_read_READ_FMT_TRAP,
|
{ M32RX_XINSN_SUBX, && case_read_READ_FMT_ADDX },
|
||||||
&& case_read_READ_FMT_UNLOCK,
|
{ M32RX_XINSN_TRAP, && case_read_READ_FMT_TRAP },
|
||||||
&& case_read_READ_FMT_SATB,
|
{ M32RX_XINSN_UNLOCK, && case_read_READ_FMT_UNLOCK },
|
||||||
&& case_read_READ_FMT_SATB,
|
{ M32RX_XINSN_SATB, && case_read_READ_FMT_SATB },
|
||||||
&& case_read_READ_FMT_SAT,
|
{ M32RX_XINSN_SATH, && case_read_READ_FMT_SATB },
|
||||||
&& case_read_READ_FMT_CMPZ,
|
{ M32RX_XINSN_SAT, && case_read_READ_FMT_SAT },
|
||||||
&& case_read_READ_FMT_SADD,
|
{ M32RX_XINSN_PCMPBZ, && case_read_READ_FMT_CMPZ },
|
||||||
&& case_read_READ_FMT_MACWU1,
|
{ M32RX_XINSN_SADD, && case_read_READ_FMT_SADD },
|
||||||
&& case_read_READ_FMT_MACWHI,
|
{ M32RX_XINSN_MACWU1, && case_read_READ_FMT_MACWU1 },
|
||||||
&& case_read_READ_FMT_MULWU1,
|
{ M32RX_XINSN_MSBLO, && case_read_READ_FMT_MACWHI },
|
||||||
&& case_read_READ_FMT_MACWU1,
|
{ M32RX_XINSN_MULWU1, && case_read_READ_FMT_MULWU1 },
|
||||||
&& case_read_READ_FMT_SC,
|
{ M32RX_XINSN_MACLH1, && case_read_READ_FMT_MACWU1 },
|
||||||
&& case_read_READ_FMT_SC,
|
{ M32RX_XINSN_SC, && case_read_READ_FMT_SC },
|
||||||
0
|
{ M32RX_XINSN_SNC, && case_read_READ_FMT_SC },
|
||||||
|
{ 0, 0 }
|
||||||
};
|
};
|
||||||
extern DECODE *m32rx_decode_vars[];
|
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for (i = 0; m32rx_decode_vars[i] != 0; ++i)
|
for (i = 0; labels[i].label != 0; ++i)
|
||||||
m32rx_decode_vars[i]->read = labels[i];
|
CPU_IDESC (current_cpu) [labels[i].index].read = labels[i].label;
|
||||||
|
|
||||||
#endif /* DEFINE_LABELS */
|
#endif /* DEFINE_LABELS */
|
||||||
|
|
||||||
|
|
|
||||||
623
sim/m32r/semx.c
623
sim/m32r/semx.c
File diff suppressed because it is too large
Load diff
Loading…
Add table
Add a link
Reference in a new issue