[PATCH, BINUTILS, AARCH64, 5/9] Add DC CVADP instruction
This patch is part of the patch series to add support for ARMv8.5-A extensions. (https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/dc-data-cache-operation-an-alias-of-sys) This patch adds the DC CVADP instruction. Since this has a separate identification mechanism a new feature bit is added. *** include/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * opcode/aarch64.h (AARCH64_FEATURE_CVADP): New. *** opcodes/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp. (aarch64_sys_ins_reg_supported_p): New check for above. *** gas/ChangeLog *** 2018-10-09 Sudakshina Das <sudi.das@arm.com> * testsuite/gas/aarch64/sysreg-4.s: Test instruction. * testsuite/gas/aarch64/sysreg-4.d: Likewise. * testsuite/gas/aarch64/illegal-sysreg-4.l: Likewise.
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8 changed files with 28 additions and 1 deletions
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@ -72,6 +72,8 @@ typedef uint32_t aarch64_insn;
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#define AARCH64_FEATURE_SB 0x10000000000ULL
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/* Execution and Data Prediction Restriction instructions. */
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#define AARCH64_FEATURE_PREDRES 0x20000000000ULL
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/* DC CVADP. */
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#define AARCH64_FEATURE_CVADP 0x40000000000ULL
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/* Architectures are the sum of the base and extensions. */
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#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
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@ -100,7 +102,8 @@ typedef uint32_t aarch64_insn;
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| AARCH64_FEATURE_FLAGMANIP \
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| AARCH64_FEATURE_FRINTTS \
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| AARCH64_FEATURE_SB \
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| AARCH64_FEATURE_PREDRES)
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| AARCH64_FEATURE_PREDRES \
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| AARCH64_FEATURE_CVADP)
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#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
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