arm: Use DWARF numbering convention for pseudo-register representation
This patch modifies the internal `struct reg_entry' numbering of DWARF
pseudo-registers to match values assigned in DWARF standards (see "4.1
DWARF register names" in [1])so ra_auth_code goes from 12 to 143 and
amends the unwinder .save directive-processing code to correctly handle
mixed register-type save directives.
The mechanism for splitting the register list is also re-written to
comply with register ordering on push statements, being that registers
are stored on the stack in numerical order, with the lowest numbered
register at the lowest address [2].
Consequently, the parsing of the hypothetical directive
.save{r4-r7, r10, ra_auth_core, lr}
has been changed such as rather than producing
.save{r4-r7, r10}
.save{ra_auth_code}
.save{lr}
as was the case with previous implementation, now produces:
.save{lr}
.save{ra_auth_code}
.save{r4-r7, r10}
[1] <https://github.com/ARM-software/abi-aa/blob/main/aadwarf32/aadwarf32.rst>
[2] <https://developer.arm.com/documentation/dui0473/j/arm-and-thumb-instructions/push>
gas/Changelog:
* config/tc-arm.c (REG_RA_AUTH_CODE): New.
(parse_dot_save): Likewise.
(parse_reg_list): Remove obsolete code.
(reg_names): Set ra_auth_code to 143.
(s_arm_unwind_save): Handle core and pseudo-register lists via
parse_dot_save.
(s_arm_unwind_save_mixed): Deleted.
(s_arm_unwind_save_pseudo): Handle one register at a time.
* testsuite/gas/arm/unwind-pacbti-m-readelf.d: Fix test.
* testsuite/gas/arm/unwind-pacbti-m.d: Likewise.
This commit is contained in:
Victor Do Nascimento
Tamar Christina
parent
217cbb0055
commit
3a368c4c24
3 changed files with 95 additions and 70 deletions
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@ -742,6 +742,7 @@ const char * const reg_expected_msgs[] =
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#define REG_SP 13
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#define REG_LR 14
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#define REG_PC 15
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#define REG_RA_AUTH_CODE 143
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/* ARM instructions take 4bytes in the object file, Thumb instructions
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take 2: */
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@ -1943,21 +1944,6 @@ parse_reg_list (char ** strp, enum reg_list_els etype)
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reg = arm_reg_parse (&str, rt);
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/* Skip over allowed registers of alternative types in mixed-type
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register lists. */
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if (reg == FAIL && rt == REG_TYPE_PSEUDO
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&& ((reg = arm_reg_parse (&str, REG_TYPE_RN)) != FAIL))
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{
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cur_reg = reg;
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continue;
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}
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else if (reg == FAIL && rt == REG_TYPE_RN
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&& ((reg = arm_reg_parse (&str, REG_TYPE_PSEUDO)) != FAIL))
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{
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cur_reg = reg;
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continue;
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}
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if (etype == REGLIST_CLRM)
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{
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if (reg == REG_SP || reg == REG_PC)
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@ -4139,7 +4125,6 @@ s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED)
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unwind.sp_restored = 0;
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}
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/* Parse a handlerdata directive. Creates the exception handling table entry
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for the function. */
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@ -4297,15 +4282,19 @@ s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED)
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/* Parse a directive saving pseudo registers. */
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static void
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s_arm_unwind_save_pseudo (long range)
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s_arm_unwind_save_pseudo (int regno)
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{
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valueT op;
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if (range & (1 << 12))
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switch (regno)
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{
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case REG_RA_AUTH_CODE:
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/* Opcode for restoring RA_AUTH_CODE. */
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op = 0xb4;
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add_unwind_opcode (op, 1);
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break;
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default:
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as_bad (_("Unknown register no. encountered: %d\n"), regno);
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}
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}
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@ -4375,6 +4364,80 @@ s_arm_unwind_save_core (long range)
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}
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}
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/* Implement correct handling of .save lists enabling the split into
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sublists where necessary, while preserving correct sublist ordering. */
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static void
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parse_dot_save (char **str_p, int prev_reg)
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{
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long core_regs = 0;
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int reg;
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int in_range = 0;
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if (**str_p == ',')
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*str_p += 1;
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if (**str_p == '}')
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{
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*str_p += 1;
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return;
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}
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while ((reg = arm_reg_parse (str_p, REG_TYPE_RN)) != FAIL)
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{
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if (!in_range)
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{
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if (core_regs & (1 << reg))
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as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
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reg);
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else if (reg <= prev_reg)
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as_tsktsk (_("Warning: register list not in ascending order"));
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core_regs |= (1 << reg);
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prev_reg = reg;
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if (skip_past_char(str_p, '-') != FAIL)
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in_range = 1;
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else if (skip_past_comma(str_p) == FAIL)
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first_error (_("bad register list"));
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}
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else
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{
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int i;
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if (reg <= prev_reg)
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first_error (_("bad range in register list"));
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for (i = prev_reg + 1; i <= reg; i++)
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{
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if (core_regs & (1 << i))
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as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
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i);
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else
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core_regs |= 1 << i;
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}
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in_range = 0;
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}
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}
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if (core_regs)
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{
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/* Higher register numbers go in higher memory addresses. When splitting a list,
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right-most sublist should therefore be .saved first. Use recursion for this. */
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parse_dot_save (str_p, reg);
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/* We're back from recursion, so emit .save insn for sublist. */
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s_arm_unwind_save_core (core_regs);
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return;
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}
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/* Handle pseudo-regs, under assumption these are emitted singly. */
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else if ((reg = arm_reg_parse (str_p, REG_TYPE_PSEUDO)) != FAIL)
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{
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/* recurse for remainder of input. Note: No assumption is made regarding which
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register in core register set holds pseudo-register. It's not considered in
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ordering check beyond ensuring it's not sandwiched between 2 consecutive
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registers. */
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parse_dot_save (str_p, prev_reg + 1);
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s_arm_unwind_save_pseudo (reg);
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return;
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}
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else
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as_bad (BAD_SYNTAX);
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}
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/* Parse a directive saving FPA registers. */
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@ -4716,39 +4779,13 @@ s_arm_unwind_save_mmxwcg (void)
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ignore_rest_of_line ();
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}
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/* Convert range and mask_range into a sequence of s_arm_unwind_core
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and s_arm_unwind_pseudo operations. We assume that mask_range will
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not have consecutive bits set, or that one operation per bit is
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acceptable. */
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static void
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s_arm_unwind_save_mixed (long range, long mask_range)
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{
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while (mask_range)
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{
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long mask_bit = mask_range & -mask_range;
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long subrange = range & (mask_bit - 1);
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if (subrange)
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s_arm_unwind_save_core (subrange);
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s_arm_unwind_save_pseudo (mask_bit);
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range &= ~subrange;
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mask_range &= ~mask_bit;
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}
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if (range)
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s_arm_unwind_save_core (range);
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}
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/* Parse an unwind_save directive.
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If the argument is non-zero, this is a .vsave directive. */
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static void
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s_arm_unwind_save (int arch_v6)
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{
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char *peek, *mask_peek;
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long range, mask_range;
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char *peek;
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struct reg_entry *reg;
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bool had_brace = false;
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@ -4756,7 +4793,7 @@ s_arm_unwind_save (int arch_v6)
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as_bad (MISSING_FNSTART);
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/* Figure out what sort of save we have. */
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peek = mask_peek = input_line_pointer;
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peek = input_line_pointer;
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if (*peek == '{')
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{
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@ -4788,20 +4825,13 @@ s_arm_unwind_save (int arch_v6)
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case REG_TYPE_PSEUDO:
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case REG_TYPE_RN:
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mask_range = parse_reg_list (&mask_peek, REGLIST_PSEUDO);
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range = parse_reg_list (&input_line_pointer, REGLIST_RN);
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if (range == FAIL || mask_range == FAIL)
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{
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as_bad (_("expected register list"));
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ignore_rest_of_line ();
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return;
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}
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demand_empty_rest_of_line ();
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s_arm_unwind_save_mixed (range, mask_range);
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return;
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{
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if (had_brace)
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input_line_pointer++;
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parse_dot_save (&input_line_pointer, -1);
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demand_empty_rest_of_line ();
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return;
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}
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case REG_TYPE_VFD:
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if (arch_v6)
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@ -23993,12 +24023,8 @@ static const struct reg_entry reg_names[] =
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/* XScale accumulator registers. */
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REGNUM(acc,0,XSCALE), REGNUM(ACC,0,XSCALE),
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/* DWARF ABI defines RA_AUTH_CODE to 143. It also reserves 134-142 for future
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expansion. RA_AUTH_CODE here is given the value 143 % 134 to make it easy
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for tc_arm_regname_to_dw2regnum to translate to DWARF reg number using
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134 + reg_number should the range 134 to 142 be used for more pseudo regs
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in the future. This also helps fit RA_AUTH_CODE into a bitmask. */
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REGDEF(ra_auth_code,12,PSEUDO),
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/* DWARF ABI defines RA_AUTH_CODE to 143. */
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REGDEF(ra_auth_code,143,PSEUDO),
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};
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#undef REGDEF
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#undef REGNUM
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@ -27905,7 +27931,6 @@ create_unwind_entry (int have_data)
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return 0;
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}
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/* Initialize the DWARF-2 unwind information for this procedure. */
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void
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@ -10,11 +10,11 @@ Unwind section '.ARM.exidx' at offset 0x60 contains 1 entry:
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0x0 <foo>: @0x0
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Compact model index: 1
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0x84 0x00 pop {r14}
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0xb4 pop {ra_auth_code}
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0x84 0x00 pop {r14}
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0xb4 pop {ra_auth_code}
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0xa3 pop {r4, r5, r6, r7}
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0xb4 pop {ra_auth_code}
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0x84 0x00 pop {r14}
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0xb4 pop {ra_auth_code}
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0xa8 pop {r4, r14}
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0xb0 finish
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@ -8,4 +8,4 @@
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.*: file format.*
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Contents of section .ARM.extab:
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0000 (00840281 b40084b4 b0a8b4a3|81028400 b48400b4 a3b4a8b0) 00000000 .*
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0000 (84b40281 84b4a300 b0a8b400|8102b484 00a3b484 00b4a8b0) 00000000 .*
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