FreeChainXenon/binutils-gdb
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

* Makefile.in (MAIN_INCLUDE_DEPS): Delete.

Browse source 
(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
	(sim-if.o): Use SIM_MAIN_DEPS.
	(arch.o,traps.o,devices.o): Ditto.
	(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
	(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
	(m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
	(stamp-arch): Pass mach=all to cgen-arch.
	* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
	* m32r-sim.h (fr30bf_h_cr_[gs]et_handler): Declare.
	([GS]ET_H_CR): Define.
	(fr30bf_h_psw_[gs]et_handler): Declare.
	([GS]ET_H_PSW): Define.
	(fr30bf_h_accum_[gs]et_handler): Declare.
	([GS]ET_H_ACCUM): Define.
	(fr30xf_h_{cr,psw,accum}_[gs]et_handler): Declare.
	(fr30bf_h_accums_[gs]et_handler): Declare.
	([GS]ET_H_ACCUMS): Define.
	* sim-if.c (sim_open): Model probing code moved to sim-model.c.
	* m32r.c (WANT_CPU): Define as m32rbf.
	(all register access fns): Rename to ..._handler.
	* cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
	* m32rx.c (WANT_CPU): Define as m32rxf.
	(all register access fns): Rename to ..._handler.
This commit is contained in:
Doug Evans 1999-01-06 03:04:25 +00:00
parent d9455383f9
commit 368fc7dba8
14 changed files with 7790 additions and 970 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

43
sim/m32r/ChangeLog
View file

@ -1,3 +1,46 @@
1999-01-05 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (MAIN_INCLUDE_DEPS): Delete.
(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
(sim-if.o): Use SIM_MAIN_DEPS.
(arch.o,traps.o,devices.o): Ditto.
(M32RBF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
(m32r.o,mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
start-sanitize-m32rx
(m32rx.o,mloopx.o,cpux.o,decodex.o,semx.o,modelx.o): Ditto.
end-sanitize-m32rx
(stamp-arch): Pass mach=all to cgen-arch.
* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
* m32r-sim.h (fr30bf_h_cr_[gs]et_handler): Declare.
([GS]ET_H_CR): Define.
(fr30bf_h_psw_[gs]et_handler): Declare.
([GS]ET_H_PSW): Define.
(fr30bf_h_accum_[gs]et_handler): Declare.
([GS]ET_H_ACCUM): Define.
start-sanitize-m32rx
(fr30xf_h_{cr,psw,accum}_[gs]et_handler): Declare.
(fr30bf_h_accums_[gs]et_handler): Declare.
([GS]ET_H_ACCUMS): Define.
end-sanitize-m32rx
* sim-if.c (sim_open): Model probing code moved to sim-model.c.
* m32r.c (WANT_CPU): Define as m32rbf.
(all register access fns): Rename to ..._handler.
start-sanitize-m32rx
* cpux.c,cpux.h,decodex.c,modelx.c,semx.c: Regenerate.
* m32rx.c (WANT_CPU): Define as m32rxf.
(all register access fns): Rename to ..._handler.
end-sanitize-m32rx
1998-12-14 Doug Evans <devans@casey.cygnus.com>
* configure.in: --enable-cgen-maint support moved to common/aclocal.m4.
(SIM_AC_OPTION_ALIGNMENT): Make strict.
* configure: Regenerate.
* sem-switch.c,sem.c,semx-switch.c: Regenerate.
* sim-main.h (SIM_ENGINE_HALT_HOOK,SIM_ENGINE_RESTART_HOOK): Define.
* traps.c (m32r_core_signal): Handle --environment=operating.
1998-12-09 Doug Evans <devans@casey.cygnus.com> 1998-12-09 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate. * cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.

108
sim/m32r/Makefile.in
View file

@ -20,9 +20,9 @@
## COMMON_PRE_CONFIG_FRAG ## COMMON_PRE_CONFIG_FRAG
M32R_OBJS = m32r.o cpu.o decode.o extract.o sem.o model.o mloop.o M32R_OBJS = m32r.o cpu.o decode.o sem.o model.o mloop.o
# start-sanitize-m32rx # start-sanitize-m32rx
M32RX_OBJS = m32rx.o cpux.o decodex.o extractx.o modelx.o mloopx.o M32RX_OBJS = m32rx.o cpux.o decodex.o modelx.o mloopx.o
# end-sanitize-m32rx # end-sanitize-m32rx
CONFIG_DEVICES = dv-sockser.o CONFIG_DEVICES = dv-sockser.o
@ -47,11 +47,8 @@ SIM_OBJS = \
# Extra headers included by sim-main.h. # Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \ SIM_EXTRA_DEPS = \
$(srcdir)/../common/cgen-types.h \ $(CGEN_INCLUDE_DEPS) \
$(srcdir)/../common/cgen-sim.h \ arch.h cpuall.h m32r-sim.h cpu-opc.h
$(srcdir)/../common/cgen-trace.h \
arch.h cpuall.h m32r-sim.h cpu-opc.h \
$(srcdir)/../../include/opcode/cgen.h
SIM_EXTRA_CFLAGS = SIM_EXTRA_CFLAGS =
@ -65,70 +62,67 @@ NL_TARGET = -DNL_TARGET_m32r
arch = m32r arch = m32r
MAIN_INCLUDE_DEPS = \ sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
sim-main.h \
$(srcdir)/../common/sim-config.h \
$(srcdir)/../common/sim-base.h \
$(srcdir)/../common/sim-basics.h \
$(srcdir)/../common/sim-module.h \
$(srcdir)/../common/sim-trace.h \
$(srcdir)/../common/sim-profile.h \
tconfig.h
INCLUDE_DEPS = $(MAIN_INCLUDE_DEPS) $(SIM_EXTRA_DEPS)
OPS_INCLUDE_DEPS = \
$(srcdir)/../common/cgen-mem.h \
$(srcdir)/../common/cgen-ops.h
sim-if.o: sim-if.c $(INCLUDE_DEPS) $(srcdir)/../common/sim-core.h arch.o: arch.c $(SIM_MAIN_DEPS)
arch.o: arch.c $(INCLUDE_DEPS) traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
devices.o: devices.c $(SIM_MAIN_DEPS)
devices.o: devices.c $(INCLUDE_DEPS)
# M32R objs # M32R objs
m32r.o: m32r.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h M32RBF_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpu.h decode.h eng.h
m32r.o: m32r.c $(M32RBF_INCLUDE_DEPS)
# FIXME: Use of `mono' is wip. # FIXME: Use of `mono' is wip.
mloop.c: $(srcdir)/../common/genmloop.sh mloop.in Makefile mloop.c eng.h: stamp-mloop
rm -f mloop.c stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \ $(SHELL) $(srccom)/genmloop.sh \
-mono -fast -pbb -switch sem-switch.c \ -mono -fast -pbb -switch sem-switch.c \
m32rbf $(srcdir)/mloop.in \ -cpu m32rbf -infile $(srcdir)/mloop.in
| sed -e 's/@cpu@/m32rbf/' -e 's/@CPU@/M32RBF/' >mloop.c $(SHELL) $(srcroot)/move-if-change eng.hin eng.h
mloop.o: mloop.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) stamp-cpu $(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
touch stamp-mloop
mloop.o: mloop.c sem-switch.c $(M32RBF_INCLUDE_DEPS)
cpu.o: cpu.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h cpu.o: cpu.c $(M32RBF_INCLUDE_DEPS)
decode.o: decode.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h decode.o: decode.c $(M32RBF_INCLUDE_DEPS)
extract.o: extract.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h sem.o: sem.c $(M32RBF_INCLUDE_DEPS)
sem.o: sem.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpu.h decode.h model.o: model.c $(M32RBF_INCLUDE_DEPS)
model.o: model.c $(INCLUDE_DEPS) cpu.h decode.h
# start-sanitize-m32rx # start-sanitize-m32rx
# M32RX objs # M32RX objs
m32rx.o: m32rx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h M32RXF_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpux.h decodex.h engx.h
m32rx.o: m32rx.c $(M32RXF_INCLUDE_DEPS)
# FIXME: Use of `mono' is wip. # FIXME: Use of `mono' is wip.
mloopx.c: $(srcdir)/../common/genmloop.sh mloopx.in Makefile mloopx.c engx.h: stamp-xmloop
rm -f mloopx.c stamp-xmloop: $(srcdir)/../common/genmloop.sh mloopx.in Makefile
$(SHELL) $(srcdir)/../common/genmloop.sh $(SHELL) \ $(SHELL) $(srccom)/genmloop.sh \
-mono -no-fast -pbb -parallel -switch semx-switch.c \ -mono -no-fast -pbb -parallel -switch semx-switch.c \
m32rxf $(srcdir)/mloopx.in \ -cpu m32rxf -infile $(srcdir)/mloopx.in
| sed -e 's/@cpu@/m32rxf/' -e 's/@CPU@/M32RXF/' >mloopx.c $(SHELL) $(srcroot)/move-if-change eng.hin engx.h
mloopx.o: mloopx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) stamp-xcpu $(SHELL) $(srcroot)/move-if-change mloop.cin mloopx.c
touch stamp-xmloop
mloopx.o: mloopx.c semx-switch.c $(M32RXF_INCLUDE_DEPS)
cpux.o: cpux.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h cpux.o: cpux.c $(M32RXF_INCLUDE_DEPS)
decodex.o: decodex.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h decodex.o: decodex.c $(M32RXF_INCLUDE_DEPS)
extractx.o: extractx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h semx.o: semx.c $(M32RXF_INCLUDE_DEPS)
#semx.o: semx.c $(INCLUDE_DEPS) $(OPS_INCLUDE_DEPS) cpux.h decodex.h modelx.o: modelx.c $(M32RXF_INCLUDE_DEPS)
modelx.o: modelx.c $(INCLUDE_DEPS) cpux.h decodex.h
# end-sanitize-m32rx # end-sanitize-m32rx
m32r-clean: m32r-clean:
rm -f mloop.c stamp-arch stamp-cpu rm -f mloop.c stamp-arch stamp-cpu stamp-mloop
# start-sanitize-m32rx # start-sanitize-m32rx
rm -f mloopx.c stamp-xcpu rm -f mloopx.c stamp-xcpu stamp-xmloop
# end-sanitize-m32rx # end-sanitize-m32rx
rm -f tmp-* rm -f tmp-*
@ -138,25 +132,27 @@ CGEN_MAINT = ; @true
# The following line is commented in or out depending upon --enable-cgen-maint. # The following line is commented in or out depending upon --enable-cgen-maint.
@CGEN_MAINT@CGEN_MAINT = @CGEN_MAINT@CGEN_MAINT =
stamp-arch: $(CGEN_MAIN_SCM) $(srccgen)/m32r.cpu stamp-arch: $(CGEN_MAIN_SCM) $(CGEN_ARCH_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) $(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all
touch stamp-arch touch stamp-arch
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
@true @true
stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu stamp-cpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32rbf mach=m32r SUFFIX= FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)" cpu=m32rbf mach=m32r SUFFIX= \
FLAGS="with-scache,with-profile fn" \
EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
touch stamp-cpu touch stamp-cpu
cpu.h extract.c sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
@true @true
# end-sanitize-cygnus # end-sanitize-cygnus
# start-sanitize-m32rx # start-sanitize-m32rx
stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu stamp-xcpu: $(CGEN_MAIN_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srccgen)/m32r.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \ $(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_EXTR) $(CGEN_CPU_SEMSW)" cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache,with-profile fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"
touch stamp-xcpu touch stamp-xcpu
cpux.h extractx.c semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu cpux.h semx-switch.c modelx.c decodex.c decodex.h: $(CGEN_MAINT) stamp-xcpu
@true @true
# end-sanitize-m32rx # end-sanitize-m32rx

196
sim/m32r/cpu.c Normal file
View file

@ -0,0 +1,196 @@
/* Misc. support for CPU family m32rbf.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define WANT_CPU m32rbf
#define WANT_CPU_M32RBF
#include "sim-main.h"
/* Get the value of h-pc. */
USI
m32rbf_h_pc_get (SIM_CPU *current_cpu)
{
return CPU (h_pc);
}
/* Set a value for h-pc. */
void
m32rbf_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
CPU (h_pc) = newval;
}
/* Get the value of h-gr. */
SI
m32rbf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_gr[regno]);
}
/* Set a value for h-gr. */
void
m32rbf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
CPU (h_gr[regno]) = newval;
}
/* Get the value of h-cr. */
USI
m32rbf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_CR (regno);
}
/* Set a value for h-cr. */
void
m32rbf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
SET_H_CR (regno, newval);
}
/* Get the value of h-accum. */
DI
m32rbf_h_accum_get (SIM_CPU *current_cpu)
{
return GET_H_ACCUM ();
}
/* Set a value for h-accum. */
void
m32rbf_h_accum_set (SIM_CPU *current_cpu, DI newval)
{
SET_H_ACCUM (newval);
}
/* Get the value of h-accums. */
DI
m32rbf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_ACCUMS (regno);
}
/* Set a value for h-accums. */
void
m32rbf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_ACCUMS (regno, newval);
}
/* Get the value of h-cond. */
BI
m32rbf_h_cond_get (SIM_CPU *current_cpu)
{
return CPU (h_cond);
}
/* Set a value for h-cond. */
void
m32rbf_h_cond_set (SIM_CPU *current_cpu, BI newval)
{
CPU (h_cond) = newval;
}
/* Get the value of h-psw. */
UQI
m32rbf_h_psw_get (SIM_CPU *current_cpu)
{
return GET_H_PSW ();
}
/* Set a value for h-psw. */
void
m32rbf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
{
SET_H_PSW (newval);
}
/* Get the value of h-bpsw. */
UQI
m32rbf_h_bpsw_get (SIM_CPU *current_cpu)
{
return CPU (h_bpsw);
}
/* Set a value for h-bpsw. */
void
m32rbf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_bpsw) = newval;
}
/* Get the value of h-bbpsw. */
UQI
m32rbf_h_bbpsw_get (SIM_CPU *current_cpu)
{
return CPU (h_bbpsw);
}
/* Set a value for h-bbpsw. */
void
m32rbf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_bbpsw) = newval;
}
/* Get the value of h-lock. */
BI
m32rbf_h_lock_get (SIM_CPU *current_cpu)
{
return CPU (h_lock);
}
/* Set a value for h-lock. */
void
m32rbf_h_lock_set (SIM_CPU *current_cpu, BI newval)
{
CPU (h_lock) = newval;
}
/* Record trace results for INSN. */
void
m32rbf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
int *indices, TRACE_RECORD *tr)
{
}

93
sim/m32r/cpu.h
View file

@ -46,26 +46,18 @@ typedef struct {
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/* control registers */ /* control registers */
USI h_cr[16]; USI h_cr[16];
#define GET_H_CR(a1) CPU (h_cr)[a1]
#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
/* accumulator */ /* accumulator */
DI h_accum; DI h_accum;
#define GET_H_ACCUM() CPU (h_accum)
#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
/* start-sanitize-m32rx */ /* start-sanitize-m32rx */
/* accumulators */ /* accumulators */
DI h_accums[2]; DI h_accums[2];
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
/* condition bit */ /* condition bit */
BI h_cond; BI h_cond;
#define GET_H_COND() CPU (h_cond) #define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x)) #define SET_H_COND(x) (CPU (h_cond) = (x))
/* psw part of psw */ /* psw part of psw */
UQI h_psw; UQI h_psw;
#define GET_H_PSW() CPU (h_psw)
#define SET_H_PSW(x) (CPU (h_psw) = (x))
/* backup psw */ /* backup psw */
UQI h_bpsw; UQI h_bpsw;
#define GET_H_BPSW() CPU (h_bpsw) #define GET_H_BPSW() CPU (h_bpsw)
@ -127,6 +119,9 @@ struct argbuf {
union sem semantic; union sem semantic;
int written; int written;
union { union {
struct { /* empty format for unspecified field list */
int empty;
} fmt_empty;
struct { /* e.g. add $dr,$sr */ struct { /* e.g. add $dr,$sr */
SI * i_dr; SI * i_dr;
SI * i_sr; SI * i_sr;
@ -135,29 +130,29 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_add; } fmt_add;
struct { /* e.g. add3 $dr,$sr,$hash$slo16 */ struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_add3; } fmt_add3;
struct { /* e.g. and3 $dr,$sr,$uimm16 */ struct { /* e.g. and3 $dr,$sr,$uimm16 */
UINT f_uimm16;
SI * i_sr; SI * i_sr;
USI f_uimm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_and3; } fmt_and3;
struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */ struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
UINT f_uimm16;
SI * i_sr; SI * i_sr;
UHI f_uimm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_or3; } fmt_or3;
struct { /* e.g. addi $dr,$simm8 */ struct { /* e.g. addi $dr,$simm8 */
INT f_simm8;
SI * i_dr; SI * i_dr;
SI f_simm8;
unsigned char in_dr; unsigned char in_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_addi; } fmt_addi;
@ -169,8 +164,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_addv; } fmt_addv;
struct { /* e.g. addv3 $dr,$sr,$simm16 */ struct { /* e.g. addv3 $dr,$sr,$simm16 */
INT f_simm16;
SI * i_sr; SI * i_sr;
SI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -189,8 +184,8 @@ struct argbuf {
unsigned char in_src2; unsigned char in_src2;
} fmt_cmp; } fmt_cmp;
struct { /* e.g. cmpi $src2,$simm16 */ struct { /* e.g. cmpi $src2,$simm16 */
INT f_simm16;
SI * i_src2; SI * i_src2;
SI f_simm16;
unsigned char in_src2; unsigned char in_src2;
} fmt_cmpi; } fmt_cmpi;
struct { /* e.g. div $dr,$sr */ struct { /* e.g. div $dr,$sr */
@ -207,8 +202,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_ld; } fmt_ld;
struct { /* e.g. ld $dr,@($slo16,$sr) */ struct { /* e.g. ld $dr,@($slo16,$sr) */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -220,8 +215,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_ldb; } fmt_ldb;
struct { /* e.g. ldb $dr,@($slo16,$sr) */ struct { /* e.g. ldb $dr,@($slo16,$sr) */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -233,8 +228,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_ldh; } fmt_ldh;
struct { /* e.g. ldh $dr,@($slo16,$sr) */ struct { /* e.g. ldh $dr,@($slo16,$sr) */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -247,17 +242,17 @@ struct argbuf {
unsigned char out_sr; unsigned char out_sr;
} fmt_ld_plus; } fmt_ld_plus;
struct { /* e.g. ld24 $dr,$uimm24 */ struct { /* e.g. ld24 $dr,$uimm24 */
ADDR f_uimm24; ADDR i_uimm24;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_ld24; } fmt_ld24;
struct { /* e.g. ldi8 $dr,$simm8 */ struct { /* e.g. ldi8 $dr,$simm8 */
SI f_simm8; INT f_simm8;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_ldi8; } fmt_ldi8;
struct { /* e.g. ldi16 $dr,$hash$slo16 */ struct { /* e.g. ldi16 $dr,$hash$slo16 */
HI f_simm16; INT f_simm16;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_ldi16; } fmt_ldi16;
@ -299,8 +294,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_mvtachi; } fmt_mvtachi;
struct { /* e.g. mvtc $sr,$dcr */ struct { /* e.g. mvtc $sr,$dcr */
SI * i_sr;
UINT f_r1; UINT f_r1;
SI * i_sr;
unsigned char in_sr; unsigned char in_sr;
} fmt_mvtc; } fmt_mvtc;
struct { /* e.g. nop */ struct { /* e.g. nop */
@ -310,20 +305,20 @@ struct argbuf {
int empty; int empty;
} fmt_rac; } fmt_rac;
struct { /* e.g. seth $dr,$hash$hi16 */ struct { /* e.g. seth $dr,$hash$hi16 */
UHI f_hi16; UINT f_hi16;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_seth; } fmt_seth;
struct { /* e.g. sll3 $dr,$sr,$simm16 */ struct { /* e.g. sll3 $dr,$sr,$simm16 */
INT f_simm16;
SI * i_sr; SI * i_sr;
SI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_sll3; } fmt_sll3;
struct { /* e.g. slli $dr,$uimm5 */ struct { /* e.g. slli $dr,$uimm5 */
UINT f_uimm5;
SI * i_dr; SI * i_dr;
USI f_uimm5;
unsigned char in_dr; unsigned char in_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_slli; } fmt_slli;
@ -334,8 +329,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_st; } fmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */ struct { /* e.g. st $src1,@($slo16,$src2) */
INT f_simm16;
SI * i_src2; SI * i_src2;
HI f_simm16;
SI * i_src1; SI * i_src1;
unsigned char in_src2; unsigned char in_src2;
unsigned char in_src1; unsigned char in_src1;
@ -347,8 +342,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_stb; } fmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */ struct { /* e.g. stb $src1,@($slo16,$src2) */
INT f_simm16;
SI * i_src2; SI * i_src2;
HI f_simm16;
SI * i_src1; SI * i_src1;
unsigned char in_src2; unsigned char in_src2;
unsigned char in_src1; unsigned char in_src1;
@ -360,8 +355,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_sth; } fmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */ struct { /* e.g. sth $src1,@($slo16,$src2) */
INT f_simm16;
SI * i_src2; SI * i_src2;
HI f_simm16;
SI * i_src1; SI * i_src1;
unsigned char in_src2; unsigned char in_src2;
unsigned char in_src1; unsigned char in_src1;
@ -383,36 +378,36 @@ struct argbuf {
struct { struct {
union { union {
struct { /* e.g. bc.s $disp8 */ struct { /* e.g. bc.s $disp8 */
IADDR f_disp8; IADDR i_disp8;
} fmt_bc8; } fmt_bc8;
struct { /* e.g. bc.l $disp24 */ struct { /* e.g. bc.l $disp24 */
IADDR f_disp24; IADDR i_disp24;
} fmt_bc24; } fmt_bc24;
struct { /* e.g. beq $src1,$src2,$disp16 */ struct { /* e.g. beq $src1,$src2,$disp16 */
SI * i_src1; SI * i_src1;
SI * i_src2; SI * i_src2;
IADDR f_disp16; IADDR i_disp16;
unsigned char in_src1; unsigned char in_src1;
unsigned char in_src2; unsigned char in_src2;
} fmt_beq; } fmt_beq;
struct { /* e.g. beqz $src2,$disp16 */ struct { /* e.g. beqz $src2,$disp16 */
SI * i_src2; SI * i_src2;
IADDR f_disp16; IADDR i_disp16;
unsigned char in_src2; unsigned char in_src2;
} fmt_beqz; } fmt_beqz;
struct { /* e.g. bl.s $disp8 */ struct { /* e.g. bl.s $disp8 */
IADDR f_disp8; IADDR i_disp8;
unsigned char out_h_gr_14; unsigned char out_h_gr_14;
} fmt_bl8; } fmt_bl8;
struct { /* e.g. bl.l $disp24 */ struct { /* e.g. bl.l $disp24 */
IADDR f_disp24; IADDR i_disp24;
unsigned char out_h_gr_14; unsigned char out_h_gr_14;
} fmt_bl24; } fmt_bl24;
struct { /* e.g. bra.s $disp8 */ struct { /* e.g. bra.s $disp8 */
IADDR f_disp8; IADDR i_disp8;
} fmt_bra8; } fmt_bra8;
struct { /* e.g. bra.l $disp24 */ struct { /* e.g. bra.l $disp24 */
IADDR f_disp24; IADDR i_disp24;
} fmt_bra24; } fmt_bra24;
struct { /* e.g. jl $sr */ struct { /* e.g. jl $sr */
SI * i_sr; SI * i_sr;
@ -427,14 +422,14 @@ struct argbuf {
int empty; int empty;
} fmt_rte; } fmt_rte;
struct { /* e.g. trap $uimm4 */ struct { /* e.g. trap $uimm4 */
USI f_uimm4; UINT f_uimm4;
} fmt_trap; } fmt_trap;
} fields; } fields;
#if WITH_SCACHE_PBB_M32RBF #if WITH_SCACHE_PBB
SEM_PC addr_cache; SEM_PC addr_cache;
#endif #endif
} cti; } cti;
#if WITH_SCACHE_PBB_M32RBF #if WITH_SCACHE_PBB
/* Writeback handler. */ /* Writeback handler. */
struct { struct {
/* Pointer to argbuf entry for insn whose results need writing back. */ /* Pointer to argbuf entry for insn whose results need writing back. */
@ -473,6 +468,12 @@ struct scache {
/* Macros to simplify extraction, reading and semantic code. /* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */ These define and assign the local vars that contain the insn's fields. */
#define EXTRACT_FMT_EMPTY_VARS \
/* Instruction fields. */ \
unsigned int length;
#define EXTRACT_FMT_EMPTY_CODE \
length = 0; \
#define EXTRACT_FMT_ADD_VARS \ #define EXTRACT_FMT_ADD_VARS \
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
@ -595,7 +596,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp8; \ SI f_disp8; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BC8_CODE \ #define EXTRACT_FMT_BC8_CODE \
length = 2; \ length = 2; \
@ -607,7 +608,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp24; \ SI f_disp24; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BC24_CODE \ #define EXTRACT_FMT_BC24_CODE \
length = 4; \ length = 4; \
@ -621,7 +622,7 @@ struct scache {
UINT f_r1; \ UINT f_r1; \
UINT f_op2; \ UINT f_op2; \
UINT f_r2; \ UINT f_r2; \
INT f_disp16; \ SI f_disp16; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BEQ_CODE \ #define EXTRACT_FMT_BEQ_CODE \
length = 4; \ length = 4; \
@ -637,7 +638,7 @@ struct scache {
UINT f_r1; \ UINT f_r1; \
UINT f_op2; \ UINT f_op2; \
UINT f_r2; \ UINT f_r2; \
INT f_disp16; \ SI f_disp16; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BEQZ_CODE \ #define EXTRACT_FMT_BEQZ_CODE \
length = 4; \ length = 4; \
@ -651,7 +652,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp8; \ SI f_disp8; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BL8_CODE \ #define EXTRACT_FMT_BL8_CODE \
length = 2; \ length = 2; \
@ -663,7 +664,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp24; \ SI f_disp24; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BL24_CODE \ #define EXTRACT_FMT_BL24_CODE \
length = 4; \ length = 4; \
@ -675,7 +676,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp8; \ SI f_disp8; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BRA8_CODE \ #define EXTRACT_FMT_BRA8_CODE \
length = 2; \ length = 2; \
@ -687,7 +688,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp24; \ SI f_disp24; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BRA24_CODE \ #define EXTRACT_FMT_BRA24_CODE \
length = 4; \ length = 4; \

196
sim/m32r/cpux.c Normal file
View file

@ -0,0 +1,196 @@
/* Misc. support for CPU family m32rxf.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define WANT_CPU m32rxf
#define WANT_CPU_M32RXF
#include "sim-main.h"
/* Get the value of h-pc. */
USI
m32rxf_h_pc_get (SIM_CPU *current_cpu)
{
return CPU (h_pc);
}
/* Set a value for h-pc. */
void
m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
CPU (h_pc) = newval;
}
/* Get the value of h-gr. */
SI
m32rxf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_gr[regno]);
}
/* Set a value for h-gr. */
void
m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
CPU (h_gr[regno]) = newval;
}
/* Get the value of h-cr. */
USI
m32rxf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_CR (regno);
}
/* Set a value for h-cr. */
void
m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
{
SET_H_CR (regno, newval);
}
/* Get the value of h-accum. */
DI
m32rxf_h_accum_get (SIM_CPU *current_cpu)
{
return GET_H_ACCUM ();
}
/* Set a value for h-accum. */
void
m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
{
SET_H_ACCUM (newval);
}
/* Get the value of h-accums. */
DI
m32rxf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
{
return GET_H_ACCUMS (regno);
}
/* Set a value for h-accums. */
void
m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
{
SET_H_ACCUMS (regno, newval);
}
/* Get the value of h-cond. */
BI
m32rxf_h_cond_get (SIM_CPU *current_cpu)
{
return CPU (h_cond);
}
/* Set a value for h-cond. */
void
m32rxf_h_cond_set (SIM_CPU *current_cpu, BI newval)
{
CPU (h_cond) = newval;
}
/* Get the value of h-psw. */
UQI
m32rxf_h_psw_get (SIM_CPU *current_cpu)
{
return GET_H_PSW ();
}
/* Set a value for h-psw. */
void
m32rxf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
{
SET_H_PSW (newval);
}
/* Get the value of h-bpsw. */
UQI
m32rxf_h_bpsw_get (SIM_CPU *current_cpu)
{
return CPU (h_bpsw);
}
/* Set a value for h-bpsw. */
void
m32rxf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_bpsw) = newval;
}
/* Get the value of h-bbpsw. */
UQI
m32rxf_h_bbpsw_get (SIM_CPU *current_cpu)
{
return CPU (h_bbpsw);
}
/* Set a value for h-bbpsw. */
void
m32rxf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
{
CPU (h_bbpsw) = newval;
}
/* Get the value of h-lock. */
BI
m32rxf_h_lock_get (SIM_CPU *current_cpu)
{
return CPU (h_lock);
}
/* Set a value for h-lock. */
void
m32rxf_h_lock_set (SIM_CPU *current_cpu, BI newval)
{
CPU (h_lock) = newval;
}
/* Record trace results for INSN. */
void
m32rxf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
int *indices, TRACE_RECORD *tr)
{
}

110
sim/m32r/cpux.h
View file

@ -46,26 +46,18 @@ typedef struct {
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x)) #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/* control registers */ /* control registers */
USI h_cr[16]; USI h_cr[16];
#define GET_H_CR(a1) CPU (h_cr)[a1]
#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
/* accumulator */ /* accumulator */
DI h_accum; DI h_accum;
#define GET_H_ACCUM() CPU (h_accum)
#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
/* start-sanitize-m32rx */ /* start-sanitize-m32rx */
/* accumulators */ /* accumulators */
DI h_accums[2]; DI h_accums[2];
/* end-sanitize-m32rx */ /* end-sanitize-m32rx */
#define GET_H_ACCUMS(a1) CPU (h_accums)[a1]
#define SET_H_ACCUMS(a1, x) (CPU (h_accums)[a1] = (x))
/* condition bit */ /* condition bit */
BI h_cond; BI h_cond;
#define GET_H_COND() CPU (h_cond) #define GET_H_COND() CPU (h_cond)
#define SET_H_COND(x) (CPU (h_cond) = (x)) #define SET_H_COND(x) (CPU (h_cond) = (x))
/* psw part of psw */ /* psw part of psw */
UQI h_psw; UQI h_psw;
#define GET_H_PSW() CPU (h_psw)
#define SET_H_PSW(x) (CPU (h_psw) = (x))
/* backup psw */ /* backup psw */
UQI h_bpsw; UQI h_bpsw;
#define GET_H_BPSW() CPU (h_bpsw) #define GET_H_BPSW() CPU (h_bpsw)
@ -123,6 +115,9 @@ struct argbuf {
union sem semantic; union sem semantic;
int written; int written;
union { union {
struct { /* empty format for unspecified field list */
int empty;
} fmt_empty;
struct { /* e.g. add $dr,$sr */ struct { /* e.g. add $dr,$sr */
SI * i_dr; SI * i_dr;
SI * i_sr; SI * i_sr;
@ -131,29 +126,29 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_add; } fmt_add;
struct { /* e.g. add3 $dr,$sr,$hash$slo16 */ struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_add3; } fmt_add3;
struct { /* e.g. and3 $dr,$sr,$uimm16 */ struct { /* e.g. and3 $dr,$sr,$uimm16 */
UINT f_uimm16;
SI * i_sr; SI * i_sr;
USI f_uimm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_and3; } fmt_and3;
struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */ struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
UINT f_uimm16;
SI * i_sr; SI * i_sr;
UHI f_uimm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_or3; } fmt_or3;
struct { /* e.g. addi $dr,$simm8 */ struct { /* e.g. addi $dr,$simm8 */
INT f_simm8;
SI * i_dr; SI * i_dr;
SI f_simm8;
unsigned char in_dr; unsigned char in_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_addi; } fmt_addi;
@ -165,8 +160,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_addv; } fmt_addv;
struct { /* e.g. addv3 $dr,$sr,$simm16 */ struct { /* e.g. addv3 $dr,$sr,$simm16 */
INT f_simm16;
SI * i_sr; SI * i_sr;
SI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -185,8 +180,8 @@ struct argbuf {
unsigned char in_src2; unsigned char in_src2;
} fmt_cmp; } fmt_cmp;
struct { /* e.g. cmpi $src2,$simm16 */ struct { /* e.g. cmpi $src2,$simm16 */
INT f_simm16;
SI * i_src2; SI * i_src2;
SI f_simm16;
unsigned char in_src2; unsigned char in_src2;
} fmt_cmpi; } fmt_cmpi;
struct { /* e.g. cmpz $src2 */ struct { /* e.g. cmpz $src2 */
@ -207,8 +202,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_ld; } fmt_ld;
struct { /* e.g. ld $dr,@($slo16,$sr) */ struct { /* e.g. ld $dr,@($slo16,$sr) */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -220,8 +215,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_ldb; } fmt_ldb;
struct { /* e.g. ldb $dr,@($slo16,$sr) */ struct { /* e.g. ldb $dr,@($slo16,$sr) */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -233,8 +228,8 @@ struct argbuf {
unsigned char out_dr; unsigned char out_dr;
} fmt_ldh; } fmt_ldh;
struct { /* e.g. ldh $dr,@($slo16,$sr) */ struct { /* e.g. ldh $dr,@($slo16,$sr) */
INT f_simm16;
SI * i_sr; SI * i_sr;
HI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
@ -247,17 +242,17 @@ struct argbuf {
unsigned char out_sr; unsigned char out_sr;
} fmt_ld_plus; } fmt_ld_plus;
struct { /* e.g. ld24 $dr,$uimm24 */ struct { /* e.g. ld24 $dr,$uimm24 */
ADDR f_uimm24; ADDR i_uimm24;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_ld24; } fmt_ld24;
struct { /* e.g. ldi8 $dr,$simm8 */ struct { /* e.g. ldi8 $dr,$simm8 */
SI f_simm8; INT f_simm8;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_ldi8; } fmt_ldi8;
struct { /* e.g. ldi16 $dr,$hash$slo16 */ struct { /* e.g. ldi16 $dr,$hash$slo16 */
HI f_simm16; INT f_simm16;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_ldi16; } fmt_ldi16;
@ -275,9 +270,9 @@ struct argbuf {
unsigned char in_src2; unsigned char in_src2;
} fmt_machi_a; } fmt_machi_a;
struct { /* e.g. mulhi $src1,$src2,$acc */ struct { /* e.g. mulhi $src1,$src2,$acc */
UINT f_acc;
SI * i_src1; SI * i_src1;
SI * i_src2; SI * i_src2;
UINT f_acc;
unsigned char in_src1; unsigned char in_src1;
unsigned char in_src2; unsigned char in_src2;
} fmt_mulhi_a; } fmt_mulhi_a;
@ -303,8 +298,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_mvtachi_a; } fmt_mvtachi_a;
struct { /* e.g. mvtc $sr,$dcr */ struct { /* e.g. mvtc $sr,$dcr */
SI * i_sr;
UINT f_r1; UINT f_r1;
SI * i_sr;
unsigned char in_sr; unsigned char in_sr;
} fmt_mvtc; } fmt_mvtc;
struct { /* e.g. nop */ struct { /* e.g. nop */
@ -312,24 +307,24 @@ struct argbuf {
} fmt_nop; } fmt_nop;
struct { /* e.g. rac $accd,$accs,$imm1 */ struct { /* e.g. rac $accd,$accs,$imm1 */
UINT f_accs; UINT f_accs;
USI f_imm1; SI f_imm1;
UINT f_accd; UINT f_accd;
} fmt_rac_dsi; } fmt_rac_dsi;
struct { /* e.g. seth $dr,$hash$hi16 */ struct { /* e.g. seth $dr,$hash$hi16 */
UHI f_hi16; UINT f_hi16;
SI * i_dr; SI * i_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_seth; } fmt_seth;
struct { /* e.g. sll3 $dr,$sr,$simm16 */ struct { /* e.g. sll3 $dr,$sr,$simm16 */
INT f_simm16;
SI * i_sr; SI * i_sr;
SI f_simm16;
SI * i_dr; SI * i_dr;
unsigned char in_sr; unsigned char in_sr;
unsigned char out_dr; unsigned char out_dr;
} fmt_sll3; } fmt_sll3;
struct { /* e.g. slli $dr,$uimm5 */ struct { /* e.g. slli $dr,$uimm5 */
UINT f_uimm5;
SI * i_dr; SI * i_dr;
USI f_uimm5;
unsigned char in_dr; unsigned char in_dr;
unsigned char out_dr; unsigned char out_dr;
} fmt_slli; } fmt_slli;
@ -340,8 +335,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_st; } fmt_st;
struct { /* e.g. st $src1,@($slo16,$src2) */ struct { /* e.g. st $src1,@($slo16,$src2) */
INT f_simm16;
SI * i_src2; SI * i_src2;
HI f_simm16;
SI * i_src1; SI * i_src1;
unsigned char in_src2; unsigned char in_src2;
unsigned char in_src1; unsigned char in_src1;
@ -353,8 +348,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_stb; } fmt_stb;
struct { /* e.g. stb $src1,@($slo16,$src2) */ struct { /* e.g. stb $src1,@($slo16,$src2) */
INT f_simm16;
SI * i_src2; SI * i_src2;
HI f_simm16;
SI * i_src1; SI * i_src1;
unsigned char in_src2; unsigned char in_src2;
unsigned char in_src1; unsigned char in_src1;
@ -366,8 +361,8 @@ struct argbuf {
unsigned char in_src1; unsigned char in_src1;
} fmt_sth; } fmt_sth;
struct { /* e.g. sth $src1,@($slo16,$src2) */ struct { /* e.g. sth $src1,@($slo16,$src2) */
INT f_simm16;
SI * i_src2; SI * i_src2;
HI f_simm16;
SI * i_src1; SI * i_src1;
unsigned char in_src2; unsigned char in_src2;
unsigned char in_src1; unsigned char in_src1;
@ -422,44 +417,44 @@ struct argbuf {
struct { struct {
union { union {
struct { /* e.g. bc.s $disp8 */ struct { /* e.g. bc.s $disp8 */
IADDR f_disp8; IADDR i_disp8;
} fmt_bc8; } fmt_bc8;
struct { /* e.g. bc.l $disp24 */ struct { /* e.g. bc.l $disp24 */
IADDR f_disp24; IADDR i_disp24;
} fmt_bc24; } fmt_bc24;
struct { /* e.g. beq $src1,$src2,$disp16 */ struct { /* e.g. beq $src1,$src2,$disp16 */
SI * i_src1; SI * i_src1;
SI * i_src2; SI * i_src2;
IADDR f_disp16; IADDR i_disp16;
unsigned char in_src1; unsigned char in_src1;
unsigned char in_src2; unsigned char in_src2;
} fmt_beq; } fmt_beq;
struct { /* e.g. beqz $src2,$disp16 */ struct { /* e.g. beqz $src2,$disp16 */
SI * i_src2; SI * i_src2;
IADDR f_disp16; IADDR i_disp16;
unsigned char in_src2; unsigned char in_src2;
} fmt_beqz; } fmt_beqz;
struct { /* e.g. bl.s $disp8 */ struct { /* e.g. bl.s $disp8 */
IADDR f_disp8; IADDR i_disp8;
unsigned char out_h_gr_14; unsigned char out_h_gr_14;
} fmt_bl8; } fmt_bl8;
struct { /* e.g. bl.l $disp24 */ struct { /* e.g. bl.l $disp24 */
IADDR f_disp24; IADDR i_disp24;
unsigned char out_h_gr_14; unsigned char out_h_gr_14;
} fmt_bl24; } fmt_bl24;
struct { /* e.g. bcl.s $disp8 */ struct { /* e.g. bcl.s $disp8 */
IADDR f_disp8; IADDR i_disp8;
unsigned char out_h_gr_14; unsigned char out_h_gr_14;
} fmt_bcl8; } fmt_bcl8;
struct { /* e.g. bcl.l $disp24 */ struct { /* e.g. bcl.l $disp24 */
IADDR f_disp24; IADDR i_disp24;
unsigned char out_h_gr_14; unsigned char out_h_gr_14;
} fmt_bcl24; } fmt_bcl24;
struct { /* e.g. bra.s $disp8 */ struct { /* e.g. bra.s $disp8 */
IADDR f_disp8; IADDR i_disp8;
} fmt_bra8; } fmt_bra8;
struct { /* e.g. bra.l $disp24 */ struct { /* e.g. bra.l $disp24 */
IADDR f_disp24; IADDR i_disp24;
} fmt_bra24; } fmt_bra24;
struct { /* e.g. jc $sr */ struct { /* e.g. jc $sr */
SI * i_sr; SI * i_sr;
@ -478,17 +473,17 @@ struct argbuf {
int empty; int empty;
} fmt_rte; } fmt_rte;
struct { /* e.g. trap $uimm4 */ struct { /* e.g. trap $uimm4 */
USI f_uimm4; UINT f_uimm4;
} fmt_trap; } fmt_trap;
struct { /* e.g. sc */ struct { /* e.g. sc */
int empty; int empty;
} fmt_sc; } fmt_sc;
} fields; } fields;
#if WITH_SCACHE_PBB_M32RXF #if WITH_SCACHE_PBB
SEM_PC addr_cache; SEM_PC addr_cache;
#endif #endif
} cti; } cti;
#if WITH_SCACHE_PBB_M32RXF #if WITH_SCACHE_PBB
/* Writeback handler. */ /* Writeback handler. */
struct { struct {
/* Pointer to argbuf entry for insn whose results need writing back. */ /* Pointer to argbuf entry for insn whose results need writing back. */
@ -527,6 +522,12 @@ struct scache {
/* Macros to simplify extraction, reading and semantic code. /* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */ These define and assign the local vars that contain the insn's fields. */
#define EXTRACT_FMT_EMPTY_VARS \
/* Instruction fields. */ \
unsigned int length;
#define EXTRACT_FMT_EMPTY_CODE \
length = 0; \
#define EXTRACT_FMT_ADD_VARS \ #define EXTRACT_FMT_ADD_VARS \
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
@ -649,7 +650,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp8; \ SI f_disp8; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BC8_CODE \ #define EXTRACT_FMT_BC8_CODE \
length = 2; \ length = 2; \
@ -661,7 +662,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp24; \ SI f_disp24; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BC24_CODE \ #define EXTRACT_FMT_BC24_CODE \
length = 4; \ length = 4; \
@ -675,7 +676,7 @@ struct scache {
UINT f_r1; \ UINT f_r1; \
UINT f_op2; \ UINT f_op2; \
UINT f_r2; \ UINT f_r2; \
INT f_disp16; \ SI f_disp16; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BEQ_CODE \ #define EXTRACT_FMT_BEQ_CODE \
length = 4; \ length = 4; \
@ -691,7 +692,7 @@ struct scache {
UINT f_r1; \ UINT f_r1; \
UINT f_op2; \ UINT f_op2; \
UINT f_r2; \ UINT f_r2; \
INT f_disp16; \ SI f_disp16; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BEQZ_CODE \ #define EXTRACT_FMT_BEQZ_CODE \
length = 4; \ length = 4; \
@ -705,7 +706,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp8; \ SI f_disp8; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BL8_CODE \ #define EXTRACT_FMT_BL8_CODE \
length = 2; \ length = 2; \
@ -717,7 +718,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp24; \ SI f_disp24; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BL24_CODE \ #define EXTRACT_FMT_BL24_CODE \
length = 4; \ length = 4; \
@ -729,7 +730,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp8; \ SI f_disp8; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BCL8_CODE \ #define EXTRACT_FMT_BCL8_CODE \
length = 2; \ length = 2; \
@ -741,7 +742,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp24; \ SI f_disp24; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BCL24_CODE \ #define EXTRACT_FMT_BCL24_CODE \
length = 4; \ length = 4; \
@ -753,7 +754,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp8; \ SI f_disp8; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BRA8_CODE \ #define EXTRACT_FMT_BRA8_CODE \
length = 2; \ length = 2; \
@ -765,7 +766,7 @@ struct scache {
/* Instruction fields. */ \ /* Instruction fields. */ \
UINT f_op1; \ UINT f_op1; \
UINT f_r1; \ UINT f_r1; \
INT f_disp24; \ SI f_disp24; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_BRA24_CODE \ #define EXTRACT_FMT_BRA24_CODE \
length = 4; \ length = 4; \
@ -1161,7 +1162,7 @@ struct scache {
UINT f_op2; \ UINT f_op2; \
UINT f_accs; \ UINT f_accs; \
UINT f_bit14; \ UINT f_bit14; \
UINT f_imm1; \ SI f_imm1; \
unsigned int length; unsigned int length;
#define EXTRACT_FMT_RAC_DSI_CODE \ #define EXTRACT_FMT_RAC_DSI_CODE \
length = 2; \ length = 2; \
@ -1471,6 +1472,9 @@ struct scache {
struct parexec { struct parexec {
union { union {
struct { /* empty format for unspecified field list */
int empty;
} fmt_empty;
struct { /* e.g. add $dr,$sr */ struct { /* e.g. add $dr,$sr */
SI dr; SI dr;
} fmt_add; } fmt_add;

138
sim/m32r/decode.c
View file

@ -22,7 +22,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
*/ */
#define WANT_CPU #define WANT_CPU m32rbf
#define WANT_CPU_M32RBF #define WANT_CPU_M32RBF
#include "sim-main.h" #include "sim-main.h"
@ -258,20 +258,20 @@ m32rbf_init_idesc_table (SIM_CPU *cpu)
/* Enum declaration for all instruction formats. */ /* Enum declaration for all instruction formats. */
typedef enum ifmt { typedef enum ifmt {
FMT_ADD, FMT_ADD3, FMT_AND3, FMT_OR3 FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3
, FMT_ADDI, FMT_ADDV, FMT_ADDV3, FMT_ADDX , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3
, FMT_BC8, FMT_BC24, FMT_BEQ, FMT_BEQZ , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ
, FMT_BL8, FMT_BL24, FMT_BRA8, FMT_BRA24 , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BRA8
, FMT_CMP, FMT_CMPI, FMT_DIV, FMT_JL , FMT_BRA24, FMT_CMP, FMT_CMPI, FMT_DIV
, FMT_JMP, FMT_LD, FMT_LD_D, FMT_LDB , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D
, FMT_LDB_D, FMT_LDH, FMT_LDH_D, FMT_LD_PLUS , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D
, FMT_LD24, FMT_LDI8, FMT_LDI16, FMT_LOCK , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16
, FMT_MACHI, FMT_MULHI, FMT_MV, FMT_MVFACHI , FMT_LOCK, FMT_MACHI, FMT_MULHI, FMT_MV
, FMT_MVFC, FMT_MVTACHI, FMT_MVTC, FMT_NOP , FMT_MVFACHI, FMT_MVFC, FMT_MVTACHI, FMT_MVTC
, FMT_RAC, FMT_RTE, FMT_SETH, FMT_SLL3 , FMT_NOP, FMT_RAC, FMT_RTE, FMT_SETH
, FMT_SLLI, FMT_ST, FMT_ST_D, FMT_STB , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D
, FMT_STB_D, FMT_STH, FMT_STH_D, FMT_ST_PLUS , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D
, FMT_TRAP, FMT_UNLOCK , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK
} IFMT; } IFMT;
/* The decoder uses this to record insns and direct extraction handling. */ /* The decoder uses this to record insns and direct extraction handling. */
@ -668,6 +668,21 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
#endif #endif
{ {
CASE (ex, FMT_EMPTY) :
{
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.fmt_empty.f
EXTRACT_FMT_EMPTY_VARS /* */
EXTRACT_FMT_EMPTY_CODE
/* Record the fields for the semantic handler. */
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
#undef FLD
BREAK (ex);
}
CASE (ex, FMT_ADD) : CASE (ex, FMT_ADD) :
{ {
CGEN_INSN_INT insn = entire_insn; CGEN_INSN_INT insn = entire_insn;
@ -703,10 +718,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ADD3_CODE EXTRACT_FMT_ADD3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -729,10 +744,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_AND3_CODE EXTRACT_FMT_AND3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_uimm16) = f_uimm16; FLD (f_uimm16) = f_uimm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "sr 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -755,10 +770,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_OR3_CODE EXTRACT_FMT_OR3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_uimm16) = f_uimm16; FLD (f_uimm16) = f_uimm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "sr 0x%x", 'x', f_r2, "ulo16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -781,9 +796,9 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ADDI_CODE EXTRACT_FMT_ADDI_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_dr) = & CPU (h_gr)[f_r1];
FLD (f_simm8) = f_simm8; FLD (f_simm8) = f_simm8;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "dr 0x%x", 'x', f_r1, "simm8 0x%x", 'x', f_simm8, (char *) 0)); FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -832,10 +847,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ADDV3_CODE EXTRACT_FMT_ADDV3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -884,7 +899,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BC8_CODE EXTRACT_FMT_BC8_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp8) = f_disp8; FLD (i_disp8) = f_disp8;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
@ -907,7 +922,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BC24_CODE EXTRACT_FMT_BC24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp24) = f_disp24; FLD (i_disp24) = f_disp24;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
@ -932,7 +947,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_disp16) = f_disp16; FLD (i_disp16) = f_disp16;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
@ -958,7 +973,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_disp16) = f_disp16; FLD (i_disp16) = f_disp16;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
@ -982,7 +997,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BL8_CODE EXTRACT_FMT_BL8_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp8) = f_disp8; FLD (i_disp8) = f_disp8;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
@ -1006,7 +1021,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BL24_CODE EXTRACT_FMT_BL24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp24) = f_disp24; FLD (i_disp24) = f_disp24;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
@ -1030,7 +1045,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BRA8_CODE EXTRACT_FMT_BRA8_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp8) = f_disp8; FLD (i_disp8) = f_disp8;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
@ -1053,7 +1068,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BRA24_CODE EXTRACT_FMT_BRA24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp24) = f_disp24; FLD (i_disp24) = f_disp24;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
@ -1101,9 +1116,9 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_CMPI_CODE EXTRACT_FMT_CMPI_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "src2 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0)); FLD (i_src2) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1225,10 +1240,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LD_D_CODE EXTRACT_FMT_LD_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1276,10 +1291,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LDB_D_CODE EXTRACT_FMT_LDB_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1327,10 +1342,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LDH_D_CODE EXTRACT_FMT_LDH_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1379,7 +1394,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LD24_CODE EXTRACT_FMT_LD24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_uimm24) = f_uimm24; FLD (i_uimm24) = f_uimm24;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
@ -1405,7 +1420,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_simm8) = f_simm8; FLD (f_simm8) = f_simm8;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1429,7 +1444,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1576,7 +1591,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2; FLD (f_r2) = f_r2;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "scr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1621,9 +1636,9 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_MVTC_CODE EXTRACT_FMT_MVTC_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_r1) = f_r1; FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "sr 0x%x", 'x', f_r2, "dcr 0x%x", 'x', f_r1, (char *) 0)); FLD (i_sr) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1699,7 +1714,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_hi16) = f_hi16; FLD (f_hi16) = f_hi16;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1721,10 +1736,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_SLL3_CODE EXTRACT_FMT_SLL3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1747,9 +1762,9 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_SLLI_CODE EXTRACT_FMT_SLLI_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_dr) = & CPU (h_gr)[f_r1];
FLD (f_uimm5) = f_uimm5; FLD (f_uimm5) = f_uimm5;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0)); FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1797,10 +1812,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ST_D_CODE EXTRACT_FMT_ST_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1848,10 +1863,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_STB_D_CODE EXTRACT_FMT_STB_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1899,10 +1914,10 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_STH_D_CODE EXTRACT_FMT_STH_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1953,7 +1968,7 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_uimm4) = f_uimm4; FLD (f_uimm4) = f_uimm4;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1990,12 +2005,11 @@ m32rbf_decode (SIM_CPU *current_cpu, PCADDR pc,
BREAK (ex); BREAK (ex);
} }
CASE (ex, FMT_EMPTY) :
BREAK (ex);
} }
ENDSWITCH (ex) ENDSWITCH (ex)
return idecode->idesc;
} }
return idecode->idesc;
} }

160
sim/m32r/decodex.c
View file

@ -22,7 +22,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
*/ */
#define WANT_CPU #define WANT_CPU m32rxf
#define WANT_CPU_M32RXF #define WANT_CPU_M32RXF
#include "sim-main.h" #include "sim-main.h"
@ -304,23 +304,23 @@ m32rxf_init_idesc_table (SIM_CPU *cpu)
/* Enum declaration for all instruction formats. */ /* Enum declaration for all instruction formats. */
typedef enum ifmt { typedef enum ifmt {
FMT_ADD, FMT_ADD3, FMT_AND3, FMT_OR3 FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3
, FMT_ADDI, FMT_ADDV, FMT_ADDV3, FMT_ADDX , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3
, FMT_BC8, FMT_BC24, FMT_BEQ, FMT_BEQZ , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ
, FMT_BL8, FMT_BL24, FMT_BCL8, FMT_BCL24 , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BCL8
, FMT_BRA8, FMT_BRA24, FMT_CMP, FMT_CMPI , FMT_BCL24, FMT_BRA8, FMT_BRA24, FMT_CMP
, FMT_CMPZ, FMT_DIV, FMT_JC, FMT_JL , FMT_CMPI, FMT_CMPZ, FMT_DIV, FMT_JC
, FMT_JMP, FMT_LD, FMT_LD_D, FMT_LDB , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D
, FMT_LDB_D, FMT_LDH, FMT_LDH_D, FMT_LD_PLUS , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D
, FMT_LD24, FMT_LDI8, FMT_LDI16, FMT_LOCK , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16
, FMT_MACHI_A, FMT_MULHI_A, FMT_MV, FMT_MVFACHI_A , FMT_LOCK, FMT_MACHI_A, FMT_MULHI_A, FMT_MV
, FMT_MVFC, FMT_MVTACHI_A, FMT_MVTC, FMT_NOP , FMT_MVFACHI_A, FMT_MVFC, FMT_MVTACHI_A, FMT_MVTC
, FMT_RAC_DSI, FMT_RTE, FMT_SETH, FMT_SLL3 , FMT_NOP, FMT_RAC_DSI, FMT_RTE, FMT_SETH
, FMT_SLLI, FMT_ST, FMT_ST_D, FMT_STB , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D
, FMT_STB_D, FMT_STH, FMT_STH_D, FMT_ST_PLUS , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D
, FMT_TRAP, FMT_UNLOCK, FMT_SATB, FMT_SAT , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK, FMT_SATB
, FMT_SADD, FMT_MACWU1, FMT_MSBLO, FMT_MULWU1 , FMT_SAT, FMT_SADD, FMT_MACWU1, FMT_MSBLO
, FMT_SC , FMT_MULWU1, FMT_SC
} IFMT; } IFMT;
/* The decoder uses this to record insns and direct extraction handling. */ /* The decoder uses this to record insns and direct extraction handling. */
@ -847,6 +847,21 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
#endif #endif
{ {
CASE (ex, FMT_EMPTY) :
{
CGEN_INSN_INT insn = entire_insn;
#define FLD(f) abuf->fields.fmt_empty.f
EXTRACT_FMT_EMPTY_VARS /* */
EXTRACT_FMT_EMPTY_CODE
/* Record the fields for the semantic handler. */
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
#undef FLD
BREAK (ex);
}
CASE (ex, FMT_ADD) : CASE (ex, FMT_ADD) :
{ {
CGEN_INSN_INT insn = entire_insn; CGEN_INSN_INT insn = entire_insn;
@ -882,10 +897,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ADD3_CODE EXTRACT_FMT_ADD3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -908,10 +923,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_AND3_CODE EXTRACT_FMT_AND3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_uimm16) = f_uimm16; FLD (f_uimm16) = f_uimm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "sr 0x%x", 'x', f_r2, "uimm16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -934,10 +949,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_OR3_CODE EXTRACT_FMT_OR3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_uimm16) = f_uimm16; FLD (f_uimm16) = f_uimm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "sr 0x%x", 'x', f_r2, "ulo16 0x%x", 'x', f_uimm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -960,9 +975,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ADDI_CODE EXTRACT_FMT_ADDI_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_dr) = & CPU (h_gr)[f_r1];
FLD (f_simm8) = f_simm8; FLD (f_simm8) = f_simm8;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "dr 0x%x", 'x', f_r1, "simm8 0x%x", 'x', f_simm8, (char *) 0)); FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1011,10 +1026,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ADDV3_CODE EXTRACT_FMT_ADDV3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1063,7 +1078,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BC8_CODE EXTRACT_FMT_BC8_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp8) = f_disp8; FLD (i_disp8) = f_disp8;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
@ -1086,7 +1101,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BC24_CODE EXTRACT_FMT_BC24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp24) = f_disp24; FLD (i_disp24) = f_disp24;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
@ -1111,7 +1126,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_disp16) = f_disp16; FLD (i_disp16) = f_disp16;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
@ -1137,7 +1152,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_disp16) = f_disp16; FLD (i_disp16) = f_disp16;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "src2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, (char *) 0));
@ -1161,7 +1176,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BL8_CODE EXTRACT_FMT_BL8_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp8) = f_disp8; FLD (i_disp8) = f_disp8;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
@ -1185,7 +1200,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BL24_CODE EXTRACT_FMT_BL24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp24) = f_disp24; FLD (i_disp24) = f_disp24;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
@ -1209,7 +1224,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BCL8_CODE EXTRACT_FMT_BCL8_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp8) = f_disp8; FLD (i_disp8) = f_disp8;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
@ -1233,7 +1248,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BCL24_CODE EXTRACT_FMT_BCL24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp24) = f_disp24; FLD (i_disp24) = f_disp24;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
@ -1257,7 +1272,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BRA8_CODE EXTRACT_FMT_BRA8_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp8) = f_disp8; FLD (i_disp8) = f_disp8;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
@ -1280,7 +1295,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_BRA24_CODE EXTRACT_FMT_BRA24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_disp24) = f_disp24; FLD (i_disp24) = f_disp24;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
@ -1328,9 +1343,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_CMPI_CODE EXTRACT_FMT_CMPI_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "src2 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, (char *) 0)); FLD (i_src2) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1499,10 +1514,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LD_D_CODE EXTRACT_FMT_LD_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1550,10 +1565,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LDB_D_CODE EXTRACT_FMT_LDB_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1601,10 +1616,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LDH_D_CODE EXTRACT_FMT_LDH_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "sr 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1653,7 +1668,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_LD24_CODE EXTRACT_FMT_LD24_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_uimm24) = f_uimm24; FLD (i_uimm24) = f_uimm24;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
@ -1679,7 +1694,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_simm8) = f_simm8; FLD (f_simm8) = f_simm8;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1703,7 +1718,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "slo16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1753,7 +1768,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
FLD (f_acc) = f_acc; FLD (f_acc) = f_acc;
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src2) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi_a", "acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1776,10 +1791,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_MULHI_A_CODE EXTRACT_FMT_MULHI_A_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_acc) = f_acc;
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
FLD (i_src2) = & CPU (h_gr)[f_r2]; FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_acc) = f_acc; TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi_a", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, "acc 0x%x", 'x', f_acc, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1829,7 +1844,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_accs) = f_accs; FLD (f_accs) = f_accs;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi_a", "accs 0x%x", 'x', f_accs, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1853,7 +1868,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2; FLD (f_r2) = f_r2;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "scr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1877,7 +1892,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_accs) = f_accs; FLD (f_accs) = f_accs;
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi_a", "accs 0x%x", 'x', f_accs, "src1 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "src1 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1899,9 +1914,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_MVTC_CODE EXTRACT_FMT_MVTC_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_r1) = f_r1; FLD (f_r1) = f_r1;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "sr 0x%x", 'x', f_r2, "dcr 0x%x", 'x', f_r1, (char *) 0)); FLD (i_sr) = & CPU (h_gr)[f_r2];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -1941,7 +1956,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
FLD (f_accs) = f_accs; FLD (f_accs) = f_accs;
FLD (f_imm1) = f_imm1; FLD (f_imm1) = f_imm1;
FLD (f_accd) = f_accd; FLD (f_accd) = f_accd;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac_dsi", "accs 0x%x", 'x', f_accs, "imm1 0x%x", 'x', f_imm1, "accd 0x%x", 'x', f_accd, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
#undef FLD #undef FLD
BREAK (ex); BREAK (ex);
@ -1980,7 +1995,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_hi16) = f_hi16; FLD (f_hi16) = f_hi16;
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -2002,10 +2017,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_SLL3_CODE EXTRACT_FMT_SLL3_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_sr) = & CPU (h_gr)[f_r2];
FLD (i_dr) = & CPU (h_gr)[f_r1]; FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "sr 0x%x", 'x', f_r2, "simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -2028,9 +2043,9 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_SLLI_CODE EXTRACT_FMT_SLLI_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_dr) = & CPU (h_gr)[f_r1];
FLD (f_uimm5) = f_uimm5; FLD (f_uimm5) = f_uimm5;
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "dr 0x%x", 'x', f_r1, "uimm5 0x%x", 'x', f_uimm5, (char *) 0)); FLD (i_dr) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -2078,10 +2093,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_ST_D_CODE EXTRACT_FMT_ST_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -2129,10 +2144,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_STB_D_CODE EXTRACT_FMT_STB_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -2180,10 +2195,10 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
EXTRACT_FMT_STH_D_CODE EXTRACT_FMT_STH_D_CODE
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (f_simm16) = f_simm16; FLD (f_simm16) = f_simm16;
FLD (i_src2) = & CPU (h_gr)[f_r2];
FLD (i_src1) = & CPU (h_gr)[f_r1]; FLD (i_src1) = & CPU (h_gr)[f_r1];
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "src2 0x%x", 'x', f_r2, "slo16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -2234,7 +2249,7 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
/* Record the fields for the semantic handler. */ /* Record the fields for the semantic handler. */
FLD (f_uimm4) = f_uimm4; FLD (f_uimm4) = f_uimm4;
SEM_BRANCH_INIT_EXTRACT (abuf); SEM_BRANCH_INIT_EXTRACT (abuf);
TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "uimm4 0x%x", 'x', f_uimm4, (char *) 0)); TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
#if WITH_PROFILE_MODEL_P #if WITH_PROFILE_MODEL_P
/* Record the fields for profiling. */ /* Record the fields for profiling. */
@ -2427,12 +2442,11 @@ m32rxf_decode (SIM_CPU *current_cpu, PCADDR pc,
BREAK (ex); BREAK (ex);
} }
CASE (ex, FMT_EMPTY) :
BREAK (ex);
} }
ENDSWITCH (ex) ENDSWITCH (ex)
return idecode->idesc;
} }
return idecode->idesc;
} }

4341
sim/m32r/model.c
View file

File diff suppressed because it is too large Load diff

2960
sim/m32r/modelx.c
View file

File diff suppressed because it is too large Load diff

92
sim/m32r/sem-switch.c
View file

@ -225,7 +225,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
m32rbf_pbb_after (current_cpu, sem_arg); m32rbf_pbb_after (current_cpu, sem_arg);
#endif #endif
} }
@ -244,7 +244,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
m32rbf_pbb_before (current_cpu, sem_arg); m32rbf_pbb_before (current_cpu, sem_arg);
#endif #endif
} }
@ -263,7 +263,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
pbb_br_npc_ptr, pbb_br_npc); pbb_br_npc_ptr, pbb_br_npc);
@ -291,7 +291,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
vpc = m32rbf_pbb_chain (current_cpu, sem_arg); vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
BREAK (sem); BREAK (sem);
@ -313,7 +313,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
/* In the switch case FAST_P is a constant, allowing several optimizations /* In the switch case FAST_P is a constant, allowing several optimizations
in any called inline functions. */ in any called inline functions. */
@ -606,7 +606,7 @@ if (CPU (h_cond)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -631,7 +631,7 @@ if (CPU (h_cond)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -656,7 +656,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -681,7 +681,7 @@ if (EQSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -706,7 +706,7 @@ if (GESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -731,7 +731,7 @@ if (GTSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -756,7 +756,7 @@ if (LESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -781,7 +781,7 @@ if (LTSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -806,7 +806,7 @@ if (NESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -834,7 +834,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -862,7 +862,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -887,7 +887,7 @@ if (NOTBI (CPU (h_cond))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -912,7 +912,7 @@ if (NOTBI (CPU (h_cond))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -937,7 +937,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -958,7 +958,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -979,7 +979,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1178,7 +1178,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1199,7 +1199,7 @@ do {
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1214,7 +1214,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1233,7 +1233,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))); SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1252,7 +1252,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1271,7 +1271,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1290,7 +1290,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1309,7 +1309,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1328,7 +1328,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1347,7 +1347,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1366,7 +1366,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1385,7 +1385,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1405,7 +1405,7 @@ do {
do { do {
SI temp1;SI temp0; SI temp1;SI temp0;
temp0 = GETMEMSI (current_cpu, * FLD (i_sr)); temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4); temp1 = ADDSI (* FLD (i_sr), 4);
{ {
SI opval = temp0; SI opval = temp0;
@ -1496,7 +1496,7 @@ do {
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
} }
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1972,7 +1972,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -2178,7 +2178,7 @@ do {
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, * FLD (i_src2), opval); SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2197,7 +2197,7 @@ do {
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2216,7 +2216,7 @@ do {
{ {
QI opval = * FLD (i_src1); QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, * FLD (i_src2), opval); SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2235,7 +2235,7 @@ do {
{ {
QI opval = * FLD (i_src1); QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2254,7 +2254,7 @@ do {
{ {
HI opval = * FLD (i_src1); HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, * FLD (i_src2), opval); SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2273,7 +2273,7 @@ do {
{ {
HI opval = * FLD (i_src1); HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2295,7 +2295,7 @@ do {
tmp_new_src2 = ADDSI (* FLD (i_src2), 4); tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, tmp_new_src2, opval); SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
{ {
@ -2323,7 +2323,7 @@ do {
tmp_new_src2 = SUBSI (* FLD (i_src2), 4); tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, tmp_new_src2, opval); SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
{ {
@ -2457,7 +2457,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -2475,7 +2475,7 @@ do {
if (CPU (h_lock)) { if (CPU (h_lock)) {
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, * FLD (i_src2), opval); SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
written |= (1 << 3); written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }

94
sim/m32r/sem.c
View file

@ -22,7 +22,7 @@ with this program; if not, write to the Free Software Foundation, Inc.,
*/ */
#define WANT_CPU #define WANT_CPU m32rbf
#define WANT_CPU_M32RBF #define WANT_CPU_M32RBF
#include "sim-main.h" #include "sim-main.h"
@ -69,7 +69,7 @@ SEM_FN_NAME (m32rbf,x_after) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
m32rbf_pbb_after (current_cpu, sem_arg); m32rbf_pbb_after (current_cpu, sem_arg);
#endif #endif
} }
@ -90,7 +90,7 @@ SEM_FN_NAME (m32rbf,x_before) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
m32rbf_pbb_before (current_cpu, sem_arg); m32rbf_pbb_before (current_cpu, sem_arg);
#endif #endif
} }
@ -111,7 +111,7 @@ SEM_FN_NAME (m32rbf,x_cti_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg, vpc = m32rbf_pbb_cti_chain (current_cpu, sem_arg,
pbb_br_npc_ptr, pbb_br_npc); pbb_br_npc_ptr, pbb_br_npc);
@ -141,7 +141,7 @@ SEM_FN_NAME (m32rbf,x_chain) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
vpc = m32rbf_pbb_chain (current_cpu, sem_arg); vpc = m32rbf_pbb_chain (current_cpu, sem_arg);
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
BREAK (sem); BREAK (sem);
@ -165,7 +165,7 @@ SEM_FN_NAME (m32rbf,x_begin) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RBF
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
/* In the switch case FAST_P is a constant, allowing several optimizations /* In the switch case FAST_P is a constant, allowing several optimizations
in any called inline functions. */ in any called inline functions. */
@ -484,7 +484,7 @@ if (CPU (h_cond)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -511,7 +511,7 @@ if (CPU (h_cond)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -538,7 +538,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -565,7 +565,7 @@ if (EQSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -592,7 +592,7 @@ if (GESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -619,7 +619,7 @@ if (GTSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -646,7 +646,7 @@ if (LESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -673,7 +673,7 @@ if (LTSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -700,7 +700,7 @@ if (NESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -730,7 +730,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -760,7 +760,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -787,7 +787,7 @@ if (NOTBI (CPU (h_cond))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -814,7 +814,7 @@ if (NOTBI (CPU (h_cond))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -841,7 +841,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -864,7 +864,7 @@ SEM_FN_NAME (m32rbf,bra8) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -887,7 +887,7 @@ SEM_FN_NAME (m32rbf,bra24) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -1104,7 +1104,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -1127,7 +1127,7 @@ SEM_FN_NAME (m32rbf,jmp) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -1144,7 +1144,7 @@ SEM_FN_NAME (m32rbf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1165,7 +1165,7 @@ SEM_FN_NAME (m32rbf,ld_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))); SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1186,7 +1186,7 @@ SEM_FN_NAME (m32rbf,ldb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1207,7 +1207,7 @@ SEM_FN_NAME (m32rbf,ldb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1228,7 +1228,7 @@ SEM_FN_NAME (m32rbf,ldh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1249,7 +1249,7 @@ SEM_FN_NAME (m32rbf,ldh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1270,7 +1270,7 @@ SEM_FN_NAME (m32rbf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1291,7 +1291,7 @@ SEM_FN_NAME (m32rbf,ldub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1312,7 +1312,7 @@ SEM_FN_NAME (m32rbf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1333,7 +1333,7 @@ SEM_FN_NAME (m32rbf,lduh_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4); SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1355,7 +1355,7 @@ SEM_FN_NAME (m32rbf,ld_plus) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
do { do {
SI temp1;SI temp0; SI temp1;SI temp0;
temp0 = GETMEMSI (current_cpu, * FLD (i_sr)); temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4); temp1 = ADDSI (* FLD (i_sr), 4);
{ {
SI opval = temp0; SI opval = temp0;
@ -1454,7 +1454,7 @@ do {
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
} }
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1976,7 +1976,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -2204,7 +2204,7 @@ SEM_FN_NAME (m32rbf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, * FLD (i_src2), opval); SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2225,7 +2225,7 @@ SEM_FN_NAME (m32rbf,st_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2246,7 +2246,7 @@ SEM_FN_NAME (m32rbf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{ {
QI opval = * FLD (i_src1); QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, * FLD (i_src2), opval); SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2267,7 +2267,7 @@ SEM_FN_NAME (m32rbf,stb_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{ {
QI opval = * FLD (i_src1); QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2288,7 +2288,7 @@ SEM_FN_NAME (m32rbf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{ {
HI opval = * FLD (i_src1); HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, * FLD (i_src2), opval); SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2309,7 +2309,7 @@ SEM_FN_NAME (m32rbf,sth_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{ {
HI opval = * FLD (i_src1); HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2333,7 +2333,7 @@ do {
tmp_new_src2 = ADDSI (* FLD (i_src2), 4); tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, tmp_new_src2, opval); SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
{ {
@ -2363,7 +2363,7 @@ do {
tmp_new_src2 = SUBSI (* FLD (i_src2), 4); tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, tmp_new_src2, opval); SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
{ {
@ -2505,7 +2505,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
return vpc; return vpc;
#undef FLD #undef FLD
} }
@ -2525,7 +2525,7 @@ do {
if (CPU (h_lock)) { if (CPU (h_lock)) {
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, * FLD (i_src2), opval); SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
written |= (1 << 3); written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }

162
sim/m32r/semx-switch.c
View file

@ -397,7 +397,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RXF
m32rxf_pbb_after (current_cpu, sem_arg); m32rxf_pbb_after (current_cpu, sem_arg);
#endif #endif
} }
@ -416,7 +416,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RXF
m32rxf_pbb_before (current_cpu, sem_arg); m32rxf_pbb_before (current_cpu, sem_arg);
#endif #endif
} }
@ -435,7 +435,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RXF
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg, vpc = m32rxf_pbb_cti_chain (current_cpu, sem_arg,
pbb_br_npc_ptr, pbb_br_npc); pbb_br_npc_ptr, pbb_br_npc);
@ -463,7 +463,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RXF
vpc = m32rxf_pbb_chain (current_cpu, sem_arg); vpc = m32rxf_pbb_chain (current_cpu, sem_arg);
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
BREAK (sem); BREAK (sem);
@ -485,7 +485,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
{ {
#if WITH_SCACHE_PBB #if WITH_SCACHE_PBB_M32RXF
#ifdef DEFINE_SWITCH #ifdef DEFINE_SWITCH
/* In the switch case FAST_P is a constant, allowing several optimizations /* In the switch case FAST_P is a constant, allowing several optimizations
in any called inline functions. */ in any called inline functions. */
@ -778,7 +778,7 @@ if (CPU (h_cond)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -803,7 +803,7 @@ if (CPU (h_cond)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -828,7 +828,7 @@ if (EQSI (* FLD (i_src1), * FLD (i_src2))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -853,7 +853,7 @@ if (EQSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -878,7 +878,7 @@ if (GESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -903,7 +903,7 @@ if (GTSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -928,7 +928,7 @@ if (LESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -953,7 +953,7 @@ if (LTSI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -978,7 +978,7 @@ if (NESI (* FLD (i_src2), 0)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1006,7 +1006,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1034,7 +1034,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1067,7 +1067,7 @@ do {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1100,7 +1100,7 @@ do {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1125,7 +1125,7 @@ if (NOTBI (CPU (h_cond))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1150,7 +1150,7 @@ if (NOTBI (CPU (h_cond))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1175,7 +1175,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1196,7 +1196,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1217,7 +1217,7 @@ if (NESI (* FLD (i_src1), * FLD (i_src2))) {
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1250,7 +1250,7 @@ do {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1283,7 +1283,7 @@ do {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1537,7 +1537,7 @@ if (CPU (h_cond)) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1562,7 +1562,7 @@ if (NOTBI (CPU (h_cond))) {
} }
abuf->written = written; abuf->written = written;
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1593,7 +1593,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1614,7 +1614,7 @@ do {
TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -1629,7 +1629,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1648,7 +1648,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = GETMEMSI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16))); SI opval = GETMEMSI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1667,7 +1667,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1686,7 +1686,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = EXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = EXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1705,7 +1705,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1724,7 +1724,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = EXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = EXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1743,7 +1743,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1762,7 +1762,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = ZEXTQISI (GETMEMQI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1781,7 +1781,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1800,7 +1800,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4); vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{ {
SI opval = ZEXTHISI (GETMEMHI (current_cpu, ADDSI (* FLD (i_sr), FLD (f_simm16)))); SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, ADDSI (* FLD (i_sr), FLD (f_simm16))));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -1820,7 +1820,7 @@ do {
do { do {
SI temp1;SI temp0; SI temp1;SI temp0;
temp0 = GETMEMSI (current_cpu, * FLD (i_sr)); temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4); temp1 = ADDSI (* FLD (i_sr), 4);
{ {
SI opval = temp0; SI opval = temp0;
@ -1911,7 +1911,7 @@ do {
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
} }
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
* FLD (i_dr) = opval; * FLD (i_dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -2378,7 +2378,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -2584,7 +2584,7 @@ do {
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, * FLD (i_src2), opval); SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2603,7 +2603,7 @@ do {
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMSI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2622,7 +2622,7 @@ do {
{ {
QI opval = * FLD (i_src1); QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, * FLD (i_src2), opval); SETMEMQI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2641,7 +2641,7 @@ do {
{ {
QI opval = * FLD (i_src1); QI opval = * FLD (i_src1);
SETMEMQI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMQI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2660,7 +2660,7 @@ do {
{ {
HI opval = * FLD (i_src1); HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, * FLD (i_src2), opval); SETMEMHI (current_cpu, pc, * FLD (i_src2), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2679,7 +2679,7 @@ do {
{ {
HI opval = * FLD (i_src1); HI opval = * FLD (i_src1);
SETMEMHI (current_cpu, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval); SETMEMHI (current_cpu, pc, ADDSI (* FLD (i_src2), FLD (f_simm16)), opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -2701,7 +2701,7 @@ do {
tmp_new_src2 = ADDSI (* FLD (i_src2), 4); tmp_new_src2 = ADDSI (* FLD (i_src2), 4);
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, tmp_new_src2, opval); SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
{ {
@ -2729,7 +2729,7 @@ do {
tmp_new_src2 = SUBSI (* FLD (i_src2), 4); tmp_new_src2 = SUBSI (* FLD (i_src2), 4);
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, tmp_new_src2, opval); SETMEMSI (current_cpu, pc, tmp_new_src2, opval);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
{ {
@ -2863,7 +2863,7 @@ do {
} }
} while (0); } while (0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -2881,7 +2881,7 @@ do {
if (CPU (h_lock)) { if (CPU (h_lock)) {
{ {
SI opval = * FLD (i_src1); SI opval = * FLD (i_src1);
SETMEMSI (current_cpu, * FLD (i_src2), opval); SETMEMSI (current_cpu, pc, * FLD (i_src2), opval);
written |= (1 << 3); written |= (1 << 3);
TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
} }
@ -3083,7 +3083,7 @@ if (CPU (h_cond)) {
SEM_SKIP_INSN (current_cpu, 1); SEM_SKIP_INSN (current_cpu, 1);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -3102,7 +3102,7 @@ if (NOTBI (CPU (h_cond))) {
SEM_SKIP_INSN (current_cpu, 1); SEM_SKIP_INSN (current_cpu, 1);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef FLD #undef FLD
} }
NEXT (vpc); NEXT (vpc);
@ -3436,7 +3436,7 @@ if (CPU (h_cond)) {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3484,7 +3484,7 @@ do {
CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14); CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3543,7 +3543,7 @@ do {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3590,7 +3590,7 @@ if (NOTBI (CPU (h_cond))) {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3630,7 +3630,7 @@ if (NOTBI (CPU (h_cond))) {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3689,7 +3689,7 @@ do {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3888,7 +3888,7 @@ if (CPU (h_cond)) {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3935,7 +3935,7 @@ if (NOTBI (CPU (h_cond))) {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
} }
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -3986,7 +3986,7 @@ do {
CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14); CPU (h_gr[((UINT) 14)]) = OPRND (h_gr_14);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -4026,7 +4026,7 @@ do {
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -4043,7 +4043,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
OPRND (dr) = opval; OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -4081,7 +4081,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = EXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval; OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -4119,7 +4119,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = EXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = EXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval; OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -4157,7 +4157,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTQISI (GETMEMQI (current_cpu, * FLD (i_sr))); SI opval = ZEXTQISI (GETMEMQI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval; OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -4195,7 +4195,7 @@ do {
vpc = SEM_NEXT_VPC (sem_arg, pc, 2); vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
{ {
SI opval = ZEXTHISI (GETMEMHI (current_cpu, * FLD (i_sr))); SI opval = ZEXTHISI (GETMEMHI (current_cpu, pc, * FLD (i_sr)));
OPRND (dr) = opval; OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -4234,7 +4234,7 @@ do {
do { do {
SI temp1;SI temp0; SI temp1;SI temp0;
temp0 = GETMEMSI (current_cpu, * FLD (i_sr)); temp0 = GETMEMSI (current_cpu, pc, * FLD (i_sr));
temp1 = ADDSI (* FLD (i_sr), 4); temp1 = ADDSI (* FLD (i_sr), 4);
{ {
SI opval = temp0; SI opval = temp0;
@ -4326,7 +4326,7 @@ do {
TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval); TRACE_RESULT (current_cpu, abuf, "lock-0", 'x', opval);
} }
{ {
SI opval = GETMEMSI (current_cpu, * FLD (i_sr)); SI opval = GETMEMSI (current_cpu, pc, * FLD (i_sr));
OPRND (dr) = opval; OPRND (dr) = opval;
TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval); TRACE_RESULT (current_cpu, abuf, "dr", 'x', opval);
} }
@ -5250,7 +5250,7 @@ do {
m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0)); m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0));
CPU (h_bpsw) = OPRND (h_bpsw_0); CPU (h_bpsw) = OPRND (h_bpsw_0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -5516,7 +5516,7 @@ do {
PCADDR UNUSED pc = abuf->addr; PCADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMSI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
#undef OPRND #undef OPRND
#undef FLD #undef FLD
@ -5555,7 +5555,7 @@ do {
PCADDR UNUSED pc = abuf->addr; PCADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMQI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); SETMEMQI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
#undef OPRND #undef OPRND
#undef FLD #undef FLD
@ -5594,7 +5594,7 @@ do {
PCADDR UNUSED pc = abuf->addr; PCADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMHI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); SETMEMHI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
#undef OPRND #undef OPRND
#undef FLD #undef FLD
@ -5642,7 +5642,7 @@ do {
PCADDR UNUSED pc = abuf->addr; PCADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMSI (current_cpu, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2)); SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
* FLD (i_src2) = OPRND (src2); * FLD (i_src2) = OPRND (src2);
#undef OPRND #undef OPRND
@ -5691,7 +5691,7 @@ do {
PCADDR UNUSED pc = abuf->addr; PCADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SETMEMSI (current_cpu, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2)); SETMEMSI (current_cpu, pc, OPRND (h_memory_new_src2_idx), OPRND (h_memory_new_src2));
* FLD (i_src2) = OPRND (src2); * FLD (i_src2) = OPRND (src2);
#undef OPRND #undef OPRND
@ -5901,7 +5901,7 @@ do {
m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0)); m32rxf_h_psw_set (current_cpu, OPRND (h_psw_0));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc); SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, OPRND (pc), vpc);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -5952,7 +5952,7 @@ if (CPU (h_lock)) {
if (written & (1 << 3)) if (written & (1 << 3))
{ {
SETMEMSI (current_cpu, OPRND (h_memory_src2_idx), OPRND (h_memory_src2)); SETMEMSI (current_cpu, pc, OPRND (h_memory_src2_idx), OPRND (h_memory_src2));
} }
CPU (h_lock) = OPRND (h_lock_0); CPU (h_lock) = OPRND (h_lock_0);
@ -6220,7 +6220,7 @@ SEM_SKIP_INSN (current_cpu, 1);
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }
@ -6257,7 +6257,7 @@ SEM_SKIP_INSN (current_cpu, 1);
vpc = SEM_NEXT_VPC (sem_arg, pc, 0); vpc = SEM_NEXT_VPC (sem_arg, pc, 0);
SEM_BRANCH_FINI SEM_BRANCH_FINI (vpc);
#undef OPRND #undef OPRND
#undef FLD #undef FLD
} }

67
sim/m32r/sim-if.c
View file

@ -17,13 +17,21 @@ with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h" #include "sim-main.h"
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#include "sim-options.h" #include "sim-options.h"
#include "libiberty.h" #include "libiberty.h"
#include "bfd.h" #include "bfd.h"
#ifdef HAVE_STRING_H
#include <string.h>
#else
#ifdef HAVE_STRINGS_H
#include <strings.h>
#endif
#endif
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
static void free_state (SIM_DESC); static void free_state (SIM_DESC);
static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose); static void print_m32r_misc_cpu (SIM_CPU *cpu, int verbose);
@ -51,8 +59,8 @@ sim_open (kind, callback, abfd, argv)
struct _bfd *abfd; struct _bfd *abfd;
char **argv; char **argv;
{ {
char c;
SIM_DESC sd = sim_state_alloc (kind, callback); SIM_DESC sd = sim_state_alloc (kind, callback);
char c;
/* The cpu data is kept in a separately allocated chunk of memory. */ /* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
@ -76,6 +84,14 @@ sim_open (kind, callback, abfd, argv)
return 0; return 0;
} }
#ifdef HAVE_DV_SOCKSER /* FIXME: was done differently before */
if (dv_sockser_install (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
#endif
#if 0 /* FIXME: 'twould be nice if we could do this */ #if 0 /* FIXME: 'twould be nice if we could do this */
/* These options override any module options. /* These options override any module options.
Obviously ambiguity should be avoided, however the caller may wish to Obviously ambiguity should be avoided, however the caller may wish to
@ -110,7 +126,7 @@ sim_open (kind, callback, abfd, argv)
/* Allocate core managed memory if none specified by user. /* Allocate core managed memory if none specified by user.
Use address 4 here in case the user wanted address 0 unmapped. */ Use address 4 here in case the user wanted address 0 unmapped. */
if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
sim_do_commandf (sd, "memory region 0,0x%lx", M32R_DEFAULT_MEM_SIZE); sim_do_commandf (sd, "memory region 0,0x%x", M32R_DEFAULT_MEM_SIZE);
/* check for/establish the reference program image */ /* check for/establish the reference program image */
if (sim_analyze_program (sd, if (sim_analyze_program (sd,
@ -123,47 +139,6 @@ sim_open (kind, callback, abfd, argv)
return 0; return 0;
} }
/* If both cpu model and state architecture are set, ensure they're
compatible. If only one is set, set the other. If neither are set,
use the default model. STATE_ARCHITECTURE is the bfd_arch_info data
for the selected "mach" (bfd terminology). */
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
if (! STATE_ARCHITECTURE (sd)
/* Only check cpu 0. STATE_ARCHITECTURE is for that one only. */
&& ! CPU_MACH (cpu))
{
/* Set the default model. */
const MODEL *model = sim_model_lookup (WITH_DEFAULT_MODEL);
sim_model_set (sd, NULL, model);
}
if (STATE_ARCHITECTURE (sd)
&& CPU_MACH (cpu))
{
if (strcmp (STATE_ARCHITECTURE (sd)->printable_name,
MACH_NAME (CPU_MACH (cpu))) != 0)
{
sim_io_eprintf (sd, "invalid model `%s' for `%s'\n",
MODEL_NAME (CPU_MODEL (cpu)),
STATE_ARCHITECTURE (sd)->printable_name);
free_state (sd);
return 0;
}
}
else if (STATE_ARCHITECTURE (sd))
{
/* Use the default model for the selected machine.
The default model is the first one in the list. */
const MACH *mach = sim_mach_lookup (STATE_ARCHITECTURE (sd)->printable_name);
sim_model_set (sd, NULL, MACH_MODELS (mach));
}
else
{
STATE_ARCHITECTURE (sd) = bfd_scan_arch (MACH_NAME (CPU_MACH (cpu)));
}
}
/* Establish any remaining configuration options. */ /* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK) if (sim_config (sd) != SIM_RC_OK)
{ {