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ARM Acorn/RISCiX target and host patches from Richard Earnshaw

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This commit is contained in:
Ken Raeburn 1994-09-05 10:53:00 +00:00
parent b50e328324
commit 318b02b6b9
19 changed files with 722 additions and 51 deletions
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9
ChangeLog
View file

@ -1,3 +1,12 @@
Mon Sep 5 05:01:30 1994 Ken Raeburn (raeburn@kr-pc.cygnus.com)
* configure.in (arm-*-*): Don't configure ld for this target.
Thu Sep 1 09:35:00 1994 J.T. Conklin (jtc@phishhead.cygnus.com)
* configure.in (*-*-netware): don't configure libg++, libio,
librx, or newlib.
Wed Aug 31 13:52:08 1994 Ian Lance Taylor (ian@sanguine.cygnus.com)
* configure.in (alpha-dec-osf*): Use osf*, not osf1*. Don't

9
bfd/ChangeLog
View file

@ -1,3 +1,12 @@
Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
* aoutx.h (NAME(aout,machine_type)): Recognize the ARM processor.
* archures.c, config.bfd, configure.host, libaout.h, reloc.c,
targets.c: Add support for the ARM.
* cpu-arm.c, riscix.c, config/riscix.mh, config/riscix.mt: New files.
* aoutx.h (add_to_stringtabl): Check that str isn't a NULL pointer.
Fri Sep 2 14:10:30 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
* reloc.c (enum bfd_reloc_code_real): Rewrote definition to use

30
bfd/configure.in
View file

@ -32,8 +32,8 @@ fi
# per-target:
# Canonicalize the secondary target names.
if [ -n "$with_targets" ]; then
for targ in `echo $with_targets | sed 's/,/ /g'`
if [ -n "$enable_targets" ]; then
for targ in `echo $enable_targets | sed 's/,/ /g'`
do
result=`$configsub $targ 2>/dev/null`
if [ -n "$result" ]; then
@ -76,11 +76,11 @@ done
rm -f Makefile.tmp Makefile.2
mv Makefile Makefile.tmp
case ${with_64_bit_bfd} in
case ${enable_64_bit_bfd} in
yes) want64=true ;;
no | "") want64=false ;;
*)
echo "*** bad value \"${with_64_bit_bfd}\" for 64-bit-bfd flag; ignored" 1>&2
echo "*** bad value \"${enable_64_bit_bfd}\" for 64-bit-bfd flag; ignored" 1>&2
;;
esac
@ -144,12 +144,12 @@ do
b_out_vec_big_host) tb="$tb bout.o aout32.o stab-syms.o" ;;
b_out_vec_little_host) tb="$tb bout.o aout32.o stab-syms.o" ;;
bfd_elf32_big_generic_vec) tb="$tb elf32-gen.o elf32.o elf.o" ;;
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.o elf32.o elf.o" ;;
bfd_elf32_bigmips_vec) tb="$tb elf32-mips.o elf32.o elf.o ecoff.o ecofflink.o" ;;
bfd_elf32_hppa_vec) tb="$tb elf32-hppa.o elf32.o elf.o" ;;
bfd_elf32_i386_vec) tb="$tb elf32-i386.o elf32.o elf.o" ;;
bfd_elf32_i860_vec) tb="$tb elf32-i860.o elf32.o elf.o" ;;
bfd_elf32_little_generic_vec) tb="$tb elf32-gen.o elf32.o elf.o" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.o elf32.o elf.o" ;;
bfd_elf32_littlemips_vec) tb="$tb elf32-mips.o elf32.o elf.o ecoff.o ecofflink.o" ;;
bfd_elf32_m68k_vec) tb="$tb elf32-m68k.o elf32.o elf.o" ;;
bfd_elf32_m88k_vec) tb="$tb elf32-m88k.o elf32.o elf.o" ;;
bfd_elf32_powerpc_vec) tb="$tb elf32-ppc.o elf32.o elf.o" ;;
@ -163,20 +163,18 @@ do
cisco_core_vec) tb="$tb cisco-core.o" ;;
demo_64_vec) tb="$tb demo64.o aout64.o stab-syms.o"
target64=true ;;
ecoff_big_vec) tb="$tb coff-mips.o" ;;
ecoff_little_vec) tb="$tb coff-mips.o" ;;
ecoffalpha_little_vec) tb="$tb coff-alpha.o"
ecoff_big_vec) tb="$tb coff-mips.o ecoff.o ecofflink.o" ;;
ecoff_little_vec) tb="$tb coff-mips.o ecoff.o ecofflink.o" ;;
ecoffalpha_little_vec) tb="$tb coff-alpha.o ecoff.o ecofflink.o"
target64=true ;;
h8300coff_vec) tb="$tb coff-h8300.o reloc16.o" ;;
h8500coff_vec) tb="$tb coff-h8500.o reloc16.o" ;;
host_aout_vec) tb="$tb host-aout.o aout32.o stab-syms.o" ;;
hp300bsd_vec) tb="$tb hp300bsd.o aout32.o stab-syms.o" ;;
hp300hpux_vec) tb="$tb hp300hpux.o aout32.o stab-syms.o" ;;
som_vec) tb="$tb som.o" ;;
i386aout_vec) tb="$tb i386aout.o aout32.o stab-syms.o" ;;
i386bsd_vec) tb="$tb i386bsd.o aout32.o stab-syms.o" ;;
i386dynix_vec) tb="$tb i386dynix.o aout32.o stab-syms.o" ;;
netbsd386_vec) tb="$tb netbsd386.o aout32.o stab-syms.o" ;;
i386coff_vec) tb="$tb coff-i386.o" ;;
i386linux_vec) tb="$tb i386linux.o aout32.o stab-syms.o" ;;
i386lynx_aout_vec) tb="$tb i386lynx.o lynx-core.o aout32.o stab-syms.o" ;;
@ -191,25 +189,29 @@ do
m68klynx_aout_vec) tb="$tb m68klynx.o lynx-core.o aout32.o stab-syms.o" ;;
m68klynx_coff_vec) tb="$tb cf-m68klynx.o coff-m68k.o lynx-core.o stab-syms.o" ;;
m88kbcs_vec) tb="$tb coff-m88k.o" ;;
netbsd386_vec) tb="$tb netbsd386.o aout32.o stab-syms.o" ;;
netbsd532_vec) tb="$tb netbsd532.o aout-ns32k.o stab-syms.o" ;;
newsos3_vec) tb="$tb newsos3.o aout32.o stab-syms.o" ;;
nlm32_i386_vec) tb="$tb nlm32-i386.o nlm32.o nlm.o" ;;
nlm32_sparc_vec) tb="$tb nlm32-sparc.o nlm32.o nlm.o" ;;
nlm32_alpha_vec) tb="$tb nlm32-alpha.o nlm32.o nlm.o"
target64=true ;;
riscix_vec) tb="$tb aout32.o riscix.o stab-syms.o" ;;
nlm32_powerpc_vec) tb="$tb nlm32-ppc.o nlm32.o nlm.o" ;;
pc532machaout_vec) tb="$tb pc532-mach.o aout-ns32k.o stab-syms.o" ;;
rs6000coff_vec) tb="$tb coff-rs6000.o" ;;
shcoff_vec) tb="$tb coff-sh.o reloc16.o" ;;
som_vec) tb="$tb som.o" ;;
sparclynx_aout_vec) tb="$tb sparclynx.o lynx-core.o aout32.o stab-syms.o" ;;
sparclynx_coff_vec) tb="$tb cf-sparclynx.o lynx-core.o stab-syms.o" ;;
sparccoff_vec) tb="$tb coff-sparc.o" ;;
srec_vec) tb="$tb srec.o" ;;
sunos_big_vec) tb="$tb sunos.o aout32.o stab-syms.o" ;;
symbolsrec_vec) tb="$tb srec.o" ;;
tekhex_vec) tb="$tb tekhex.o" ;;
we32kcoff_vec) tb="$tb coff-we32k.o" ;;
z8kcoff_vec) tb="$tb coff-z8k.o reloc16.o" ;;
srec_vec) tb="$tb srec.o" ;;
symbolsrec_vec) tb="$tb srec.o" ;;
"") ;;
*) echo "*** unknown target vector $vec" 1>&2; exit 1 ;;
esac

3
configure.in
View file

@ -314,6 +314,9 @@ case "${target}" in
# newlib is not 64 bit ready
noconfigdirs="$noconfigdirs newlib"
;;
arm-*-*)
noconfigdirs="$noconfigdirs ld"
;;
h8300*-*-* | \
h8500-*-*)
noconfigdirs="$noconfigdirs libg++ libio librx"

5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
* config/ho-riscix.h, config/tc-arm.c, config/tc-arm.h: New files
* configure.in: Recognize the arm.
Fri Sep 2 16:05:50 1994 Ian Lance Taylor (ian@sanguine.cygnus.com)
* ecoff.c (add_file): Don't try to generate line numbers if the

90
gas/configure vendored
View file

@ -171,11 +171,14 @@ EOF
-prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*)
prefix="$ac_optarg" ;;
# The program_*_given variables are so we can distinguish between
# unspecified and empty-string-valued options.
-program-prefix | --program-prefix | --program-prefi | --program-pref \
| --program-pre | --program-pr | --program-p)
ac_prev=program_prefix ;;
-program-prefix=* | --program-prefix=* | --program-prefi=* \
| --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*)
program_prefix_given=yes
program_prefix="$ac_optarg" ;;
-program-suffix | --program-suffix | --program-suffi | --program-suff \
@ -183,6 +186,7 @@ EOF
ac_prev=program_suffix ;;
-program-suffix=* | --program-suffix=* | --program-suffi=* \
| --program-suff=* | --program-suf=* | --program-su=* | --program-s=*)
program_suffix_given=yes
program_suffix="$ac_optarg" ;;
-program-transform-name | --program-transform-name \
@ -200,7 +204,10 @@ EOF
| --program-transfo=* | --program-transf=* \
| --program-trans=* | --program-tran=* \
| --progr-tra=* | --program-tr=* | --program-t=*)
program_transform_name="$ac_optarg" ;;
# Double any backslashes or dollar signs in the argument
program_transform_name_given=yes
program_transform_name="${program_transform_name} -e `echo ${ac_optarg} | sed -e 's/\\\\/\\\\\\\\/g' -e 's/\\\$/$$/g'`"
;;
-q | -quiet | --quiet | --quie | --qui | --qu | --q \
| -silent | --silent | --silen | --sile | --sil)
@ -393,12 +400,13 @@ ac_compile='${CC-cc} $CFLAGS $CPPFLAGS $LDFLAGS conftest.${ac_ext} -o conftest $
bfd_gas=no
user_bfd_gas=
# Check whether --enable-bfd-assembler or --disable-bfd-assembler was given.
enableval="$enable_bfd_assembler"
if test -n "$enableval"; then
case "${enableval}" in
yes) need_bfd=yes bfd_gas=yes ;;
no) ;;
yes) need_bfd=yes user_bfd_gas=yes ;;
no) user_bfd_gas=no ;;
*) { echo "configure: bad value ${enableval} given for bfd-assembler option" 1>&2; exit 1; } ;;
esac
fi
@ -510,6 +518,22 @@ esac
echo "$ac_t""$build" 1>&4
if [ "${host_alias}" != "${target_alias}" ] ; then
if [ "${program_prefix_given}${program_suffix_given}${program_transform_name_given}" = "" ] ; then
program_prefix=${target_alias}- ;
fi
fi
# Merge program_prefix and program_suffix onto program_transform_name
# Use a double $ so that make ignores it
if [ "${program_suffix}" != "" ] ; then
program_transform_name="-e s,\$\$,${program_suffix}, ${program_transform_name}"
fi
if [ "${program_prefix}" != "" ] ; then
program_transform_name="-e s,^,${program_prefix}, ${program_transform_name}"
fi
emulation=generic
@ -557,6 +581,8 @@ case ${generic_target} in
alpha-*-netware*) obj_format=ecoff ;;
alpha-*-osf*) obj_format=ecoff ;;
arm-*-riscix*) obj_format=aout bfd_gas=yes ;;
hppa-*-*elf*) obj_format=elf emulation=hppa ;;
hppa-*-osf*) obj_format=som emulation=hppa ;;
hppa-*-hpux*) obj_format=som emulation=hppa ;;
@ -573,7 +599,7 @@ case ${generic_target} in
i386-*-linux*elf*) obj_format=elf emulation=linux ;;
i386-*-linux*coff*) obj_format=coff emulation=linux
gas_target=i386coff ;;
i386-*-linux*) obj_format=aout emulation=linux ;;
i386-*-linux*) obj_format=aout emulation=linux bfd_gas=preferred ;;
i386-*-lynxos*) obj_format=coff gas_target=i386coff
emulation=lynx ;;
i386-*-sysv4* | i386-*-solaris* | i386-*-elf)
@ -694,20 +720,16 @@ fi
target_frag=${srcdir}/config/${gas_target}.mt
case ${bfd_gas}-${obj_format} in
yes-coff) need_bfd=yes ;;
no-coff) need_bfd=yes
cat >> confdefs.h <<\EOF
#define MANY_SEGMENTS 1
EOF
;;
case ${cpu_type}-${obj_format} in
# not yet
# i386-aout) bfd_gas=preferred ;;
*-elf) bfd_gas=yes ;;
*-ecoff) bfd_gas=yes ;;
*-som) bfd_gas=yes ;;
*) ;;
esac
case ${with_bfd_assembler}-${bfd_gas} in
case ${user_bfd_gas}-${bfd_gas} in
yes-yes | no-no)
# We didn't override user's choice.
;;
@ -725,6 +747,15 @@ case ${with_bfd_assembler}-${bfd_gas} in
;;
esac
case ${bfd_gas}-${cpu_type}-${obj_format} in
yes-*-coff) need_bfd=yes ;;
no-*-coff) need_bfd=yes
cat >> confdefs.h <<\EOF
#define MANY_SEGMENTS 1
EOF
;;
esac
reject_dev_configs=yes
case ${reject_dev_configs}-${dev} in
@ -881,7 +912,7 @@ else
# On the NeXT, cc -E runs the code through the compiler's parser,
# not just through cpp.
cat > conftest.${ac_ext} <<EOF
#line 885 "configure"
#line 914 "configure"
#include "confdefs.h"
#include <stdio.h>
Syntax Error
@ -894,7 +925,7 @@ else
rm -rf conftest*
CPP="${CC-cc} -E -traditional-cpp"
cat > conftest.${ac_ext} <<EOF
#line 898 "configure"
#line 927 "configure"
#include "confdefs.h"
#include <stdio.h>
Syntax Error
@ -924,7 +955,7 @@ if eval "test \"`echo '${'ac_cv_header_$ac_safe'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 928 "configure"
#line 957 "configure"
#include "confdefs.h"
#include <${ac_hdr}>
EOF
@ -961,7 +992,7 @@ else
{ echo "configure: can not run test program while cross compiling" 1>&2; exit 1; }
else
cat > conftest.${ac_ext} <<EOF
#line 965 "configure"
#line 994 "configure"
#include "confdefs.h"
main(){exit(0);}
EOF
@ -984,7 +1015,7 @@ if eval "test \"`echo '${'ac_cv_header_alloca_h'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 988 "configure"
#line 1017 "configure"
#include "confdefs.h"
#include <alloca.h>
int main() { return 0; }
@ -1015,7 +1046,7 @@ if eval "test \"`echo '${'ac_cv_func_alloca'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1019 "configure"
#line 1048 "configure"
#include "confdefs.h"
#ifdef __GNUC__
@ -1073,7 +1104,7 @@ if eval "test \"`echo '${'ac_cv_os_cray'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1077 "configure"
#line 1106 "configure"
#include "confdefs.h"
#if defined(CRAY) && ! defined(CRAY2)
webecray
@ -1100,7 +1131,7 @@ if eval "test \"`echo '${'ac_cv_func__getb67'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1104 "configure"
#line 1133 "configure"
#include "confdefs.h"
#include <ctype.h> /* Arbitrary system header to define __stub macros. */
int main() { return 0; }
@ -1141,7 +1172,7 @@ if eval "test \"`echo '${'ac_cv_func_GETB67'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1145 "configure"
#line 1174 "configure"
#include "confdefs.h"
#include <ctype.h> /* Arbitrary system header to define __stub macros. */
int main() { return 0; }
@ -1182,7 +1213,7 @@ if eval "test \"`echo '${'ac_cv_func_getb67'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1186 "configure"
#line 1215 "configure"
#include "confdefs.h"
#include <ctype.h> /* Arbitrary system header to define __stub macros. */
int main() { return 0; }
@ -1236,7 +1267,7 @@ ac_cv_c_stack_direction=0
else
cat > conftest.${ac_ext} <<EOF
#line 1240 "configure"
#line 1269 "configure"
#include "confdefs.h"
find_stack_direction ()
{
@ -1277,7 +1308,7 @@ if eval "test \"`echo '${'ac_cv_c_inline'+set}'`\" = set"; then
else
if test "$GCC" = yes; then
cat > conftest.${ac_ext} <<EOF
#line 1281 "configure"
#line 1310 "configure"
#include "confdefs.h"
int main() { return 0; }
@ -1315,7 +1346,7 @@ if eval "test \"`echo '${'gas_cv_assert_ok'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1319 "configure"
#line 1348 "configure"
#include "confdefs.h"
#include <assert.h>
#include <stdio.h>
@ -1356,7 +1387,7 @@ if eval "test \"`echo '${'gas_cv_malloc_decl_needed'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1360 "configure"
#line 1389 "configure"
#include "confdefs.h"
#ifdef HAVE_MEMORY_H
@ -1401,7 +1432,7 @@ if eval "test \"`echo '${'gas_cv_free_decl_needed'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1405 "configure"
#line 1434 "configure"
#include "confdefs.h"
#ifdef HAVE_MEMORY_H
@ -1449,7 +1480,7 @@ if eval "test \"`echo '${'gas_cv_errno_decl_needed'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&4
else
cat > conftest.${ac_ext} <<EOF
#line 1453 "configure"
#line 1482 "configure"
#include "confdefs.h"
#ifdef HAVE_ERRNO_H
@ -1589,6 +1620,9 @@ s%@build_alias@%$build_alias%g
s%@build_cpu@%$build_cpu%g
s%@build_vendor@%$build_vendor%g
s%@build_os@%$build_os%g
s%@program_prefix@%$program_prefix%g
s%@program_suffix@%$program_suffix%g
s%@program_transform_name@%$program_transform_name%g
s%@OPCODES_LIB@%$OPCODES_LIB%g
/@target_frag@/r $target_frag
s%@target_frag@%%g

25
gas/configure.in
View file

@ -9,11 +9,12 @@ dnl
AC_INIT(as.h)
dnl
bfd_gas=no
user_bfd_gas=
AC_ARG_ENABLE(bfd-assembler,
[ bfd-assembler use BFD back end for writing object files],
[case "${enableval}" in
yes) need_bfd=yes bfd_gas=yes ;;
no) ;;
yes) need_bfd=yes user_bfd_gas=yes ;;
no) user_bfd_gas=no ;;
*) AC_MSG_ERROR(bad value ${enableval} given for bfd-assembler option) ;;
esac])dnl
@ -23,6 +24,7 @@ AC_CONFIG_HEADER(conf)
dnl For recursion to work right, this must be an absolute pathname.
AC_CONFIG_AUX_DIR(`cd $srcdir;pwd`/..)
AC_CANONICAL_SYSTEM
AC_PROGRAM_TRANSFORM_NAME
emulation=generic
@ -69,6 +71,8 @@ case ${generic_target} in
alpha-*-netware*) obj_format=ecoff ;;
alpha-*-osf*) obj_format=ecoff ;;
arm-*-riscix*) obj_format=aout bfd_gas=yes ;;
hppa-*-*elf*) obj_format=elf emulation=hppa ;;
hppa-*-osf*) obj_format=som emulation=hppa ;;
hppa-*-hpux*) obj_format=som emulation=hppa ;;
@ -85,7 +89,7 @@ case ${generic_target} in
i386-*-linux*elf*) obj_format=elf emulation=linux ;;
i386-*-linux*coff*) obj_format=coff emulation=linux
gas_target=i386coff ;;
i386-*-linux*) obj_format=aout emulation=linux ;;
i386-*-linux*) obj_format=aout emulation=linux bfd_gas=preferred ;;
i386-*-lynxos*) obj_format=coff gas_target=i386coff
emulation=lynx ;;
i386-*-sysv4* | i386-*-solaris* | i386-*-elf)
@ -209,17 +213,16 @@ fi
target_frag=${srcdir}/config/${gas_target}.mt
AC_SUBST_FILE(target_frag)
case ${bfd_gas}-${obj_format} in
yes-coff) need_bfd=yes ;;
no-coff) need_bfd=yes
AC_DEFINE(MANY_SEGMENTS) ;;
case ${cpu_type}-${obj_format} in
# not yet
# i386-aout) bfd_gas=preferred ;;
*-elf) bfd_gas=yes ;;
*-ecoff) bfd_gas=yes ;;
*-som) bfd_gas=yes ;;
*) ;;
esac
case ${with_bfd_assembler}-${bfd_gas} in
case ${user_bfd_gas}-${bfd_gas} in
yes-yes | no-no)
# We didn't override user's choice.
;;
@ -237,6 +240,12 @@ case ${with_bfd_assembler}-${bfd_gas} in
;;
esac
case ${bfd_gas}-${cpu_type}-${obj_format} in
yes-*-coff) need_bfd=yes ;;
no-*-coff) need_bfd=yes
AC_DEFINE(MANY_SEGMENTS) ;;
esac
reject_dev_configs=yes
case ${reject_dev_configs}-${dev} in

12
gas/testsuite/ChangeLog
View file

@ -1,3 +1,12 @@
Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
* gas/arm/*: New subtree. Add ARM tests.
Mon Aug 8 12:13:31 1994 Jeff Law (law@snake.cs.utah.edu)
* gas/hppa/unsorted/unsorted.exp: Accept any character
between foo's type and foo itself.
Fri Jul 15 19:09:25 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
* lib/gas-defs.exp (run_dump_test): New routine for running the
@ -10,6 +19,9 @@ Fri Jul 15 19:09:25 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
(regexp_diff): Always return a value. Fix bugs in actually doing
the regexp test.
* gas/sun4/addend.exp: Use run_dump_test.
* gas/sun4/addend.d: Fix regular expressions so that they work.
Thu Jul 7 11:55:33 1994 Jeff Law (law@snake.cs.utah.edu)
* gas/hppa/reloc/relocreduce2.s: More relocation reduction tests.

13
gas/testsuite/gas/arm/arm6.s Normal file
View file

@ -0,0 +1,13 @@
.text
.align 0
mrs r8, CPSR
mrseq r9, CPSR_all
mrs r1, CPSR_flg
mrs r2, SPSR
msr CPSR, r1
msrne CPSR_flg, #0xf0000000
msr SPSR_flg, r8
msr SPSR_all, r9

24
gas/testsuite/gas/arm/copro.s Normal file
View file

@ -0,0 +1,24 @@
.text
.align 0
cdp p1, 4, cr1, cr2, cr3
cdpeq 4, 3, c1, c4, cr5, 5
ldc 5, cr9, [r3]
ldcl 1, cr14, [r1, #32]
ldcmi 0, cr0, [r2, #1020]!
ldcpll p7, c1, [r3], #64
ldc p0, c8, foo
foo:
stc 5, cr0, [r3]
stcl 3, cr15, [r0, #8]
stceq p4, cr12, [r2, #100]!
stccc p6, c8, [r4], #48
stc p1, c7, bar
bar:
mrc 2, 3, r5, c1, c2
mrcge p4, 5, r15, cr1, cr2, 7
mcr p7, 1, r15, cr1, cr1
mcrlt 5, 1, r8, cr2, cr9, 0

150
gas/testsuite/gas/arm/float.s Normal file
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@ -0,0 +1,150 @@
.text
.align 0
mvfe f0, f1
mvfeqe f3, f5
mvfeqd f4, #1.0
mvfs f4, f7
mvfsp f0, f1
mvfdm f3, f4
mvfez f7, f7
adfe f0, f1, #2.0
adfeqe f1, f2, #0.5
adfsm f3, f4, f5
sufd f0, f0, #2.0
sufs f1, f2, #10.0
sufneez f3, f4, f5
rsfs f1, f1, #0.0
rsfdp f3, f0, #5.0
rsfled f7, f6, f0
mufd f0, f0, f0
mufez f1, f2, #3.0
mufals f0, f0, #4.0
dvfd f0, f0, #1.0000
dvfez f0, f1, #10e0
dvfmism f3, f4, f5
rdfe f0, f1, #1.0e1
rdfs f3, f7, #0f1
rdfccdp f4, f4, f3
powd f0, f2, f3
pows f1, f3, #0e1e1
powcsez f4, f7, #1
rpws f7, f6, f7
rpweqd f0, f1, f2
rpwem f2, f2, f3
rmfd f1, f2, #3
rmfvss f3, f4, f4
rmfep f4, f7, f0
fmls f0, f1, f2
fmleqs f1, f3, f5
fmlplsz f4, f6, f0
fdvs f1, f3, #10
fdvsp f0, f1, f2
fdvhssm f4, f4, f4
frds f1, f1, #1.0
frdgts f2, f1, f0
frdgtsz f4, f4, f5
pold f0, f1, f2
polsz f4, f6, #3.0
poleqe f5, f6, f7
mnfs f0, f1
mnfd f0, #3.0
mnfez f0, #4.0
mnfeqez f0, f5
mnfsp f0, f4
mnfdm f1, f7
absd f0, f1
abssp f1, #3.0
abseqe f4, f5
rnds f1, f2
rndd f3, f4
rndeqez f6, #4.0
sqts f5, f5
sqtdp f6, f6
sqtplez f7, f6
logs f0, #10
loge f0, #0f10
lognedz f0, f1
lgne f1, f2
lgndz f1, f3
lgnvcs f3, f4
exps f1, f3
expem f3, #10.0
exppld f6, f7
sind f0, f1
sinsm f1, f2
singte f4, #5
cosd f1, f3
cosem f4, f5
cosnedp f6, f1
tane f1, f5
tansz f4, f7
tangedz f1, #4.0
asne f4, f5
asnsp f6, #5e-1
asnmidz f5, f5
acss f5, f6
acsd f6, f0
acshsem f1, #0.05e1
atne f0, f5
atnsz f1, #5
atnltd f3, f2
urde f5, f4
nrme f6, f5
nrmpldz f7, f5
fltsp f0, r8
flte f1, r0
flteqdz f5, r7
fix r0, f1
fixz r1, f7
fixcsm r5, f5
wfc r0
wfs r1
rfseq r2
rfc r4
cmf f0, #1
cmf f1, f2
cmfeq f0, f1
cnf f0, #3
cnf f1, #0.5
cnfvs f3, f4
cmfe f0, f1
cmfeeq f1, f2
cmfeqe f3, #5.0
cnfe f1, f3
cnfeeq f3, f4
cnfeqe f4, f7
cnfale f4, #5.0

14
gas/testsuite/gas/arm/gas.exp Normal file
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@ -0,0 +1,14 @@
#
# Some ARM tests
#
if [istarget arm-*-riscix*] then {
gas_test "inst.s" "" $stdoptlist "Basic instruction set"
gas_test "arm3.s" "" $stdoptlist "Arm 3 instructions"
gas_test "arm6.s" "" $stdoptlist "Arm 6 instructions"
gas_test "copro.s" "" $stdoptlist "Co processor instructions"
gas_test "float.s" "" $stdoptlist "Core floating point instructions"
}

189
gas/testsuite/gas/arm/inst.s Normal file
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@ -0,0 +1,189 @@
@ Test file for ARM/GAS -- basic instructions
.text
.align
mov r0, #0
mov r1, r2
mov r3, r4, lsl #3
mov r5, r6, lsr r7
mov r8, r9, asr r10
mov r11, r12, asl r13
mov r14, r15, rrx
moval r1, r2
moveq r2, r3
movne r4, r5
movlt r6, r7
movge r8, r9
movle r10, r11
movgt r12, r13
movcc r1, r2
movcs r1, r3
movmi r3, r6
movpl r7, r9
movvs r1, r8
movvc r9, r1, lsr #31
movhi r8, r15
movls r15, r14
movhs r9, r8
movul r1, r3
movs r0, r8
movuls r0, r7
add r0, r1, #10
add r2, r3, r4
add r5, r6, r7, asl #5
add r1, r2, r3, lsl r1
and r0, r1, #10
and r2, r3, r4
and r5, r6, r7, asl #5
and r1, r2, r3, lsl r1
eor r0, r1, #10
eor r2, r3, r4
eor r5, r6, r7, asl #5
eor r1, r2, r3, lsl r1
sub r0, r1, #10
sub r2, r3, r4
sub r5, r6, r7, asl #5
sub r1, r2, r3, lsl r1
adc r0, r1, #10
adc r2, r3, r4
adc r5, r6, r7, asl #5
adc r1, r2, r3, lsl r1
sbc r0, r1, #10
sbc r2, r3, r4
sbc r5, r6, r7, asl #5
sbc r1, r2, r3, lsl r1
rsb r0, r1, #10
rsb r2, r3, r4
rsb r5, r6, r7, asl #5
rsb r1, r2, r3, lsl r1
rsc r0, r1, #10
rsc r2, r3, r4
rsc r5, r6, r7, asl #5
rsc r1, r2, r3, lsl r1
orr r0, r1, #10
orr r2, r3, r4
orr r5, r6, r7, asl #5
orr r1, r2, r3, lsl r1
bic r0, r1, #10
bic r2, r3, r4
bic r5, r6, r7, asl #5
bic r1, r2, r3, lsl r1
mvn r0, #10
mvn r2, r4
mvn r5, r7, asl #5
mvn r1, r3, lsl r1
tst r0, #10
tst r2, r4
tst r5, r7, asl #5
tst r1, r3, lsl r1
teq r0, #10
teq r2, r4
teq r5, r7, asl #5
teq r1, r3, lsl r1
cmp r0, #10
cmp r2, r4
cmp r5, r7, asl #5
cmp r1, r3, lsl r1
cmn r0, #10
cmn r2, r4
cmn r5, r7, asl #5
cmn r1, r3, lsl r1
teqp r0, #10
teqp r2, r4
teqp r5, r7, asl #5
teqp r1, r3, lsl r1
cmnp r0, #10
cmnp r2, r4
cmnp r5, r7, asl #5
cmnp r1, r3, lsl r1
cmpp r0, #10
cmpp r2, r4
cmpp r5, r7, asl #5
cmpp r1, r3, lsl r1
tstp r0, #10
tstp r2, r4
tstp r5, r7, asl #5
tstp r1, r3, lsl r1
mul r0, r1, r2
muls r1, r2, r3
mulne r0, r1, r0
mullss r9, r8, r7
mla r1, r9, r10, r11
mlas r3, r4, r9, r12
mlalt r9, r8, r7, r13
mlages r4, r1, r3, r14
ldr r0, [r1]
ldr r1, [r1, r2]
ldr r2, [r3, r4]!
ldr r2, [r2, #32]
ldr r2, [r3, r4, lsr #8]
ldreq r4, [r5, r4, asl #9]!
ldrne r4, [r5], #6
ldrt r1, [r2], r3
ldr r2, [r4], r5, lsr #8
foo:
ldr r0, foo
ldrb r3, [r4]
ldrnebt r5, [r8]
str r0, [r1]
str r1, [r1, r2]
str r3, [r3, r4]!
str r2, [r2, #32]
str r2, [r3, r4, lsr #8]
streq r4, [r5, r4, asl #9]!
strne r4, [r5], #6
str r1, [r2], r3
strt r2, [r4], r5, lsr #8
str r1, bar
bar:
stralb r1, [r7]
strbt r2, [r0]
ldmia r0, {r1}
ldmeqib r2, {r3, r4, r5}
ldmalda r3, {r0-r15}^
ldmdb r11!, {r0-r8, r10}
ldmed r1, {r0, r1, r2}|0xf0
ldmfd r2, {r3, r4}+{r5, r6, r7, r8}
ldmea r3, 3
ldmfa r4!, {r8, r9}^
stmia r0, {r1}
stmeqib r2, {r3, r4, r5}
stmalda r3, {r0-r15}^
stmdb r10!, {r0-r8, r10}
stmed r1, {r0, r1, r2}
stmfd r2, {r3, r4}
stmea r3, 3
stmfa r4!, {r8, r9}^
swi 0x123456
swihs 0x33
bl _wombat
blpl bar
b _wibble
ble testerfunc

6
ld/ChangeLog
View file

@ -1,3 +1,9 @@
Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
* Makefile.in, configure.in: Add support (disabled) the ARM/RISCiX.
* config/riscix.mt, emulparams/riscix.sh, scripttempl/riscix.sc:
New files.
Tue Aug 30 11:48:08 1994 Eric Youngdale (ericy@cais.cais.com)
* ld.h (args_type): Add field soname.

1
ld/config/riscix.mt Normal file
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@ -0,0 +1 @@
EMUL=riscix

5
ld/emulparams/riscix.sh Normal file
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@ -0,0 +1,5 @@
SCRIPT_NAME=riscix
OUTPUT_FORMAT="a.out-riscix"
TEXT_START_ADDR=0x8000
PAGE_SIZE=0x8000
ARCH=arm

35
ld/scripttempl/riscix.sc Normal file
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@ -0,0 +1,35 @@
cat <<EOF
OUTPUT_FORMAT("${OUTPUT_FORMAT}")
OUTPUT_ARCH(${ARCH})
${RELOCATING+${LIB_SEARCH_DIRS}}
${RELOCATING+__DYNAMIC = 0;}
${STACKZERO+${RELOCATING+${STACKZERO}}}
${SHLIB_PATH+${RELOCATING+${SHLIB_PATH}}}
SECTIONS
{
.text ${RELOCATING+${TEXT_START_ADDR}}:
{
CREATE_OBJECT_SYMBOLS
*(.text)
${PAD_TEXT+${RELOCATING+. = ${DATA_ALIGNMENT};}}
${RELOCATING+_etext = ${DATA_ALIGNMENT};}
${RELOCATING+__etext = ${DATA_ALIGNMENT};}
}
.data ${RELOCATING+${DATA_ALIGNMENT}} :
{
*(.data)
${CONSTRUCTING+CONSTRUCTORS}
${RELOCATING+_edata = .;}
${RELOCATING+__edata = .;}
}
.bss ${RELOCATING+SIZEOF(.data) + ADDR(.data)} :
{
${RELOCATING+ __bss_start = .};
*(.bss)
*(COMMON)
${RELOCATING+_end = ALIGN(4) };
${RELOCATING+__end = ALIGN(4) };
}
}
EOF

13
opcodes/ChangeLog
View file

@ -1,3 +1,14 @@
Sun Sep 04 17:58:10 1994 Richard Earnshaw (rwe@pegasus.esprit.ec.org)
* configure.in, Makefile.in, disassemble.c: Add support for the ARM.
* arm-dis.c, arm-opc.h: New files.
Fri Aug 5 14:00:05 1994 Stan Shebs (shebs@andros.cygnus.com)
* Makefile.in (ns32k-dis.o): Add dependency.
* ns32k-dis.c (print_insn_arg): Declare initialized local as
string, not as array of chars.
Thu Jul 28 18:14:16 1994 Ken Raeburn (raeburn@cujo.cygnus.com)
* sparc-dis.c (print_insn_sparc): Handle new operand type 'x'.
@ -53,7 +64,7 @@ Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au)
from distribution. A ns32k-dis.c from a previous distribution has
been brought up to date and supports the new interface.
* disaaemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
* disassemble.c: define ARCH_ns32k and add case bfd_arch_ns32k.
* configure.in: add bfd_ns32k_arch target support.

140
opcodes/arm-opc.h Normal file
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/* Opcode table for the ARM.
Copyright 1994 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
struct arm_opcode {
unsigned long value, mask; /* recognise instruction if (op&mask)==value */
char *assembler; /* how to disassemble this instruction */
};
/* format of the assembler string :
%% %
%<bitfield>d print the bitfield in decimal
%<bitfield>x print the bitfield in hex
%<bitfield>r print as an ARM register
%<bitfield>f print a floating point constant if >7 else an fp register
%c print condition code (always bits 28-31)
%P print floating point precision in arithmetic insn
%Q print floating point precision in ldf/stf insn
%R print floating point rounding mode
%<bitnum>'c print specified char iff bit is one
%<bitnum>`c print specified char iff bit is zero
%<bitnum>?ab print a if bit is one else print b
%p print 'p' iff bits 12-15 are 15
%t print 't' iff bit 21 set and bit 24 clear
%o print operand2 (immediate or register + shift)
%a print address for ldr/str instruction
%b print branch destination
%A print address for ldc/stc/ldf/stf instruction
%m print register mask for ldm/stm instruction
%C print the PSR sub type.
%F print the COUNT field of a LFM/SFM instruction.
*/
static struct arm_opcode arm_opcodes[] = {
/* ARM instructions */
{0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
{0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
{0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
{0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
{0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
{0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
{0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
{0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
{0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
{0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
{0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
{0x0120f000, 0x0db6f000, "msr%c\t%22?scpsr%C, %o"},
{0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?scpsr"},
{0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
{0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
{0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
{0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
{0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
{0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
{0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
{0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
{0x04000000, 0x0c100000, "str%c%22'b%t\t%12-15r, %a"},
{0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
{0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"},
{0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%22`!, %m%22'^"},
{0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
{0x0f000000, 0x0f000000, "swi%c\t%0-23x"},
/* Floating point coprocessor instructions */
{0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
{0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
{0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
{0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
{0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
{0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
{0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
{0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
{0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
{0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
{0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
{0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
{0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
{0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
{0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
{0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
{0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
{0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
{0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
{0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
{0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
{0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
{0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
{0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
{0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
{0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
{0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
{0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
{0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
{0x0d000200, 0x0f900fff, "sfm%cfd\t%12-14f, %F, [%16-19r]%21'!"},
{0x0c900200, 0x0f900fff, "lfm%cfd\t%12-14f, %F, [%16-19r]%21'!"},
{0x0c800200, 0x0f900fff, "sfm%cea\t%12-14f, %F, [%16-19r]%21'!"},
{0x0d100200, 0x0f900fff, "lfm%cea\t%12-14f, %F, [%16-19r]%21'!"},
{0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
{0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
/* Generic coprocessor instructions */
{0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
{0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
{0x0c000000, 0x0e100000, "stc%c%22`l\t%8-11d, cr%12-15d, %A"},
{0x0c100000, 0x0e100000, "ldc%c%22`l\t%8-11d, cr%12-15d, %A"},
/* the rest */
{0x00000000, 0x00000000, "undefined instruction %0-31x"},
{0x00000000, 0x00000000, 0}
};
#define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000)