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[AArch64][PATCH 11/14] Add support for the 2H vector type.

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ARMv8.2 adds 16-bit floating point operations as an optional extension
to the floating point and Adv.SIMD support. The FP16 additions to the
scalar pairwise group introduce a new vector type, 2H. This patch adds
support for this vector type to binutils.

The patch adds a new operand qualifier to the enum
aarch64.h:aarch64_opnd_qualifier. This interferes with the calculation
used by aarch64-dis.c:get_vreg_qualifier_from_value, called when
decoding an instruction. Since the new vector type is only used in FP16
scalar pairwise instructions which do not require the function, this
patch adjusts the function to ignore the new qualifier.

gas/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
	take into account new vector type 2H.
	(vectype_to_qualifier): Likewise.

include/opcode/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64.h (enum aarch64_opnd_qualifier): Add
	AARCH64_OPND_QLF_V_2H.

opcodes/
2015-12-14  Matthew Wahab  <matthew.wahab@arm.coM>

	* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
	and adjust calculation to ignore qualifier for type 2H.
	* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".

Change-Id: Idf9a3694732962c80fde04f08c7304de9164f126
This commit is contained in:
Matthew Wahab 2015-12-14 17:27:52 +00:00
parent 65f2205d60
commit 3067d3b96c
7 changed files with 33 additions and 8 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
gas/ChangeLog
View file

@ -1,3 +1,9 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
take into account new vector type 2H.
(vectype_to_qualifier): Likewise.
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand

13
gas/config/tc-aarch64.c
View file

@ -744,7 +744,7 @@ aarch64_reg_parse_32_64 (char **ccp, int reject_sp, int reject_rz,
otherwise return FALSE.
Accept only one occurrence of:
8b 16b 4h 8h 2s 4s 1d 2d
8b 16b 2h 4h 8h 2s 4s 1d 2d
b h s d q */
static bfd_boolean
parse_neon_type_for_operand (struct neon_type_el *parsed_type, char **str)
@ -803,7 +803,8 @@ elt_size:
first_error (_("missing element size"));
return FALSE;
}
if (width != 0 && width * element_size != 64 && width * element_size != 128)
if (width != 0 && width * element_size != 64 && width * element_size != 128
&& !(width == 2 && element_size == 16))
{
first_error_fmt (_
("invalid element size %d and vector size combination %c"),
@ -4674,7 +4675,7 @@ vectype_to_qualifier (const struct neon_type_el *vectype)
const unsigned int ele_base [5] =
{
AARCH64_OPND_QLF_V_8B,
AARCH64_OPND_QLF_V_4H,
AARCH64_OPND_QLF_V_2H,
AARCH64_OPND_QLF_V_2S,
AARCH64_OPND_QLF_V_1D,
AARCH64_OPND_QLF_V_1Q
@ -4694,7 +4695,7 @@ vectype_to_qualifier (const struct neon_type_el *vectype)
int reg_size = ele_size[vectype->type] * vectype->width;
unsigned offset;
unsigned shift;
if (reg_size != 16 && reg_size != 8)
if (reg_size != 16 && reg_size != 8 && reg_size != 4)
goto vectype_conversion_fail;
/* The conversion is by calculating the offset from the base operand
@ -4704,9 +4705,7 @@ vectype_to_qualifier (const struct neon_type_el *vectype)
shift = 0;
if (vectype->type == NT_b)
shift = 4;
else if (vectype->type == NT_h)
shift = 3;
else if (vectype->type == NT_s)
else if (vectype->type == NT_h || vectype->type == NT_s)
shift = 2;
else if (vectype->type >= NT_d)
shift = 1;

5
include/opcode/ChangeLog
View file

@ -1,3 +1,8 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (enum aarch64_opnd_qualifier): Add
AARCH64_OPND_QLF_V_2H.
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.

1
include/opcode/aarch64.h
View file

@ -282,6 +282,7 @@ enum aarch64_opnd_qualifier
constraint qualifiers for immediate operands wherever possible. */
AARCH64_OPND_QLF_V_8B,
AARCH64_OPND_QLF_V_16B,
AARCH64_OPND_QLF_V_2H,
AARCH64_OPND_QLF_V_4H,
AARCH64_OPND_QLF_V_8H,
AARCH64_OPND_QLF_V_2S,

6
opcodes/ChangeLog
View file

@ -1,3 +1,9 @@
2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
* aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
and adjust calculation to ignore qualifier for type 2H.
* aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.

9
opcodes/aarch64-dis.c
View file

@ -173,12 +173,19 @@ get_greg_qualifier_from_value (aarch64_insn value)
return qualifier;
}
/* Given VALUE, return qualifier for a vector register. */
/* Given VALUE, return qualifier for a vector register. This does not support
decoding instructions that accept the 2H vector type. */
static inline enum aarch64_opnd_qualifier
get_vreg_qualifier_from_value (aarch64_insn value)
{
enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
/* Instructions using vector type 2H should not call this function. Skip over
the 2H qualifier. */
if (qualifier >= AARCH64_OPND_QLF_V_2H)
qualifier += 1;
assert (value <= 0x8
&& aarch64_get_qualifier_standard_value (qualifier) == value);
return qualifier;

1
opcodes/aarch64-opc.c
View file

@ -578,6 +578,7 @@ struct operand_qualifier_data aarch64_opnd_qualifiers[] =
{1, 8, 0x0, "8b", OQK_OPD_VARIANT},
{1, 16, 0x1, "16b", OQK_OPD_VARIANT},
{2, 2, 0x0, "2h", OQK_OPD_VARIANT},
{2, 4, 0x2, "4h", OQK_OPD_VARIANT},
{2, 8, 0x3, "8h", OQK_OPD_VARIANT},
{4, 2, 0x4, "2s", OQK_OPD_VARIANT},