* mips.h: Add macros for cop0, cop1 cop2 and cop3.
Change mips_opcodes from const array to a pointer, and change bfd_mips_num_opcodes from const int to int, so that we can increase the size of the mips opcodes table dynamically.
This commit is contained in:
Dawn Perchik
parent
efec4a282c
commit
2fedd0a135
2 changed files with 218 additions and 4 deletions
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@ -1,3 +1,11 @@
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Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com>
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* mips.h: Add macros for cop0, cop1 cop2 and cop3.
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Change mips_opcodes from const array to a pointer,
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and change bfd_mips_num_opcodes from const int to int,
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so that we can increase the size of the mips opcodes table
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dynamically.
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start-sanitize-d30v
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Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com>
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@ -1,5 +1,5 @@
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/* mips.h. Mips opcode list for GDB, the GNU debugger.
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Copyright 1993, 1995 Free Software Foundation, Inc.
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Copyright 1993, 94, 95, 1996 Free Software Foundation, Inc.
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Contributed by Ralph Campbell and OSF
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Commented and modified by Ian Lance Taylor, Cygnus Support
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@ -19,6 +19,9 @@ You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef _MIPS_H_
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#define _MIPS_H_
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/* These are bit masks and shift counts to use to access the various
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fields of an instruction. To retrieve the X field of an
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instruction, use the expression
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@ -94,6 +97,30 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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#define OP_SH_FUNCT 0
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#define OP_MASK_SPEC 0x3f
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#define OP_SH_SPEC 0
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#define OP_SH_LOCC 8 /* FP condition code */
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#define OP_SH_HICC 18 /* FP condition code */
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#define OP_MASK_CC 0x7
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#define OP_SH_COP1NORM 25 /* Normal COP1 encoding */
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#define OP_MASK_COP1NORM 0x1 /* a single bit */
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#define OP_SH_COP1SPEC 21 /* COP1 encodings */
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#define OP_MASK_COP1SPEC 0xf
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#define OP_MASK_COP1SCLR 0x4
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#define OP_MASK_COP1CMP 0x3
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#define OP_SH_COP1CMP 4
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#define OP_SH_FORMAT 21 /* FP short format field */
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#define OP_MASK_FORMAT 0x7
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#define OP_SH_TRUE 16
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#define OP_MASK_TRUE 0x1
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#define OP_SH_GE 17
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#define OP_MASK_GE 0x01
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#define OP_SH_UNSIGNED 16
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#define OP_MASK_UNSIGNED 0x1
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#define OP_SH_HINT 16
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#define OP_MASK_HINT 0x1f
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#define OP_SH_MMI 0 /* Multimedia (parallel) op */
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#define OP_MASK_MMI 0x3f
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#define OP_SH_MMISUB 6
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#define OP_MASK_MMISUB 0x1f
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/* This structure holds information for a particular instruction. */
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@ -246,6 +273,12 @@ struct mips_opcode
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#define INSN_ISA4 0x40000000
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/* LSI R4010 instruction. */
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#define INSN_4010 0x50000000
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/* NEC VR4100 instruction. */
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#define INSN_4100 0x60000000
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/* start-sanitize-r5900 */
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/* Toshiba R5900 instruction */
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#define INSN_5900 0x70000000
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/* end-sanitize-r5900 */
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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@ -264,6 +297,7 @@ enum {
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M_ADD_I,
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M_ADDU_I,
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M_AND_I,
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M_BEQ,
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M_BEQ_I,
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M_BEQL_I,
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M_BGE,
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@ -298,6 +332,7 @@ enum {
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M_BLTUL,
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M_BLTU_I,
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M_BLTUL_I,
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M_BNE,
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M_BNE_I,
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M_BNEL_I,
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M_DABS,
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@ -325,6 +360,7 @@ enum {
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M_DREMU_3I,
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M_DSUB_I,
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M_DSUBU_I,
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M_DSUBU_I_2,
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M_J_A,
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M_JAL_1,
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M_JAL_2,
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@ -439,6 +475,7 @@ enum {
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M_SWR_AB,
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M_SUB_I,
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M_SUBU_I,
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M_SUBU_I_2,
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M_TEQ_I,
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M_TGE_I,
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M_TGEU_I,
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@ -461,9 +498,15 @@ enum {
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M_USW_A,
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M_USD,
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M_USD_A,
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M_XOR_I
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M_XOR_I,
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M_COP0,
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M_COP1,
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M_COP2,
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M_COP3,
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M_NUM_MACROS
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};
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/* The order of overloaded instructions matters. Label arguments and
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register arguments look the same. Instructions that can have either
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for arguments must apear in the correct order in this table for the
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@ -474,6 +517,169 @@ enum {
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Many instructions are short hand for other instructions (i.e., The
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jal <register> instruction is short for jalr <register>). */
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extern const struct mips_opcode mips_opcodes[];
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extern const int bfd_mips_num_opcodes;
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extern const struct mips_opcode mips_builtin_opcodes[];
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extern const int bfd_mips_num_builtin_opcodes;
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extern struct mips_opcode *mips_opcodes;
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extern int bfd_mips_num_opcodes;
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#define NUMOPCODES bfd_mips_num_opcodes
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/* The rest of this file adds definitions for the mips16 TinyRISC
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processor. */
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/* These are the bitmasks and shift counts used for the different
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fields in the instruction formats. Other than OP, no masks are
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provided for the fixed portions of an instruction, since they are
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not needed.
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The I format uses IMM11.
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The RI format uses RX and IMM8.
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The RR format uses RX, and RY.
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The RRI format uses RX, RY, and IMM5.
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The RRR format uses RX, RY, and RZ.
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The RRI_A format uses RX, RY, and IMM4.
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The SHIFT format uses RX, RY, and SHAMT.
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The I8 format uses IMM8.
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The I8_MOVR32 format uses RY and REGR32.
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The IR_MOV32R format uses REG32R and MOV32Z.
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The I64 format uses IMM8.
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The RI64 format uses RY and IMM5.
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*/
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#define MIPS16OP_MASK_OP 0x1f
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#define MIPS16OP_SH_OP 11
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#define MIPS16OP_MASK_IMM11 0x7ff
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#define MIPS16OP_SH_IMM11 0
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#define MIPS16OP_MASK_RX 0x7
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#define MIPS16OP_SH_RX 8
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#define MIPS16OP_MASK_IMM8 0xff
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#define MIPS16OP_SH_IMM8 0
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#define MIPS16OP_MASK_RY 0x7
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#define MIPS16OP_SH_RY 5
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#define MIPS16OP_MASK_IMM5 0x1f
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#define MIPS16OP_SH_IMM5 0
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#define MIPS16OP_MASK_RZ 0x7
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#define MIPS16OP_SH_RZ 2
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#define MIPS16OP_MASK_IMM4 0xf
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#define MIPS16OP_SH_IMM4 0
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#define MIPS16OP_MASK_REGR32 0x1f
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#define MIPS16OP_SH_REGR32 0
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#define MIPS16OP_MASK_REG32R 0x1f
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#define MIPS16OP_SH_REG32R 3
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#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
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#define MIPS16OP_MASK_MOVE32Z 0x7
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#define MIPS16OP_SH_MOVE32Z 0
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#define MIPS16OP_MASK_IMM6 0x3f
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#define MIPS16OP_SH_IMM6 5
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/* These are the characters which may appears in the args field of an
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instruction. They appear in the order in which the fields appear
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when the instruction is used. Commas and parentheses in the args
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string are ignored when assembling, and written into the output
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when disassembling.
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"y" 3 bit register (MIPS16OP_*_RY)
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"x" 3 bit register (MIPS16OP_*_RX)
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"z" 3 bit register (MIPS16OP_*_RZ)
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"Z" 3 bit register (MIPS16OP_*_MOVE32Z)
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"v" 3 bit same register as source and destination (MIPS16OP_*_RX)
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"w" 3 bit same register as source and destination (MIPS16OP_*_RY)
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"0" zero register ($0)
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"S" stack pointer ($sp or $29)
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"P" program counter
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"R" return address register ($ra or $31)
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"X" 5 bit MIPS register (MIPS16OP_*_REGR32)
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"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
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"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
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"a" 26 bit jump address
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"e" 11 bit extension value
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"l" register list for entry instruction
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"L" register list for exit instruction
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The remaining codes may be extended. Except as otherwise noted,
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the full extended operand is a 16 bit signed value.
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"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
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">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
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"[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
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"]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
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"4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
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"5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
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"H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
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"W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
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"D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
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"j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
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"8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
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"V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
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"C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
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"U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
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"k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
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"K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
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"p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
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"q" 11 bit branch address (MIPS16OP_*_IMM11)
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"A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
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"B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
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"E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
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*/
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/* For the mips16, we use the same opcode table format and a few of
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the same flags. However, most of the flags are different. */
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/* Modifies the register in MIPS16OP_*_RX. */
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#define MIPS16_INSN_WRITE_X 0x00000001
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/* Modifies the register in MIPS16OP_*_RY. */
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#define MIPS16_INSN_WRITE_Y 0x00000002
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/* Modifies the register in MIPS16OP_*_RZ. */
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#define MIPS16_INSN_WRITE_Z 0x00000004
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/* Modifies the T ($24) register. */
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#define MIPS16_INSN_WRITE_T 0x00000008
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/* Modifies the SP ($29) register. */
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#define MIPS16_INSN_WRITE_SP 0x00000010
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/* Modifies the RA ($31) register. */
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#define MIPS16_INSN_WRITE_31 0x00000020
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/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
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#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
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/* Reads the register in MIPS16OP_*_RX. */
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#define MIPS16_INSN_READ_X 0x00000080
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/* Reads the register in MIPS16OP_*_RY. */
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#define MIPS16_INSN_READ_Y 0x00000100
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/* Reads the register in MIPS16OP_*_MOVE32Z. */
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#define MIPS16_INSN_READ_Z 0x00000200
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/* Reads the T ($24) register. */
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#define MIPS16_INSN_READ_T 0x00000400
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/* Reads the SP ($29) register. */
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#define MIPS16_INSN_READ_SP 0x00000800
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/* Reads the RA ($31) register. */
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#define MIPS16_INSN_READ_31 0x00001000
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/* Reads the program counter. */
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#define MIPS16_INSN_READ_PC 0x00002000
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/* Reads the general purpose register in MIPS16OP_*_REGR32. */
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#define MIPS16_INSN_READ_GPR_X 0x00004000
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/* The following flags have the same value for the mips16 opcode
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table:
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INSN_UNCOND_BRANCH_DELAY
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INSN_COND_BRANCH_DELAY
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INSN_COND_BRANCH_LIKELY (never used)
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INSN_READ_HI
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INSN_READ_LO
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INSN_WRITE_HI
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INSN_WRITE_LO
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INSN_TRAP
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INSN_ISA3
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*/
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extern const struct mips_opcode mips16_opcodes[];
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extern const int bfd_mips16_num_opcodes;
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#endif /* _MIPS_H_ */
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