include/opcode/
* h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove. (IMM8U, IMM8U_NS): Define. (h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy. gas/ * config/tc-h8300.c (get_specific): Allow ':8' to be used for unsigned 8-bit operands. gas/testsuite/ * gas/h8300/h8sx_mov_imm.[sd]: Add tests for mov.[wl] #xx:8,@yy.
This commit is contained in:
parent
8d1e520a64
commit
2d0d09ca83
7 changed files with 49 additions and 7 deletions
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@ -1,3 +1,8 @@
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2003-06-25 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-h8300.c (get_specific): Allow ':8' to be used for
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unsigned 8-bit operands.
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2003-06-24 Nick Clifton <nickc@redhat.com>
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2003-06-24 Nick Clifton <nickc@redhat.com>
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* read.c (s_comm): Change error message to assume an unsigned size
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* read.c (s_comm): Change error message to assume an unsigned size
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@ -1302,6 +1302,7 @@ get_specific (instruction, operands, size)
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#endif
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#endif
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if (((x_size == L_16 && op_size == L_16U)
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if (((x_size == L_16 && op_size == L_16U)
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|| (x_size == L_8 && op_size == L_8U)
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|| (x_size == L_3 && op_size == L_3NZ))
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|| (x_size == L_3 && op_size == L_3NZ))
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/* We're deliberately more permissive for ABS modes. */
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/* We're deliberately more permissive for ABS modes. */
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&& (op_mode == ABS
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&& (op_mode == ABS
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@ -1,3 +1,7 @@
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2003-06-25 Richard Sandiford <rsandifo@redhat.com>
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* gas/h8300/h8sx_mov_imm.[sd]: Add tests for mov.[wl] #xx:8,@yy.
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2003-06-24 Richard Sandiford <rsandifo@redhat.com>
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2003-06-24 Richard Sandiford <rsandifo@redhat.com>
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* gas/h8300/h8300.exp (h8sx_disp2, h8sx_rtsl, h8sx_mov_imm): Move...
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* gas/h8300/h8300.exp (h8sx_disp2, h8sx_rtsl, h8sx_mov_imm): Move...
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@ -289,5 +289,19 @@ Disassembly of section \.text:
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.*: 00 00 48 00 *
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.*: 00 00 48 00 *
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.*: 00 01 80 00 *
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.*: 00 01 80 00 *
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.*: R_H8_DIR32 bar
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.*: R_H8_DIR32 bar
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.*: 79 74 ff ff * 79 74 ff ff 00 00 * mov.w #0xffff,@r0
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.*: 00 00 *
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.*: 01 5d 00 00 * 01 5d 00 00 * mov.w #0x0,@r0
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.*: 01 5d 00 01 * 01 5d 00 01 * mov.w #0x1,@r0
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.*: 01 5d 00 ff * 01 5d 00 ff * mov.w #0xff,@r0
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.*: 79 74 01 00 * 79 74 01 00 00 00 * mov.w #0x100,@r0
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.*: 00 00 *
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.*: 7a 74 ff ff * 7a 74 ff ff ff ff 00 00 * mov.l #0xffffffff,@r0
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.*: ff ff 00 00 *
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.*: 01 0d 00 00 * 01 0d 00 00 * mov.l #0x0,@r0
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.*: 01 0d 00 01 * 01 0d 00 01 * mov.l #0x1,@r0
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.*: 01 0d 00 ff * 01 0d 00 ff * mov.l #0xff,@r0
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.*: 7a 7c 01 00 * 7a 7c 01 00 00 00 * mov.l #0x100,@r0
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.*: 00 00 *
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.* <.*>:
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.* <.*>:
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\.\.\.
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\.\.\.
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@ -93,6 +93,18 @@
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mov.l #.L1,@0x18000
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mov.l #.L1,@0x18000
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mov.l #bar,@0x18000
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mov.l #bar,@0x18000
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mov.w #-1,@er0
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mov.w #0,@er0
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mov.w #1,@er0
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mov.w #0xff,@er0
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mov.w #0x100,@er0
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mov.l #-1,@er0
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mov.l #0,@er0
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mov.l #1,@er0
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mov.l #0xff,@er0
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mov.l #0x100,@er0
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.globl bar
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.globl bar
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bar:
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bar:
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.space 16
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.space 16
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@ -1,7 +1,13 @@
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2003-06-25 Richard Sandiford <rsandifo@redhat.com>
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2003-06-25 Richard Sandiford <rsandifo@redhat.com>
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* include/opcode/h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd
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* h8300.h (IMM2_NS, IMM8_NS, IMM16_NS): Remove.
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and mov.l ERs,@(dd:32,ERd) entries.
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(IMM8U, IMM8U_NS): Define.
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(h8_opcodes): Use IMM8U_NS for mov.[wl] #xx:8,@yy.
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2003-06-25 Richard Sandiford <rsandifo@redhat.com>
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* h8300.h (h8_opcodes): Fix the mov.l @(dd:32,ERs),ERd and
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mov.l ERs,@(dd:32,ERd) entries.
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2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
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2003-06-23 H.J. Lu <hongjiu.lu@intel.com>
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@ -117,6 +117,7 @@ enum h8_flags {
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B31 = 0x40000000, /* Bit 3 must be high. */
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B31 = 0x40000000, /* Bit 3 must be high. */
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E = 0x80000000, /* End of nibble sequence. */
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E = 0x80000000, /* End of nibble sequence. */
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/* Immediates smaller than 8 bits are always unsigned. */
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IMM3 = IMM | L_3,
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IMM3 = IMM | L_3,
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IMM4 = IMM | L_4,
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IMM4 = IMM | L_4,
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IMM5 = IMM | L_5,
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IMM5 = IMM | L_5,
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@ -124,15 +125,14 @@ enum h8_flags {
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IMM2 = IMM | L_2,
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IMM2 = IMM | L_2,
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IMM8 = IMM | SRC | L_8,
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IMM8 = IMM | SRC | L_8,
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IMM8U = IMM | SRC | L_8U,
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IMM16 = IMM | SRC | L_16,
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IMM16 = IMM | SRC | L_16,
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IMM16U = IMM | SRC | L_16U,
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IMM16U = IMM | SRC | L_16U,
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IMM32 = IMM | SRC | L_32,
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IMM32 = IMM | SRC | L_32,
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IMM3NZ_NS = IMM3NZ | NO_SYMBOLS,
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IMM3NZ_NS = IMM3NZ | NO_SYMBOLS,
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IMM2_NS = IMM2 | NO_SYMBOLS,
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IMM4_NS = IMM4 | NO_SYMBOLS,
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IMM4_NS = IMM4 | NO_SYMBOLS,
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IMM8_NS = IMM8 | NO_SYMBOLS,
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IMM8U_NS = IMM8U | NO_SYMBOLS,
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IMM16_NS = IMM16 | NO_SYMBOLS,
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IMM16U_NS = IMM16U | NO_SYMBOLS,
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IMM16U_NS = IMM16U | NO_SYMBOLS,
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RD8 = DST | L_8 | REG,
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RD8 = DST | L_8 | REG,
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{O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}},
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{O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS16DST, E}}, {{0x6, 0xb, 0xd, IMM4, DSTABS16LIST, E}}},
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{O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}},
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{O (O_MOV, SW), AV_H8SX, 0, "mov.w", {{IMM4_NS, ABS32DST, E}}, {{0x6, 0xb, 0xf, IMM4, DSTABS32LIST, E}}},
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MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8_NS),
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MOVFROM_IMM8 (O (O_MOV, SW), PREFIX_015D, "mov.w", IMM8U_NS),
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MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST),
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MOVFROM_IMM (O (O_MOV, SW), PREFIX_7974, "mov.w", IMM16, IMM16LIST),
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{O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}},
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{O (O_MOV, SW), AV_H8, 2, "mov.w", {{RS16, RD16, E}}, {{0x0, 0xD, RS16, RD16, E}}},
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{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
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{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM3NZ_NS, RD32, E}}, {{0x0, 0xf, B31 | IMM3NZ, B31 | RD32, E}}},
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MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8_NS),
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MOVFROM_IMM8 (O (O_MOV, SL), PREFIX_010D, "mov.l", IMM8U_NS),
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MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST),
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MOVFROM_IMM (O (O_MOV, SL), PREFIX_7A7C, "mov.l", IMM16U_NS, IMM16ULIST),
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{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}},
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{O (O_MOV, SL), AV_H8SX, 0, "mov.l", {{IMM16U_NS, RD32, E}}, {{0x7, 0xa, 0x0, B31 | RD32, IMM16ULIST, E}}},
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