Add AVX512IFMA instructions
gas/ * config/tc-i386.c (cpu_arch): Add .avx512ifma. * doc/c-i386.texi: Document it. opcodes/ * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq. * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4, PREFIX_EVEX_0F38B5. * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS. (cpu_flags): Add CpuAVX512IFMA. * i386-opc.h (enum): Add CpuAVX512IFMA. (i386_cpu_flags): Add cpuavx512ifma. * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. /gas/testsuite/ * gas/i386/i386.exp: Run new tests. * gas/i386/avx512ifma-intel.d: New file. * gas/i386/avx512ifma.d: Likewise. * gas/i386/avx512ifma.s: Likewise. * gas/i386/avx512ifma_vl-intel.d: Likewise. * gas/i386/avx512ifma_vl.d: Likewise. * gas/i386/avx512ifma_vl.s: Likewise. * gas/i386/x86-64-avx512ifma-intel.d: Likewise. * gas/i386/x86-64-avx512ifma.d: Likewise. * gas/i386/x86-64-avx512ifma.s: Likewise. * gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise. * gas/i386/x86-64-avx512ifma_vl.d: Likewise. * gas/i386/x86-64-avx512ifma_vl.s: Likewise.
This commit is contained in:
Ilya Tocar
H.J. Lu
parent
9d8596f079
commit
2cc1b5aad8
25 changed files with 6818 additions and 5513 deletions
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@ -1,3 +1,8 @@
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* config/tc-i386.c (cpu_arch): Add .avx512ifma.
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* doc/c-i386.texi: Document it.
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* config/tc-i386.c (cpu_arch): Add .pcommit.
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@ -933,6 +933,8 @@ static const arch_entry cpu_arch[] =
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CPU_CLWB_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".pcommit"), PROCESSOR_UNKNOWN,
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CPU_PCOMMIT_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".avx512ifma"), PROCESSOR_UNKNOWN,
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CPU_AVX512IFMA_FLAGS, 0, 0 },
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};
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#ifdef I386COFF
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@ -163,6 +163,7 @@ accept various extension mnemonics. For example,
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@code{avx512vl},
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@code{avx512bw},
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@code{avx512dq},
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@code{avx512ifma},
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@code{noavx},
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@code{vmx},
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@code{vmfunc},
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@ -1104,7 +1105,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
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@item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
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@item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
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@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq}
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@item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
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@item @samp{.clwb} @tab @samp{.pcommit}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@ -1,3 +1,19 @@
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* gas/i386/i386.exp: Run new tests.
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* gas/i386/avx512ifma-intel.d: New file.
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* gas/i386/avx512ifma.d: Likewise.
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* gas/i386/avx512ifma.s: Likewise.
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* gas/i386/avx512ifma_vl-intel.d: Likewise.
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* gas/i386/avx512ifma_vl.d: Likewise.
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* gas/i386/avx512ifma_vl.s: Likewise.
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* gas/i386/x86-64-avx512ifma-intel.d: Likewise.
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* gas/i386/x86-64-avx512ifma.d: Likewise.
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* gas/i386/x86-64-avx512ifma.s: Likewise.
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* gas/i386/x86-64-avx512ifma_vl-intel.d: Likewise.
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* gas/i386/x86-64-avx512ifma_vl.d: Likewise.
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* gas/i386/x86-64-avx512ifma_vl.s: Likewise.
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2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
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* gas/i386/i386.exp: Run new tests.
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68
gas/testsuite/gas/i386/avx512ifma-intel.d
Normal file
68
gas/testsuite/gas/i386/avx512ifma-intel.d
Normal file
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@ -0,0 +1,68 @@
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#as:
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#objdump: -dw -Mintel
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#name: i386 AVX512IFMA insns (Intel disassembly)
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#source: avx512ifma.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 f4[ ]*vpmadd52luq zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b4 f4[ ]*vpmadd52luq zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b4 f4[ ]*vpmadd52luq zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 31[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 30[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[eax\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 7f[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 00 20 00 00[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 80[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 c0 df ff ff[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 7f[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 00 04 00 00[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 80[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 f8 fb ff ff[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 f4[ ]*vpmadd52huq zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b5 f4[ ]*vpmadd52huq zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b5 f4[ ]*vpmadd52huq zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 31[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 30[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[eax\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 7f[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 00 20 00 00[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 80[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 c0 df ff ff[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 7f[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 00 04 00 00[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 80[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 f8 fb ff ff[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 f4[ ]*vpmadd52luq zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b4 f4[ ]*vpmadd52luq zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b4 f4[ ]*vpmadd52luq zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 31[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 30[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[eax\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 7f[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 00 20 00 00[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 80[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 c0 df ff ff[ ]*vpmadd52luq zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 7f[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 00 04 00 00[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 80[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 f8 fb ff ff[ ]*vpmadd52luq zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 f4[ ]*vpmadd52huq zmm6,zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b5 f4[ ]*vpmadd52huq zmm6\{k7\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b5 f4[ ]*vpmadd52huq zmm6\{k7\}\{z\},zmm5,zmm4
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 31[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[ecx\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 30[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[eax\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 7f[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 00 20 00 00[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 80[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 c0 df ff ff[ ]*vpmadd52huq zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 7f[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx\+0x3f8\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 00 04 00 00[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx\+0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 80[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx-0x400\]\{1to8\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 f8 fb ff ff[ ]*vpmadd52huq zmm6,zmm5,QWORD PTR \[edx-0x408\]\{1to8\}
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#pass
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68
gas/testsuite/gas/i386/avx512ifma.d
Normal file
68
gas/testsuite/gas/i386/avx512ifma.d
Normal file
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@ -0,0 +1,68 @@
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#as:
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#objdump: -dw
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#name: i386 AVX512IFMA insns
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#source: avx512ifma.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6\{%k7\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 31[ ]*vpmadd52luq \(%ecx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 30[ ]*vpmadd52luq \(%eax\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 7f[ ]*vpmadd52luq 0x1fc0\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 00 20 00 00[ ]*vpmadd52luq 0x2000\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 80[ ]*vpmadd52luq -0x2000\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 c0 df ff ff[ ]*vpmadd52luq -0x2040\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 f4[ ]*vpmadd52huq %zmm4,%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b5 f4[ ]*vpmadd52huq %zmm4,%zmm5,%zmm6\{%k7\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b5 f4[ ]*vpmadd52huq %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 31[ ]*vpmadd52huq \(%ecx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 30[ ]*vpmadd52huq \(%eax\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 7f[ ]*vpmadd52huq 0x1fc0\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 00 20 00 00[ ]*vpmadd52huq 0x2000\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 80[ ]*vpmadd52huq -0x2000\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 c0 df ff ff[ ]*vpmadd52huq -0x2040\(%edx\),%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to8\},%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6\{%k7\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b4 f4[ ]*vpmadd52luq %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
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[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 31[ ]*vpmadd52luq \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 30[ ]*vpmadd52luq \(%eax\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 7f[ ]*vpmadd52luq 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 00 20 00 00[ ]*vpmadd52luq 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 72 80[ ]*vpmadd52luq -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b4 b2 c0 df ff ff[ ]*vpmadd52luq -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 f4[ ]*vpmadd52huq %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f b5 f4[ ]*vpmadd52huq %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf b5 f4[ ]*vpmadd52huq %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 31[ ]*vpmadd52huq \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 30[ ]*vpmadd52huq \(%eax\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 7f[ ]*vpmadd52huq 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 00 20 00 00[ ]*vpmadd52huq 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 72 80[ ]*vpmadd52huq -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 b5 b2 c0 df ff ff[ ]*vpmadd52huq -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 58 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to8\},%zmm5,%zmm6
|
||||
#pass
|
||||
63
gas/testsuite/gas/i386/avx512ifma.s
Normal file
63
gas/testsuite/gas/i386/avx512ifma.s
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
# Check 32bit AVX512IFMA instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpmadd52luq %zmm4, %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52luq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA
|
||||
vpmadd52luq %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512IFMA
|
||||
vpmadd52luq (%ecx), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52luq -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52luq (%eax){1to8}, %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52luq 8128(%edx), %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52luq 8192(%edx), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52luq -8192(%edx), %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52luq -8256(%edx), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52luq 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52luq 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52luq -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52luq -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq %zmm4, %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq %zmm4, %zmm5, %zmm6{%k7} # AVX512IFMA
|
||||
vpmadd52huq %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512IFMA
|
||||
vpmadd52huq (%ecx), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq (%eax){1to8}, %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq 8128(%edx), %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52huq 8192(%edx), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq -8192(%edx), %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52huq -8256(%edx), %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq 1016(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52huq 1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA
|
||||
vpmadd52huq -1024(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA Disp8
|
||||
vpmadd52huq -1032(%edx){1to8}, %zmm5, %zmm6 # AVX512IFMA
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpmadd52luq zmm6, zmm5, zmm4 # AVX512IFMA
|
||||
vpmadd52luq zmm6{k7}, zmm5, zmm4 # AVX512IFMA
|
||||
vpmadd52luq zmm6{k7}{z}, zmm5, zmm4 # AVX512IFMA
|
||||
vpmadd52luq zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512IFMA
|
||||
vpmadd52luq zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512IFMA
|
||||
vpmadd52luq zmm6, zmm5, [eax]{1to8} # AVX512IFMA
|
||||
vpmadd52luq zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512IFMA
|
||||
vpmadd52luq zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512IFMA
|
||||
vpmadd52luq zmm6, zmm5, [edx+1016]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm6, zmm5, [edx+1024]{1to8} # AVX512IFMA
|
||||
vpmadd52luq zmm6, zmm5, [edx-1024]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm6, zmm5, [edx-1032]{1to8} # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, zmm4 # AVX512IFMA
|
||||
vpmadd52huq zmm6{k7}, zmm5, zmm4 # AVX512IFMA
|
||||
vpmadd52huq zmm6{k7}{z}, zmm5, zmm4 # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, [eax]{1to8} # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, [edx+1016]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm6, zmm5, [edx+1024]{1to8} # AVX512IFMA
|
||||
vpmadd52huq zmm6, zmm5, [edx-1024]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm6, zmm5, [edx-1032]{1to8} # AVX512IFMA
|
||||
116
gas/testsuite/gas/i386/avx512ifma_vl-intel.d
Normal file
116
gas/testsuite/gas/i386/avx512ifma_vl-intel.d
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 AVX512IFMA/VL insns (Intel disassembly)
|
||||
#source: avx512ifma_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 f4[ ]*vpmadd52luq xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b4 f4[ ]*vpmadd52luq xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 31[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 30[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 7f[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 00 08 00 00[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 80[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 f0 f7 ff ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 7f[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 00 04 00 00[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 80[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 f4[ ]*vpmadd52luq ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b4 f4[ ]*vpmadd52luq ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 31[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 30[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 7f[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 00 10 00 00[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 80[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 e0 ef ff ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 7f[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 00 04 00 00[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 80[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 f4[ ]*vpmadd52huq xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b5 f4[ ]*vpmadd52huq xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 31[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 30[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 7f[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 00 08 00 00[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 80[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 f0 f7 ff ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 7f[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 00 04 00 00[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 80[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 f4[ ]*vpmadd52huq ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b5 f4[ ]*vpmadd52huq ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 31[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 30[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 7f[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 00 10 00 00[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 80[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 e0 ef ff ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 7f[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 00 04 00 00[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 80[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 f4[ ]*vpmadd52luq xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b4 f4[ ]*vpmadd52luq xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 31[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 30[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 7f[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 00 08 00 00[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 80[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 f0 f7 ff ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 7f[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 00 04 00 00[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 80[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 f4[ ]*vpmadd52luq ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b4 f4[ ]*vpmadd52luq ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 31[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 30[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 7f[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 00 10 00 00[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 80[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 e0 ef ff ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 7f[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 00 04 00 00[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 80[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 f4[ ]*vpmadd52huq xmm6\{k7\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b5 f4[ ]*vpmadd52huq xmm6\{k7\}\{z\},xmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 31[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 30[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[eax\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 7f[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 00 08 00 00[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 80[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 f0 f7 ff ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 7f[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 00 04 00 00[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 80[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq xmm6\{k7\},xmm5,QWORD PTR \[edx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 f4[ ]*vpmadd52huq ymm6\{k7\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b5 f4[ ]*vpmadd52huq ymm6\{k7\}\{z\},ymm5,ymm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 31[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 30[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[eax\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 7f[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 00 10 00 00[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 80[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 e0 ef ff ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 7f[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 00 04 00 00[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 80[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm6\{k7\},ymm5,QWORD PTR \[edx-0x408\]\{1to4\}
|
||||
#pass
|
||||
116
gas/testsuite/gas/i386/avx512ifma_vl.d
Normal file
116
gas/testsuite/gas/i386/avx512ifma_vl.d
Normal file
|
|
@ -0,0 +1,116 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512IFMA/VL insns
|
||||
#source: avx512ifma_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 f4[ ]*vpmadd52luq %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b4 f4[ ]*vpmadd52luq %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 31[ ]*vpmadd52luq \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 30[ ]*vpmadd52luq \(%eax\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 7f[ ]*vpmadd52luq 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 00 08 00 00[ ]*vpmadd52luq 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 80[ ]*vpmadd52luq -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 f0 f7 ff ff[ ]*vpmadd52luq -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 f4[ ]*vpmadd52luq %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b4 f4[ ]*vpmadd52luq %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 31[ ]*vpmadd52luq \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 30[ ]*vpmadd52luq \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 7f[ ]*vpmadd52luq 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 00 10 00 00[ ]*vpmadd52luq 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 80[ ]*vpmadd52luq -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 e0 ef ff ff[ ]*vpmadd52luq -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 f4[ ]*vpmadd52huq %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b5 f4[ ]*vpmadd52huq %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 31[ ]*vpmadd52huq \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 30[ ]*vpmadd52huq \(%eax\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 7f[ ]*vpmadd52huq 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 00 08 00 00[ ]*vpmadd52huq 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 80[ ]*vpmadd52huq -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 f0 f7 ff ff[ ]*vpmadd52huq -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 f4[ ]*vpmadd52huq %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b5 f4[ ]*vpmadd52huq %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 31[ ]*vpmadd52huq \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 30[ ]*vpmadd52huq \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 7f[ ]*vpmadd52huq 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 00 10 00 00[ ]*vpmadd52huq 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 80[ ]*vpmadd52huq -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 e0 ef ff ff[ ]*vpmadd52huq -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 f4[ ]*vpmadd52luq %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b4 f4[ ]*vpmadd52luq %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 31[ ]*vpmadd52luq \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 30[ ]*vpmadd52luq \(%eax\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 7f[ ]*vpmadd52luq 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 00 08 00 00[ ]*vpmadd52luq 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 72 80[ ]*vpmadd52luq -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b4 b2 f0 f7 ff ff[ ]*vpmadd52luq -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 f4[ ]*vpmadd52luq %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b4 f4[ ]*vpmadd52luq %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 31[ ]*vpmadd52luq \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b4 f4 c0 1d fe ff[ ]*vpmadd52luq -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 30[ ]*vpmadd52luq \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 7f[ ]*vpmadd52luq 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 00 10 00 00[ ]*vpmadd52luq 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 72 80[ ]*vpmadd52luq -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b4 b2 e0 ef ff ff[ ]*vpmadd52luq -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 7f[ ]*vpmadd52luq 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 72 80[ ]*vpmadd52luq -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 f4[ ]*vpmadd52huq %xmm4,%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 8f b5 f4[ ]*vpmadd52huq %xmm4,%xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 31[ ]*vpmadd52huq \(%ecx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq -0x1e240\(%esp,%esi,8\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 30[ ]*vpmadd52huq \(%eax\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 7f[ ]*vpmadd52huq 0x7f0\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 00 08 00 00[ ]*vpmadd52huq 0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 72 80[ ]*vpmadd52huq -0x800\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 0f b5 b2 f0 f7 ff ff[ ]*vpmadd52huq -0x810\(%edx\),%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 1f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to2\},%xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 f4[ ]*vpmadd52huq %ymm4,%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 af b5 f4[ ]*vpmadd52huq %ymm4,%ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 31[ ]*vpmadd52huq \(%ecx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b4 f4 c0 1d fe ff[ ]*vpmadd52huq -0x1e240\(%esp,%esi,8\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 30[ ]*vpmadd52huq \(%eax\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 7f[ ]*vpmadd52huq 0xfe0\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 00 10 00 00[ ]*vpmadd52huq 0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 72 80[ ]*vpmadd52huq -0x1000\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 2f b5 b2 e0 ef ff ff[ ]*vpmadd52huq -0x1020\(%edx\),%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 7f[ ]*vpmadd52huq 0x3f8\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 72 80[ ]*vpmadd52huq -0x400\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 3f b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%edx\)\{1to4\},%ymm5,%ymm6\{%k7\}
|
||||
#pass
|
||||
111
gas/testsuite/gas/i386/avx512ifma_vl.s
Normal file
111
gas/testsuite/gas/i386/avx512ifma_vl.s
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
# Check 32bit AVX512{IFMA,VL} instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpmadd52luq %xmm4, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%ecx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq %ymm4, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%ecx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq %xmm4, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq %xmm4, %xmm5, %xmm6{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%ecx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq -123456(%esp,%esi,8), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%eax){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq 2032(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq -2048(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -2064(%edx), %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq 1016(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq -1024(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -1032(%edx){1to2}, %xmm5, %xmm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq %ymm4, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq %ymm4, %ymm5, %ymm6{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%ecx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq -123456(%esp,%esi,8), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%eax){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq 4064(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq -4096(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -4128(%edx), %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq 1016(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq -1024(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -1032(%edx){1to4}, %ymm5, %ymm6{%k7} # AVX512{IFMA,VL}
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpmadd52luq xmm6{k7}, xmm5, xmm4 # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}{z}, xmm5, xmm4 # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, ymm4 # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}{z}, ymm5, ymm4 # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, [eax]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, [edx+1016]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm6{k7}, ymm5, [edx+1024]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm6{k7}, ymm5, [edx-1024]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm6{k7}, ymm5, [edx-1032]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, xmm4 # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}{z}, xmm5, xmm4 # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [ecx] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, [eax]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx+2032] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx+2048] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx-2048] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm6{k7}, xmm5, XMMWORD PTR [edx-2064] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, [edx+1016]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm6{k7}, xmm5, [edx+1024]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm6{k7}, xmm5, [edx-1024]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm6{k7}, xmm5, [edx-1032]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, ymm4 # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}{z}, ymm5, ymm4 # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [ecx] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [esp+esi*8-123456] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, [eax]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx+4064] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx+4096] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx-4096] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm6{k7}, ymm5, YMMWORD PTR [edx-4128] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, [edx+1016]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm6{k7}, ymm5, [edx+1024]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm6{k7}, ymm5, [edx-1024]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm6{k7}, ymm5, [edx-1032]{1to4} # AVX512{IFMA,VL}
|
||||
|
|
@ -334,6 +334,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "clwb-intel"
|
||||
run_dump_test "pcommit"
|
||||
run_dump_test "pcommit-intel"
|
||||
run_dump_test "avx512ifma"
|
||||
run_dump_test "avx512ifma-intel"
|
||||
run_dump_test "avx512ifma_vl"
|
||||
run_dump_test "avx512ifma_vl-intel"
|
||||
run_dump_test "disassem"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
|
|
@ -689,6 +693,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-clwb-intel"
|
||||
run_dump_test "x86-64-pcommit"
|
||||
run_dump_test "x86-64-pcommit-intel"
|
||||
run_dump_test "x86-64-avx512ifma"
|
||||
run_dump_test "x86-64-avx512ifma-intel"
|
||||
run_dump_test "x86-64-avx512ifma_vl"
|
||||
run_dump_test "x86-64-avx512ifma_vl-intel"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
68
gas/testsuite/gas/i386/x86-64-avx512ifma-intel.d
Normal file
68
gas/testsuite/gas/i386/x86-64-avx512ifma-intel.d
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX512IFMA insns (Intel disassembly)
|
||||
#source: x86-64-avx512ifma.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b4 f4[ ]*vpmadd52luq zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b4 f4[ ]*vpmadd52luq zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b4 f4[ ]*vpmadd52luq zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 31[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b4 b4 f0 23 01 00 00[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 31[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 7f[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 00 20 00 00[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 80[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 c0 df ff ff[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 7f[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 00 04 00 00[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 80[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 f8 fb ff ff[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b5 f4[ ]*vpmadd52huq zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b5 f4[ ]*vpmadd52huq zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b5 f4[ ]*vpmadd52huq zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 31[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b5 b4 f0 23 01 00 00[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 31[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 7f[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 00 20 00 00[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 80[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 c0 df ff ff[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 7f[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 00 04 00 00[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 80[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 f8 fb ff ff[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b4 f4[ ]*vpmadd52luq zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b4 f4[ ]*vpmadd52luq zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b4 f4[ ]*vpmadd52luq zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 31[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b4 b4 f0 34 12 00 00[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 31[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 7f[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 00 20 00 00[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 80[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 c0 df ff ff[ ]*vpmadd52luq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 7f[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 00 04 00 00[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 80[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 f8 fb ff ff[ ]*vpmadd52luq zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b5 f4[ ]*vpmadd52huq zmm30,zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b5 f4[ ]*vpmadd52huq zmm30\{k7\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b5 f4[ ]*vpmadd52huq zmm30\{k7\}\{z\},zmm29,zmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 31[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b5 b4 f0 34 12 00 00[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 31[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rcx\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 7f[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 00 20 00 00[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 80[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 c0 df ff ff[ ]*vpmadd52huq zmm30,zmm29,ZMMWORD PTR \[rdx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 7f[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx\+0x3f8\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 00 04 00 00[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx\+0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 80[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx-0x400\]\{1to8\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 f8 fb ff ff[ ]*vpmadd52huq zmm30,zmm29,QWORD PTR \[rdx-0x408\]\{1to8\}
|
||||
#pass
|
||||
68
gas/testsuite/gas/i386/x86-64-avx512ifma.d
Normal file
68
gas/testsuite/gas/i386/x86-64-avx512ifma.d
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512IFMA insns
|
||||
#source: x86-64-avx512ifma.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b4 f4[ ]*vpmadd52luq %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b4 f4[ ]*vpmadd52luq %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b4 f4[ ]*vpmadd52luq %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 31[ ]*vpmadd52luq \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b4 b4 f0 23 01 00 00[ ]*vpmadd52luq 0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 7f[ ]*vpmadd52luq 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 00 20 00 00[ ]*vpmadd52luq 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 80[ ]*vpmadd52luq -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 c0 df ff ff[ ]*vpmadd52luq -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b5 f4[ ]*vpmadd52huq %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b5 f4[ ]*vpmadd52huq %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b5 f4[ ]*vpmadd52huq %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 31[ ]*vpmadd52huq \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b5 b4 f0 23 01 00 00[ ]*vpmadd52huq 0x123\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 7f[ ]*vpmadd52huq 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 00 20 00 00[ ]*vpmadd52huq 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 80[ ]*vpmadd52huq -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 c0 df ff ff[ ]*vpmadd52huq -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b4 f4[ ]*vpmadd52luq %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b4 f4[ ]*vpmadd52luq %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b4 f4[ ]*vpmadd52luq %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 31[ ]*vpmadd52luq \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b4 b4 f0 34 12 00 00[ ]*vpmadd52luq 0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 7f[ ]*vpmadd52luq 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 00 20 00 00[ ]*vpmadd52luq 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 72 80[ ]*vpmadd52luq -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b4 b2 c0 df ff ff[ ]*vpmadd52luq -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 40 b5 f4[ ]*vpmadd52huq %zmm28,%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 47 b5 f4[ ]*vpmadd52huq %zmm28,%zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 c7 b5 f4[ ]*vpmadd52huq %zmm28,%zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 31[ ]*vpmadd52huq \(%rcx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 40 b5 b4 f0 34 12 00 00[ ]*vpmadd52huq 0x1234\(%rax,%r14,8\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 7f[ ]*vpmadd52huq 0x1fc0\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 00 20 00 00[ ]*vpmadd52huq 0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 72 80[ ]*vpmadd52huq -0x2000\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 40 b5 b2 c0 df ff ff[ ]*vpmadd52huq -0x2040\(%rdx\),%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 50 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to8\},%zmm29,%zmm30
|
||||
#pass
|
||||
63
gas/testsuite/gas/i386/x86-64-avx512ifma.s
Normal file
63
gas/testsuite/gas/i386/x86-64-avx512ifma.s
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
# Check 64bit AVX512IFMA instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpmadd52luq %zmm28, %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52luq %zmm28, %zmm29, %zmm30{%k7} # AVX512IFMA
|
||||
vpmadd52luq %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512IFMA
|
||||
vpmadd52luq (%rcx), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52luq 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52luq (%rcx){1to8}, %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52luq 8128(%rdx), %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52luq 8192(%rdx), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52luq -8192(%rdx), %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52luq -8256(%rdx), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52luq 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52luq 1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52luq -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52luq -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq %zmm28, %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq %zmm28, %zmm29, %zmm30{%k7} # AVX512IFMA
|
||||
vpmadd52huq %zmm28, %zmm29, %zmm30{%k7}{z} # AVX512IFMA
|
||||
vpmadd52huq (%rcx), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq 0x123(%rax,%r14,8), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq (%rcx){1to8}, %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq 8128(%rdx), %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52huq 8192(%rdx), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq -8192(%rdx), %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52huq -8256(%rdx), %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq 1016(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52huq 1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA
|
||||
vpmadd52huq -1024(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA Disp8
|
||||
vpmadd52huq -1032(%rdx){1to8}, %zmm29, %zmm30 # AVX512IFMA
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpmadd52luq zmm30, zmm29, zmm28 # AVX512IFMA
|
||||
vpmadd52luq zmm30{k7}, zmm29, zmm28 # AVX512IFMA
|
||||
vpmadd52luq zmm30{k7}{z}, zmm29, zmm28 # AVX512IFMA
|
||||
vpmadd52luq zmm30, zmm29, ZMMWORD PTR [rcx] # AVX512IFMA
|
||||
vpmadd52luq zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512IFMA
|
||||
vpmadd52luq zmm30, zmm29, [rcx]{1to8} # AVX512IFMA
|
||||
vpmadd52luq zmm30, zmm29, ZMMWORD PTR [rdx+8128] # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm30, zmm29, ZMMWORD PTR [rdx+8192] # AVX512IFMA
|
||||
vpmadd52luq zmm30, zmm29, ZMMWORD PTR [rdx-8192] # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm30, zmm29, ZMMWORD PTR [rdx-8256] # AVX512IFMA
|
||||
vpmadd52luq zmm30, zmm29, [rdx+1016]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm30, zmm29, [rdx+1024]{1to8} # AVX512IFMA
|
||||
vpmadd52luq zmm30, zmm29, [rdx-1024]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52luq zmm30, zmm29, [rdx-1032]{1to8} # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, zmm28 # AVX512IFMA
|
||||
vpmadd52huq zmm30{k7}, zmm29, zmm28 # AVX512IFMA
|
||||
vpmadd52huq zmm30{k7}{z}, zmm29, zmm28 # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, ZMMWORD PTR [rcx] # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, ZMMWORD PTR [rax+r14*8+0x1234] # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, [rcx]{1to8} # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, ZMMWORD PTR [rdx+8128] # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm30, zmm29, ZMMWORD PTR [rdx+8192] # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, ZMMWORD PTR [rdx-8192] # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm30, zmm29, ZMMWORD PTR [rdx-8256] # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, [rdx+1016]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm30, zmm29, [rdx+1024]{1to8} # AVX512IFMA
|
||||
vpmadd52huq zmm30, zmm29, [rdx-1024]{1to8} # AVX512IFMA Disp8
|
||||
vpmadd52huq zmm30, zmm29, [rdx-1032]{1to8} # AVX512IFMA
|
||||
124
gas/testsuite/gas/i386/x86-64-avx512ifma_vl-intel.d
Normal file
124
gas/testsuite/gas/i386/x86-64-avx512ifma_vl-intel.d
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 AVX512IFMA/VL insns (Intel disassembly)
|
||||
#source: x86-64-avx512ifma_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b4 f4[ ]*vpmadd52luq xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b4 f4[ ]*vpmadd52luq xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b4 f4[ ]*vpmadd52luq xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 31[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b4 b4 f0 23 01 00 00[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 31[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rcx\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 7f[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 00 08 00 00[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 80[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 f0 f7 ff ff[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 7f[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 00 04 00 00[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 80[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 f8 fb ff ff[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b4 f4[ ]*vpmadd52luq ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b4 f4[ ]*vpmadd52luq ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b4 f4[ ]*vpmadd52luq ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 31[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b4 b4 f0 23 01 00 00[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 31[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 7f[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 00 10 00 00[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 80[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 e0 ef ff ff[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 7f[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 00 04 00 00[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 80[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b5 f4[ ]*vpmadd52huq xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b5 f4[ ]*vpmadd52huq xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b5 f4[ ]*vpmadd52huq xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 31[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b5 b4 f0 23 01 00 00[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 31[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rcx\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 7f[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 00 08 00 00[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 80[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 f0 f7 ff ff[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 7f[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 00 04 00 00[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 80[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 f8 fb ff ff[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b5 f4[ ]*vpmadd52huq ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b5 f4[ ]*vpmadd52huq ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b5 f4[ ]*vpmadd52huq ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 31[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b5 b4 f0 23 01 00 00[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x123\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 31[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 7f[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 00 10 00 00[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 80[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 e0 ef ff ff[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 7f[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 00 04 00 00[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 80[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b4 f4[ ]*vpmadd52luq xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b4 f4[ ]*vpmadd52luq xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b4 f4[ ]*vpmadd52luq xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 31[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b4 b4 f0 34 12 00 00[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 31[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rcx\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 7f[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 00 08 00 00[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 80[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 f0 f7 ff ff[ ]*vpmadd52luq xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 7f[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 00 04 00 00[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 80[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 f8 fb ff ff[ ]*vpmadd52luq xmm30,xmm29,QWORD PTR \[rdx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b4 f4[ ]*vpmadd52luq ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b4 f4[ ]*vpmadd52luq ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b4 f4[ ]*vpmadd52luq ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 31[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b4 b4 f0 34 12 00 00[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 31[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 7f[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 00 10 00 00[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 80[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 e0 ef ff ff[ ]*vpmadd52luq ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 7f[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 00 04 00 00[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 80[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 f8 fb ff ff[ ]*vpmadd52luq ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b5 f4[ ]*vpmadd52huq xmm30,xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b5 f4[ ]*vpmadd52huq xmm30\{k7\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b5 f4[ ]*vpmadd52huq xmm30\{k7\}\{z\},xmm29,xmm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 31[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b5 b4 f0 34 12 00 00[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 31[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rcx\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 7f[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 00 08 00 00[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 80[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 f0 f7 ff ff[ ]*vpmadd52huq xmm30,xmm29,XMMWORD PTR \[rdx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 7f[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx\+0x3f8\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 00 04 00 00[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx\+0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 80[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx-0x400\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 f8 fb ff ff[ ]*vpmadd52huq xmm30,xmm29,QWORD PTR \[rdx-0x408\]\{1to2\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b5 f4[ ]*vpmadd52huq ymm30,ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b5 f4[ ]*vpmadd52huq ymm30\{k7\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b5 f4[ ]*vpmadd52huq ymm30\{k7\}\{z\},ymm29,ymm28
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 31[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rcx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b5 b4 f0 34 12 00 00[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rax\+r14\*8\+0x1234\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 31[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rcx\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 7f[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 00 10 00 00[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 80[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 e0 ef ff ff[ ]*vpmadd52huq ymm30,ymm29,YMMWORD PTR \[rdx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 7f[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx\+0x3f8\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 00 04 00 00[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx\+0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 80[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx-0x400\]\{1to4\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 f8 fb ff ff[ ]*vpmadd52huq ymm30,ymm29,QWORD PTR \[rdx-0x408\]\{1to4\}
|
||||
#pass
|
||||
124
gas/testsuite/gas/i386/x86-64-avx512ifma_vl.d
Normal file
124
gas/testsuite/gas/i386/x86-64-avx512ifma_vl.d
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 AVX512IFMA/VL insns
|
||||
#source: x86-64-avx512ifma_vl.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b4 f4[ ]*vpmadd52luq %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b4 f4[ ]*vpmadd52luq %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b4 f4[ ]*vpmadd52luq %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 31[ ]*vpmadd52luq \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b4 b4 f0 23 01 00 00[ ]*vpmadd52luq 0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 7f[ ]*vpmadd52luq 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 00 08 00 00[ ]*vpmadd52luq 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 80[ ]*vpmadd52luq -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 f0 f7 ff ff[ ]*vpmadd52luq -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b4 f4[ ]*vpmadd52luq %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b4 f4[ ]*vpmadd52luq %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b4 f4[ ]*vpmadd52luq %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 31[ ]*vpmadd52luq \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b4 b4 f0 23 01 00 00[ ]*vpmadd52luq 0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 7f[ ]*vpmadd52luq 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 00 10 00 00[ ]*vpmadd52luq 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 80[ ]*vpmadd52luq -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 e0 ef ff ff[ ]*vpmadd52luq -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b5 f4[ ]*vpmadd52huq %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b5 f4[ ]*vpmadd52huq %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b5 f4[ ]*vpmadd52huq %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 31[ ]*vpmadd52huq \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b5 b4 f0 23 01 00 00[ ]*vpmadd52huq 0x123\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 7f[ ]*vpmadd52huq 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 00 08 00 00[ ]*vpmadd52huq 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 80[ ]*vpmadd52huq -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 f0 f7 ff ff[ ]*vpmadd52huq -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b5 f4[ ]*vpmadd52huq %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b5 f4[ ]*vpmadd52huq %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b5 f4[ ]*vpmadd52huq %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 31[ ]*vpmadd52huq \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b5 b4 f0 23 01 00 00[ ]*vpmadd52huq 0x123\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 7f[ ]*vpmadd52huq 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 00 10 00 00[ ]*vpmadd52huq 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 80[ ]*vpmadd52huq -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 e0 ef ff ff[ ]*vpmadd52huq -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b4 f4[ ]*vpmadd52luq %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b4 f4[ ]*vpmadd52luq %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b4 f4[ ]*vpmadd52luq %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 31[ ]*vpmadd52luq \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b4 b4 f0 34 12 00 00[ ]*vpmadd52luq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 7f[ ]*vpmadd52luq 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 00 08 00 00[ ]*vpmadd52luq 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 72 80[ ]*vpmadd52luq -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b4 b2 f0 f7 ff ff[ ]*vpmadd52luq -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b4 f4[ ]*vpmadd52luq %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b4 f4[ ]*vpmadd52luq %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b4 f4[ ]*vpmadd52luq %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 31[ ]*vpmadd52luq \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b4 b4 f0 34 12 00 00[ ]*vpmadd52luq 0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 31[ ]*vpmadd52luq \(%rcx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 7f[ ]*vpmadd52luq 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 00 10 00 00[ ]*vpmadd52luq 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 72 80[ ]*vpmadd52luq -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b4 b2 e0 ef ff ff[ ]*vpmadd52luq -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 7f[ ]*vpmadd52luq 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 00 04 00 00[ ]*vpmadd52luq 0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 72 80[ ]*vpmadd52luq -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b4 b2 f8 fb ff ff[ ]*vpmadd52luq -0x408\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 00 b5 f4[ ]*vpmadd52huq %xmm28,%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 07 b5 f4[ ]*vpmadd52huq %xmm28,%xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 87 b5 f4[ ]*vpmadd52huq %xmm28,%xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 31[ ]*vpmadd52huq \(%rcx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 00 b5 b4 f0 34 12 00 00[ ]*vpmadd52huq 0x1234\(%rax,%r14,8\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 7f[ ]*vpmadd52huq 0x7f0\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 00 08 00 00[ ]*vpmadd52huq 0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 72 80[ ]*vpmadd52huq -0x800\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 00 b5 b2 f0 f7 ff ff[ ]*vpmadd52huq -0x810\(%rdx\),%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 10 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to2\},%xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 20 b5 f4[ ]*vpmadd52huq %ymm28,%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 27 b5 f4[ ]*vpmadd52huq %ymm28,%ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 02 95 a7 b5 f4[ ]*vpmadd52huq %ymm28,%ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 31[ ]*vpmadd52huq \(%rcx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 22 95 20 b5 b4 f0 34 12 00 00[ ]*vpmadd52huq 0x1234\(%rax,%r14,8\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 31[ ]*vpmadd52huq \(%rcx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 7f[ ]*vpmadd52huq 0xfe0\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 00 10 00 00[ ]*vpmadd52huq 0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 72 80[ ]*vpmadd52huq -0x1000\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 20 b5 b2 e0 ef ff ff[ ]*vpmadd52huq -0x1020\(%rdx\),%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 7f[ ]*vpmadd52huq 0x3f8\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 00 04 00 00[ ]*vpmadd52huq 0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 72 80[ ]*vpmadd52huq -0x400\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 62 95 30 b5 b2 f8 fb ff ff[ ]*vpmadd52huq -0x408\(%rdx\)\{1to4\},%ymm29,%ymm30
|
||||
#pass
|
||||
119
gas/testsuite/gas/i386/x86-64-avx512ifma_vl.s
Normal file
119
gas/testsuite/gas/i386/x86-64-avx512ifma_vl.s
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
# Check 64bit AVX512{IFMA,VL} instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpmadd52luq %xmm28, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq %xmm28, %xmm29, %xmm30{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%rcx), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%rcx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq 2032(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq -2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -2064(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq %ymm28, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq %ymm28, %ymm29, %ymm30{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52luq %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%rcx), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq (%rcx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq 4064(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq -4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -4128(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52luq -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq %xmm28, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq %xmm28, %xmm29, %xmm30{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq %xmm28, %xmm29, %xmm30{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%rcx), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq 0x123(%rax,%r14,8), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%rcx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq 2032(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq -2048(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -2064(%rdx), %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq 1016(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq -1024(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -1032(%rdx){1to2}, %xmm29, %xmm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq %ymm28, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq %ymm28, %ymm29, %ymm30{%k7} # AVX512{IFMA,VL}
|
||||
vpmadd52huq %ymm28, %ymm29, %ymm30{%k7}{z} # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%rcx), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq 0x123(%rax,%r14,8), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq (%rcx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq 4064(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq -4096(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -4128(%rdx), %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq 1016(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq 1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
vpmadd52huq -1024(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq -1032(%rdx){1to4}, %ymm29, %ymm30 # AVX512{IFMA,VL}
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpmadd52luq xmm30, xmm29, xmm28 # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30{k7}, xmm29, xmm28 # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30{k7}{z}, xmm29, xmm28 # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30, xmm29, [rcx]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30, xmm29, [rdx+1016]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm30, xmm29, [rdx+1024]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52luq xmm30, xmm29, [rdx-1024]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq xmm30, xmm29, [rdx-1032]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, ymm28 # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30{k7}, ymm29, ymm28 # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30{k7}{z}, ymm29, ymm28 # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, [rcx]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, [rdx+1016]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm30, ymm29, [rdx+1024]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52luq ymm30, ymm29, [rdx-1024]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52luq ymm30, ymm29, [rdx-1032]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, xmm28 # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30{k7}, xmm29, xmm28 # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30{k7}{z}, xmm29, xmm28 # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, XMMWORD PTR [rcx] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, XMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, [rcx]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx+2032] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx+2048] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx-2048] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm30, xmm29, XMMWORD PTR [rdx-2064] # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, [rdx+1016]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm30, xmm29, [rdx+1024]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52huq xmm30, xmm29, [rdx-1024]{1to2} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq xmm30, xmm29, [rdx-1032]{1to2} # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, ymm28 # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30{k7}, ymm29, ymm28 # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30{k7}{z}, ymm29, ymm28 # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, YMMWORD PTR [rcx] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, YMMWORD PTR [rax+r14*8+0x1234] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, [rcx]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx+4064] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx+4096] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx-4096] # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm30, ymm29, YMMWORD PTR [rdx-4128] # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, [rdx+1016]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm30, ymm29, [rdx+1024]{1to4} # AVX512{IFMA,VL}
|
||||
vpmadd52huq ymm30, ymm29, [rdx-1024]{1to4} # AVX512{IFMA,VL} Disp8
|
||||
vpmadd52huq ymm30, ymm29, [rdx-1032]{1to4} # AVX512{IFMA,VL}
|
||||
|
|
@ -1,3 +1,16 @@
|
|||
2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
|
||||
|
||||
* i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
|
||||
* i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
|
||||
PREFIX_EVEX_0F38B5.
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
|
||||
(cpu_flags): Add CpuAVX512IFMA.
|
||||
* i386-opc.h (enum): Add CpuAVX512IFMA.
|
||||
(i386_cpu_flags): Add cpuavx512ifma.
|
||||
* i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-tbl.h: Likewise.
|
||||
|
||||
2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
|
||||
|
||||
* i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
|
||||
|
|
|
|||
|
|
@ -497,8 +497,8 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F38B4) },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F38B5) },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F38B6) },
|
||||
{ PREFIX_TABLE (PREFIX_EVEX_0F38B7) },
|
||||
/* B8 */
|
||||
|
|
@ -2311,6 +2311,18 @@ static const struct dis386 evex_table[][256] = {
|
|||
{ Bad_Opcode },
|
||||
{ "vfnmsub213s%XW", { XMScalar, VexScalar, EXxmm_mdq, EXxEVexR } },
|
||||
},
|
||||
/* PREFIX_EVEX_0F38B4 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "vpmadd52luq", { XM, Vex, EXx } },
|
||||
},
|
||||
/* PREFIX_EVEX_0F38B5 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ "vpmadd52huq", { XM, Vex, EXx } },
|
||||
},
|
||||
/* PREFIX_EVEX_0F38B6 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
|
|
|
|||
|
|
@ -1511,6 +1511,8 @@ enum
|
|||
PREFIX_EVEX_0F38AD,
|
||||
PREFIX_EVEX_0F38AE,
|
||||
PREFIX_EVEX_0F38AF,
|
||||
PREFIX_EVEX_0F38B4,
|
||||
PREFIX_EVEX_0F38B5,
|
||||
PREFIX_EVEX_0F38B6,
|
||||
PREFIX_EVEX_0F38B7,
|
||||
PREFIX_EVEX_0F38B8,
|
||||
|
|
|
|||
|
|
@ -241,6 +241,8 @@ static initializer cpu_flag_init[] =
|
|||
"CpuCLWB" },
|
||||
{ "CPU_PCOMMIT_FLAGS",
|
||||
"CpuPCOMMIT" },
|
||||
{ "CPU_AVX512IFMA_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512IFMA" },
|
||||
};
|
||||
|
||||
static initializer operand_type_init[] =
|
||||
|
|
@ -442,6 +444,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (Cpu64),
|
||||
BITFIELD (CpuNo64),
|
||||
BITFIELD (CpuMPX),
|
||||
BITFIELD (CpuAVX512IFMA),
|
||||
#ifdef CpuUnused
|
||||
BITFIELD (CpuUnused),
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -22,701 +22,708 @@
|
|||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, \
|
||||
1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PENTIUMPRO_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BDVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BDVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BDVER3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BDVER4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BTVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BTVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_NOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XSAVEOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BMI_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_TBM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CX16_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_FSGSBASE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RDRND_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_F16C_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_BMI2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_LZCNT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_HLE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RTM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_INVPCID_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_VMFUNC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512F_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512CD_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512ER_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512PF_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, \
|
||||
1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
#define CPU_K1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, \
|
||||
1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, \
|
||||
1, 1 } }
|
||||
|
||||
#define CPU_ADX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_RDSEED_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PRFCHW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SMAP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_MPX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SHA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSHOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XSAVES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_XSAVEC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PREFETCHWT1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_SE1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512DQ_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512BW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512VL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_CLWB_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_PCOMMIT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0 } }
|
||||
0, 0 } }
|
||||
|
||||
#define CPU_AVX512IFMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -188,6 +188,8 @@ enum
|
|||
CpuCLWB,
|
||||
/* PCOMMIT instruction required */
|
||||
CpuPCOMMIT,
|
||||
/* Intel AVX-512 IFMA Instructions support required. */
|
||||
CpuAVX512IFMA,
|
||||
/* 64bit support required */
|
||||
Cpu64,
|
||||
/* Not supported in the 64bit mode */
|
||||
|
|
@ -289,6 +291,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuse1:1;
|
||||
unsigned int cpuclwb:1;
|
||||
unsigned int cpupcommit:1;
|
||||
unsigned int cpuavx512ifma:1;
|
||||
unsigned int cpu64:1;
|
||||
unsigned int cpuno64:1;
|
||||
#ifdef CpuUnused
|
||||
|
|
|
|||
|
|
@ -5894,3 +5894,14 @@ clwb, 1, 0x660fae, 0x6, 2, CpuCLWB, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_
|
|||
pcommit, 0, 0x660fae, 0xf8, 2, CpuPCOMMIT, IgnoreSize|ImmExt|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
// PCOMMIT instructions end.
|
||||
|
||||
// AVX512IFMA instructions
|
||||
|
||||
vpmadd52huq, 3, 0x66B5, None, 1, CpuAVX512IFMA, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmadd52huq, 3, 0x66B5, None, 1, CpuAVX512IFMA|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmadd52huq, 3, 0x66B5, None, 1, CpuAVX512IFMA|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmadd52luq, 3, 0x66B4, None, 1, CpuAVX512IFMA, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Qword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
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vpmadd52luq, 3, 0x66B4, None, 1, CpuAVX512IFMA|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=4|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
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vpmadd52luq, 3, 0x66B4, None, 1, CpuAVX512IFMA|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
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||||
|
||||
// AVX512IFMA instructions end
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||||
|
|
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10928
opcodes/i386-tbl.h
10928
opcodes/i386-tbl.h
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