MIPS: Add Octeon 3 support
binutils: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * readelf.c (print_mips_isa_ext): Print the value of Octeon3. gas: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * config/tc-mips.c (CPU_IS_OCTEON): Handle CPU_OCTEON3. (mips_cpu_info_table): Octeon3 enables virt ase. * doc/c-mips.texi: Document octeon3 as an acceptable value for -march=. gas/testsuite: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * gas/mips/mips.exp: Add support for Octeon3 architecture. Also add in support for running Octeon3 tests. * gas/mips/octeon3.d: New test. * gas/mips/octeon3.s: New test source. opcodes: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * mips-dis.c (mips_arch_choices): Add octeon3. * mips-opc.c (IOCT): Include INSN_OCTEON3. (IOCT2): Likewise. (IOCT3): New define. (IVIRT): New define. (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti IVIRT instructions. Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another operand for IOCT3. bfd: 2014-10-31 Andrew Pinski <apinski@cavium.com> Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> * archures.c: Add octeon3 for mips target. * bfd-in2.h: Regenerate. * bfd/cpu-mips.c: Define I_mipsocteon3. nfo_struct): Add octeon3 support. * bfd/elfxx-mips.c: (_bfd_elf_mips_mach): Add support for octeon3. (mips_set_isa_flags): Add support for octeon3. (bfd_mips_isa_ext): Add bfd_mach_mips_octeon3. (mips_mach_extensions): Make bfd_mach_mips_octeon3 an extension of bfd_mach_mips_octeon2. (print_mips_isa_ext): Print the value of Octeon3.
This commit is contained in:
parent
2220166513
commit
2c62985659
20 changed files with 146 additions and 4 deletions
|
@ -1196,6 +1196,7 @@ static const unsigned int mips_isa_table[] = {
|
|||
#define INSN_OCTEON 0x00000800
|
||||
#define INSN_OCTEONP 0x00000200
|
||||
#define INSN_OCTEON2 0x00000100
|
||||
#define INSN_OCTEON3 0x00000040
|
||||
|
||||
/* MIPS R5900 instruction */
|
||||
#define INSN_5900 0x00004000
|
||||
|
@ -1323,6 +1324,7 @@ static const unsigned int mips_isa_table[] = {
|
|||
#define CPU_OCTEON 6501
|
||||
#define CPU_OCTEONP 6601
|
||||
#define CPU_OCTEON2 6502
|
||||
#define CPU_OCTEON3 6503
|
||||
#define CPU_XLR 887682 /* decimal 'XLR' */
|
||||
|
||||
/* Return true if the given CPU is included in INSN_* mask MASK. */
|
||||
|
@ -1388,6 +1390,9 @@ cpu_is_member (int cpu, unsigned int mask)
|
|||
case CPU_OCTEON2:
|
||||
return (mask & INSN_OCTEON2) != 0;
|
||||
|
||||
case CPU_OCTEON3:
|
||||
return (mask & INSN_OCTEON3) != 0;
|
||||
|
||||
case CPU_XLR:
|
||||
return (mask & INSN_XLR) != 0;
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue