Commit gdb and sim support for v850e2 and v850e2v3 on behalf of
Rathish C <Rathish.C@kpitcummins.com>.
This commit is contained in:
Kevin Buettner
parent
1c1b6f059a
commit
2aaed97917
11 changed files with 3380 additions and 29 deletions
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@ -15,6 +15,7 @@
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#include "sim-basics.h"
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#include "sim-signal.h"
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#include "sim-fpu.h"
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typedef address_word sim_cia;
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@ -39,7 +40,10 @@ typedef struct _v850_regs {
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reg_t regs[32]; /* general-purpose registers */
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reg_t sregs[32]; /* system registers, including psw */
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reg_t pc;
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int dummy_mem; /* where invalid accesses go */
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int dummy_mem; /* where invalid accesses go */
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reg_t mpu0_sregs[28]; /* mpu0 system registers */
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reg_t mpu1_sregs[28]; /* mpu1 system registers */
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reg_t fpu_sregs[28]; /* fpu system registers */
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} v850_regs;
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struct _sim_cpu
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@ -122,11 +126,15 @@ nia = PC
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/* new */
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#define GR ((CPU)->reg.regs)
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#define SR ((CPU)->reg.sregs)
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#define MPU0_SR ((STATE_CPU (sd, 0))->reg.mpu0_sregs)
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#define MPU1_SR ((STATE_CPU (sd, 0))->reg.mpu1_sregs)
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#define FPU_SR ((STATE_CPU (sd, 0))->reg.fpu_sregs)
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/* old */
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#define State (STATE_CPU (simulator, 0)->reg)
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#define PC (State.pc)
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#define SP (State.regs[3])
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#define SP_REGNO 3
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#define SP (State.regs[SP_REGNO])
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#define EP (State.regs[30])
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#define EIPC (State.sregs[0])
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@ -135,11 +143,20 @@ nia = PC
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#define FEPSW (State.sregs[3])
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#define ECR (State.sregs[4])
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#define PSW (State.sregs[5])
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#define PSW_REGNO 5
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#define EIIC (State.sregs[13])
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#define FEIC (State.sregs[14])
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#define DBIC (SR[15])
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#define CTPC (SR[16])
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#define CTPSW (SR[17])
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#define DBPC (State.sregs[18])
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#define DBPSW (State.sregs[19])
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#define CTBP (State.sregs[20])
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#define DIR (SR[21])
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#define EIWR (SR[28])
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#define FEWR (SR[29])
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#define DBWR (SR[30])
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#define BSEL (SR[31])
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#define PSW_US BIT32 (8)
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#define PSW_NP 0x80
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@ -151,6 +168,210 @@ nia = PC
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#define PSW_S 0x2
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#define PSW_Z 0x1
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#define PSW_NPV (1<<18)
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#define PSW_DMP (1<<17)
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#define PSW_IMP (1<<16)
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#define ECR_EICC 0x0000ffff
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#define ECR_FECC 0xffff0000
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/* FPU */
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#define FPSR (FPU_SR[6])
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#define FPSR_REGNO 6
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#define FPEPC (FPU_SR[7])
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#define FPST (FPU_SR[8])
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#define FPST_REGNO 8
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#define FPCC (FPU_SR[9])
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#define FPCFG (FPU_SR[10])
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#define FPCFG_REGNO 10
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#define FPSR_DEM 0x00200000
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#define FPSR_SEM 0x00100000
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#define FPSR_RM 0x000c0000
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#define FPSR_RN 0x00000000
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#define FPSR_FS 0x00020000
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#define FPSR_PR 0x00010000
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#define FPSR_XC 0x0000fc00
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#define FPSR_XCE 0x00008000
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#define FPSR_XCV 0x00004000
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#define FPSR_XCZ 0x00002000
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#define FPSR_XCO 0x00001000
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#define FPSR_XCU 0x00000800
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#define FPSR_XCI 0x00000400
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#define FPSR_XE 0x000003e0
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#define FPSR_XEV 0x00000200
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#define FPSR_XEZ 0x00000100
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#define FPSR_XEO 0x00000080
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#define FPSR_XEU 0x00000040
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#define FPSR_XEI 0x00000020
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#define FPSR_XP 0x0000001f
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#define FPSR_XPV 0x00000010
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#define FPSR_XPZ 0x00000008
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#define FPSR_XPO 0x00000004
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#define FPSR_XPU 0x00000002
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#define FPSR_XPI 0x00000001
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#define FPST_PR 0x00008000
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#define FPST_XCE 0x00002000
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#define FPST_XCV 0x00001000
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#define FPST_XCZ 0x00000800
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#define FPST_XCO 0x00000400
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#define FPST_XCU 0x00000200
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#define FPST_XCI 0x00000100
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#define FPST_XPV 0x00000010
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#define FPST_XPZ 0x00000008
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#define FPST_XPO 0x00000004
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#define FPST_XPU 0x00000002
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#define FPST_XPI 0x00000001
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#define FPCFG_RM 0x00000180
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#define FPCFG_XEV 0x00000010
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#define FPCFG_XEZ 0x00000008
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#define FPCFG_XEO 0x00000004
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#define FPCFG_XEU 0x00000002
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#define FPCFG_XEI 0x00000001
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#define GET_FPCC()\
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((FPSR >> 24) &0xf)
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#define CLEAR_FPCC(bbb)\
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(FPSR &= ~(1 << (bbb+24)))
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#define SET_FPCC(bbb)\
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(FPSR |= 1 << (bbb+24))
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#define TEST_FPCC(bbb)\
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((FPSR & (1 << (bbb+24))) != 0)
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#define FPSR_GET_ROUND() \
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(((FPSR & FPSR_RM) == FPSR_RN) ? sim_fpu_round_near \
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: ((FPSR & FPSR_RM) == 0x00040000) ? sim_fpu_round_up \
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: ((FPSR & FPSR_RM) == 0x00080000) ? sim_fpu_round_down \
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: sim_fpu_round_zero)
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enum FPU_COMPARE {
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FPU_CMP_F = 0,
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FPU_CMP_UN,
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FPU_CMP_EQ,
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FPU_CMP_UEQ,
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FPU_CMP_OLT,
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FPU_CMP_ULT,
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FPU_CMP_OLE,
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FPU_CMP_ULE,
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FPU_CMP_SF,
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FPU_CMP_NGLE,
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FPU_CMP_SEQ,
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FPU_CMP_NGL,
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FPU_CMP_LT,
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FPU_CMP_NGE,
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FPU_CMP_LE,
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FPU_CMP_NGT
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};
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/* MPU */
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#define MPM (MPU1_SR[0])
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#define MPC (MPU1_SR[1])
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#define MPC_REGNO 1
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#define TID (MPU1_SR[2])
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#define PPA (MPU1_SR[3])
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#define PPM (MPU1_SR[4])
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#define PPC (MPU1_SR[5])
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#define DCC (MPU1_SR[6])
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#define DCV0 (MPU1_SR[7])
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#define DCV1 (MPU1_SR[8])
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#define SPAL (MPU1_SR[10])
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#define SPAU (MPU1_SR[11])
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#define IPA0L (MPU1_SR[12])
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#define IPA0U (MPU1_SR[13])
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#define IPA1L (MPU1_SR[14])
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#define IPA1U (MPU1_SR[15])
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#define IPA2L (MPU1_SR[16])
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#define IPA2U (MPU1_SR[17])
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#define IPA3L (MPU1_SR[18])
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#define IPA3U (MPU1_SR[19])
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#define DPA0L (MPU1_SR[20])
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#define DPA0U (MPU1_SR[21])
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#define DPA1L (MPU1_SR[22])
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#define DPA1U (MPU1_SR[23])
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#define DPA2L (MPU1_SR[24])
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#define DPA2U (MPU1_SR[25])
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#define DPA3L (MPU1_SR[26])
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#define DPA3U (MPU1_SR[27])
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#define PPC_PPE 0x1
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#define SPAL_SPE 0x1
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#define SPAL_SPS 0x10
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#define VIP (MPU0_SR[0])
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#define VMECR (MPU0_SR[4])
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#define VMTID (MPU0_SR[5])
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#define VMADR (MPU0_SR[6])
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#define VPECR (MPU0_SR[8])
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#define VPTID (MPU0_SR[9])
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#define VPADR (MPU0_SR[10])
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#define VDECR (MPU0_SR[12])
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#define VDTID (MPU0_SR[13])
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#define MPM_AUE 0x2
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#define MPM_MPE 0x1
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#define VMECR_VMX 0x2
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#define VMECR_VMR 0x4
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#define VMECR_VMW 0x8
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#define VMECR_VMS 0x10
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#define VMECR_VMRMW 0x20
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#define VMECR_VMMS 0x40
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#define IPA2ADDR(IPA) ((IPA) & 0x1fffff80)
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#define IPA_IPE 0x1
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#define IPA_IPX 0x2
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#define IPA_IPR 0x4
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#define IPE0 (IPA0L & IPA_IPE)
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#define IPE1 (IPA1L & IPA_IPE)
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#define IPE2 (IPA2L & IPA_IPE)
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#define IPE3 (IPA3L & IPA_IPE)
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#define IPX0 (IPA0L & IPA_IPX)
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#define IPX1 (IPA1L & IPA_IPX)
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#define IPX2 (IPA2L & IPA_IPX)
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#define IPX3 (IPA3L & IPA_IPX)
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#define IPR0 (IPA0L & IPA_IPR)
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#define IPR1 (IPA1L & IPA_IPR)
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#define IPR2 (IPA2L & IPA_IPR)
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#define IPR3 (IPA3L & IPA_IPR)
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#define DPA2ADDR(DPA) ((DPA) & 0x1fffff80)
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#define DPA_DPE 0x1
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#define DPA_DPR 0x4
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#define DPA_DPW 0x8
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#define DPE0 (DPA0L & DPA_DPE)
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#define DPE1 (DPA1L & DPA_DPE)
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#define DPE2 (DPA2L & DPA_DPE)
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#define DPE3 (DPA3L & DPA_DPE)
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#define DPR0 (DPA0L & DPA_DPR)
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#define DPR1 (DPA1L & DPA_DPR)
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#define DPR2 (DPA2L & DPA_DPR)
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#define DPR3 (DPA3L & DPA_DPR)
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#define DPW0 (DPA0L & DPA_DPW)
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#define DPW1 (DPA1L & DPA_DPW)
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#define DPW2 (DPA2L & DPA_DPW)
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#define DPW3 (DPA3L & DPA_DPW)
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#define DCC_DCE0 0x1
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#define DCC_DCE1 0x10000
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#define PPA2ADDR(PPA) ((PPA) & 0x1fffff80)
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#define PPC_PPC 0xfffffffe
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#define PPC_PPE 0x1
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#define PPC_PPM 0x0000fff8
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#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
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/* sign-extend a 4-bit number */
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@ -344,6 +565,79 @@ do { \
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} \
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} while (0)
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#define TRACE_FP_INPUT_FPU1(V0) \
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do { \
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if (TRACE_FPU_P (CPU)) \
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{ \
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unsigned64 f0; \
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sim_fpu_to64 (&f0, (V0)); \
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trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
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} \
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} while (0)
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#define TRACE_FP_INPUT_FPU2(V0, V1) \
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do { \
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if (TRACE_FPU_P (CPU)) \
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{ \
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unsigned64 f0, f1; \
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sim_fpu_to64 (&f0, (V0)); \
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sim_fpu_to64 (&f1, (V1)); \
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trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1); \
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} \
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} while (0)
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#define TRACE_FP_INPUT_FPU3(V0, V1, V2) \
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do { \
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if (TRACE_FPU_P (CPU)) \
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{ \
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unsigned64 f0, f1, f2; \
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sim_fpu_to64 (&f0, (V0)); \
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sim_fpu_to64 (&f1, (V1)); \
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sim_fpu_to64 (&f2, (V2)); \
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trace_input_fp3 (SD, CPU, TRACE_FPU_IDX, f0, f1, f2); \
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} \
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} while (0)
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#define TRACE_FP_INPUT_BOOL1_FPU2(V0, V1, V2) \
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do { \
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if (TRACE_FPU_P (CPU)) \
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{ \
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int d0 = (V0); \
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unsigned64 f1, f2; \
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TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
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TRACE_IDX (data) = TRACE_FPU_IDX; \
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sim_fpu_to64 (&f1, (V1)); \
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sim_fpu_to64 (&f2, (V2)); \
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save_data (SD, data, trace_fmt_bool, sizeof (d0), &d0); \
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save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f1); \
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save_data (SD, data, trace_fmt_fp, sizeof (fp_word), &f2); \
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} \
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} while (0)
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#define TRACE_FP_INPUT_WORD2(V0, V1) \
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do { \
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if (TRACE_FPU_P (CPU)) \
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trace_input_word2 (SD, CPU, TRACE_FPU_IDX, (V0), (V1)); \
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} while (0)
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#define TRACE_FP_RESULT_FPU1(R0) \
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do { \
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if (TRACE_FPU_P (CPU)) \
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{ \
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unsigned64 f0; \
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sim_fpu_to64 (&f0, (R0)); \
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trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
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} \
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} while (0)
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#define TRACE_FP_RESULT_WORD1(R0) TRACE_FP_RESULT_WORD(R0)
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#define TRACE_FP_RESULT_WORD2(R0, R1) \
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do { \
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if (TRACE_FPU_P (CPU)) \
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trace_result_word2 (SD, CPU, TRACE_FPU_IDX, (R0), (R1)); \
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} while (0)
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#else
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#define trace_input(NAME, IN1, IN2)
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#define trace_output(RESULT)
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