x86/APX: optimize certain {nf}-form insns to LEA
..., as that leaves EFLAGS untouched anyway. That's a shorter encoding,
available as long as certain constraints on operand size and registers
are met; see code comments.
Note that this requires deferring to derive encoding_evex from {nf}
presence, as in optimize_encoding() we want to avoid touching the insns
when {evex} was also used.
Note further that this requires want_disp32() to now also consider the
opcode: We don't want to replace i.tm.mnem_off, for diagnostics to still
report the original mnemonic (or else things can get confusing). While
there, correct adjacent mis-indentation.
This commit is contained in:
Jan Beulich
parent
c7eae03eab
commit
27ef4876f7
7 changed files with 1819 additions and 15 deletions
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@ -1929,6 +1929,7 @@ static INLINE bool need_evex_encoding (const insn_template *t)
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{
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return i.encoding == encoding_evex
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|| i.encoding == encoding_evex512
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|| i.has_nf
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|| (t->opcode_modifier.vex && i.encoding == encoding_egpr)
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|| i.mask.reg;
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}
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@ -3804,9 +3805,10 @@ want_disp32 (const insn_template *t)
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{
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return flag_code != CODE_64BIT
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|| i.prefix[ADDR_PREFIX]
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|| (t->mnem_off == MN_lea
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|| ((t->mnem_off == MN_lea
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|| (i.tm.base_opcode == 0x8d && i.tm.opcode_space == SPACE_BASE))
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&& (!i.types[1].bitfield.qword
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|| t->opcode_modifier.size == SIZE32));
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|| t->opcode_modifier.size == SIZE32));
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}
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static int
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@ -5327,6 +5329,30 @@ optimize_encoding (void)
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}
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}
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/* Check whether the promoted (to address size) register is usable as index
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register in ModR/M SIB addressing. */
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static bool is_index (const reg_entry *r)
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{
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gas_assert (flag_code == CODE_64BIT);
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if (r->reg_type.bitfield.byte)
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{
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if (!(r->reg_flags & RegRex64))
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{
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if (r->reg_num >= 4)
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return false;
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r += 8;
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}
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r += 32;
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}
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if (r->reg_type.bitfield.word)
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r += 32;
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/* No need to further check .dword here. */
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return r->reg_type.bitfield.baseindex;
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}
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/* Try to shorten {nf} encodings, by shortening operand size or switching to
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functionally identical encodings. */
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@ -5423,6 +5449,203 @@ optimize_nf_encoding (void)
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i.tm.operand_types[0].bitfield.imm1 = 1;
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i.imm_operands = 0;
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}
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if (optimize_for_space
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&& i.encoding != encoding_evex
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&& (i.tm.base_opcode == 0x00
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|| (i.tm.base_opcode == 0xd0 && i.tm.extension_opcode == 4))
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&& !i.mem_operands
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&& !i.types[1].bitfield.byte
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/* 16-bit operand size has extra restrictions: If REX2 was needed,
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no size reduction would be possible. Plus 3-operand forms zero-
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extend the result, which can't be expressed with LEA. */
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&& (!i.types[1].bitfield.word
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|| (i.operands == 2 && i.encoding != encoding_egpr))
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&& is_plausible_suffix (1)
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/* %rsp can't be the index. */
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&& (is_index (i.op[1].regs)
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|| (i.imm_operands == 0 && is_index (i.op[0].regs)))
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/* While %rbp, %r13, %r21, and %r29 can be made the index in order to
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avoid the otherwise necessary Disp8, if the other operand is also
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from that set and REX2 would be required to encode the insn, the
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resulting encoding would be no smaller than the EVEX one. */
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&& (i.op[1].regs->reg_num != 5
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|| i.encoding != encoding_egpr
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|| i.imm_operands > 0
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|| i.op[0].regs->reg_num != 5))
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{
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/* Optimize: -Os:
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{nf} addw %N, %M -> leaw (%rM,%rN), %M
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{nf} addl %eN, %eM -> leal (%rM,%rN), %eM
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{nf} addq %rN, %rM -> leaq (%rM,%rN), %rM
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{nf} shlw $1, %N -> leaw (%rN,%rN), %N
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{nf} shll $1, %eN -> leal (%rN,%rN), %eN
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{nf} shlq $1, %rN -> leaq (%rN,%rN), %rN
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{nf} addl %eK, %eN, %eM -> leal (%rN,%rK), %eM
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{nf} addq %rK, %rN, %rM -> leaq (%rN,%rK), %rM
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{nf} shll $1, %eN, %eM -> leal (%rN,%rN), %eM
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{nf} shlq $1, %rN, %rM -> leaq (%rN,%rN), %rM
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*/
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i.tm.opcode_space = SPACE_BASE;
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i.tm.base_opcode = 0x8d;
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i.tm.extension_opcode = None;
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i.tm.opcode_modifier.evex = 0;
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i.tm.opcode_modifier.vexvvvv = 0;
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if (i.imm_operands != 0)
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i.index_reg = i.base_reg = i.op[1].regs;
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else if (!is_index (i.op[0].regs)
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|| (i.op[1].regs->reg_num == 5
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&& i.op[0].regs->reg_num != 5))
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{
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i.base_reg = i.op[0].regs;
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i.index_reg = i.op[1].regs;
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}
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else
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{
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i.base_reg = i.op[1].regs;
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i.index_reg = i.op[0].regs;
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}
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if (i.types[1].bitfield.word)
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{
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/* NB: No similar adjustment is needed when operand size is 32-bit. */
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i.base_reg += 64;
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i.index_reg += 64;
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}
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i.op[1].regs = i.op[i.operands - 1].regs;
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operand_type_set (&i.types[0], 0);
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i.types[0].bitfield.baseindex = 1;
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i.tm.operand_types[0] = i.types[0];
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i.op[0].disps = NULL;
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i.flags[0] = Operand_Mem;
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i.operands = 2;
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i.mem_operands = i.reg_operands = 1;
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i.imm_operands = 0;
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i.has_nf = false;
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}
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else if (optimize_for_space
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&& i.encoding != encoding_evex
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&& (i.tm.base_opcode == 0x80 || i.tm.base_opcode == 0x83)
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&& (i.tm.extension_opcode == 0
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|| (i.tm.extension_opcode == 5
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&& i.op[0].imms->X_op == O_constant
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/* Subtraction of -0x80 will end up smaller only if neither
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operand size nor REX/REX2 prefixes are needed. */
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&& (i.op[0].imms->X_add_number != -0x80
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|| (i.types[1].bitfield.dword
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&& !(i.op[1].regs->reg_flags & RegRex)
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&& !(i.op[i.operands - 1].regs->reg_flags & RegRex)
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&& i.encoding != encoding_egpr))))
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&& !i.mem_operands
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&& !i.types[1].bitfield.byte
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/* 16-bit operand size has extra restrictions: If REX2 was needed,
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no size reduction would be possible. Plus 3-operand forms zero-
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extend the result, which can't be expressed with LEA. */
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&& (!i.types[1].bitfield.word
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|| (i.operands == 2 && i.encoding != encoding_egpr))
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&& is_plausible_suffix (1))
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{
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/* Optimize: -Os:
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{nf} addw $N, %M -> leaw N(%rM), %M
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{nf} addl $N, %eM -> leal N(%rM), %eM
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{nf} addq $N, %rM -> leaq N(%rM), %rM
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{nf} subw $N, %M -> leaw -N(%rM), %M
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{nf} subl $N, %eM -> leal -N(%rM), %eM
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{nf} subq $N, %rM -> leaq -N(%rM), %rM
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{nf} addl $N, %eK, %eM -> leal N(%rK), %eM
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{nf} addq $N, %rK, %rM -> leaq N(%rK), %rM
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{nf} subl $N, %eK, %eM -> leal -N(%rK), %eM
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{nf} subq $N, %rK, %rM -> leaq -N(%rK), %rM
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*/
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i.tm.opcode_space = SPACE_BASE;
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i.tm.base_opcode = 0x8d;
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if (i.tm.extension_opcode == 5)
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i.op[0].imms->X_add_number = -i.op[0].imms->X_add_number;
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i.tm.extension_opcode = None;
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i.tm.opcode_modifier.evex = 0;
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i.tm.opcode_modifier.vexvvvv = 0;
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i.base_reg = i.op[1].regs;
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if (i.types[1].bitfield.word)
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{
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/* NB: No similar adjustment is needed when operand size is 32-bit. */
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i.base_reg += 64;
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}
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i.op[1].regs = i.op[i.operands - 1].regs;
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operand_type_set (&i.types[0], 0);
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i.types[0].bitfield.baseindex = 1;
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i.types[0].bitfield.disp32 = 1;
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i.op[0].disps = i.op[0].imms;
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i.flags[0] = Operand_Mem;
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optimize_disp (&i.tm);
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i.tm.operand_types[0] = i.types[0];
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i.operands = 2;
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i.disp_operands = i.mem_operands = i.reg_operands = 1;
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i.imm_operands = 0;
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i.has_nf = false;
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}
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else if (i.tm.base_opcode == 0x6b
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&& !i.mem_operands
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&& i.encoding != encoding_evex
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&& is_plausible_suffix (1)
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/* %rsp can't be the index. */
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&& is_index (i.op[1].regs)
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/* There's no reduction in size for 16-bit forms requiring Disp8 and
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REX2. */
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&& (!optimize_for_space
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|| !i.types[1].bitfield.word
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|| i.op[1].regs->reg_num != 5
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|| i.encoding != encoding_egpr)
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&& i.op[0].imms->X_op == O_constant
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&& (i.op[0].imms->X_add_number == 3
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|| i.op[0].imms->X_add_number == 5
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|| i.op[0].imms->X_add_number == 9))
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{
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/* Optimize: -O:
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For n one of 3, 5, or 9
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{nf} imulw $n, %N, %M -> leaw (%rN,%rN,n-1), %M
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{nf} imull $n, %eN, %eM -> leal (%rN,%rN,n-1), %eM
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{nf} imulq $n, %rN, %rM -> leaq (%rN,%rN,n-1), %rM
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{nf} imulw $n, %N -> leaw (%rN,%rN,s), %N
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{nf} imull $n, %eN -> leal (%rN,%rN,s), %eN
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{nf} imulq $n, %rN -> leaq (%rN,%rN,s), %rN
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*/
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i.tm.opcode_space = SPACE_BASE;
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i.tm.base_opcode = 0x8d;
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i.tm.extension_opcode = None;
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i.tm.opcode_modifier.evex = 0;
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i.base_reg = i.op[1].regs;
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/* NB: No similar adjustment is needed when operand size is 32 bits. */
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if (i.types[1].bitfield.word)
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i.base_reg += 64;
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i.index_reg = i.base_reg;
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i.log2_scale_factor = i.op[0].imms->X_add_number == 9
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? 3 : i.op[0].imms->X_add_number >> 1;
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operand_type_set (&i.types[0], 0);
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i.types[0].bitfield.baseindex = 1;
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i.tm.operand_types[0] = i.types[0];
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i.op[0].disps = NULL;
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i.flags[0] = Operand_Mem;
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i.tm.operand_types[1] = i.tm.operand_types[i.operands - 1];
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i.op[1].regs = i.op[i.operands - 1].regs;
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i.types[1] = i.types[i.operands - 1];
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i.operands = 2;
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i.mem_operands = i.reg_operands = 1;
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i.imm_operands = 0;
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i.has_nf = false;
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}
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}
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static void
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@ -7318,6 +7541,10 @@ md_assemble (char *line)
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i.encoding = is_any_vex_encoding (&i.tm) ? encoding_evex
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: encoding_default;
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/* Similarly {nf} can now be taken to imply {evex}. */
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if (i.has_nf && i.encoding == encoding_default)
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i.encoding = encoding_evex;
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if (use_unaligned_vector_move)
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encode_with_unaligned_vector_move ();
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@ -7631,8 +7858,6 @@ parse_insn (const char *line, char *mnemonic, bool prefix_only)
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case Prefix_NF:
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/* {nf} */
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i.has_nf = true;
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if (i.encoding == encoding_default)
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i.encoding = encoding_evex;
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break;
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case Prefix_NoOptimize:
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/* {nooptimize} */
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@ -7641,7 +7866,9 @@ parse_insn (const char *line, char *mnemonic, bool prefix_only)
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default:
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abort ();
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}
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if (i.has_nf && i.encoding != encoding_evex)
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if (i.has_nf
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&& i.encoding != encoding_default
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&& i.encoding != encoding_evex)
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{
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as_bad (_("{nf} cannot be combined with {vex}/{vex3}"));
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return NULL;
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@ -8784,9 +9011,6 @@ VEX_check_encoding (const insn_template *t)
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switch (i.encoding)
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{
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case encoding_default:
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break;
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case encoding_vex:
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case encoding_vex3:
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/* This instruction must be encoded with VEX prefix. */
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@ -8797,6 +9021,10 @@ VEX_check_encoding (const insn_template *t)
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}
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break;
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case encoding_default:
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if (!i.has_nf)
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break;
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/* Fall through. */
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case encoding_evex:
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case encoding_evex512:
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/* This instruction must be encoded with EVEX prefix. */
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1535
gas/testsuite/gas/i386/x86-64-apx-nf-optimize-size.d
Normal file
1535
gas/testsuite/gas/i386/x86-64-apx-nf-optimize-size.d
Normal file
File diff suppressed because it is too large
Load diff
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@ -1512,4 +1512,24 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%eax
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c d1 02[ ]+\{nf\} rolq \$1,\(%rdx\)
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 1c d1 02[ ]+\{nf\} rol \$1,\(%rdx\),%rax
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[ ]*[a-f0-9]+:[ ]*66 8d 14 49[ ]+lea \(%rcx,%rcx,2\),%dx
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[ ]*[a-f0-9]+:[ ]*66 8d 54 ad 00[ ]+lea 0x0\(%rbp,%rbp,4\),%dx
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[ ]*[a-f0-9]+:[ ]*66 8d 2c c9[ ]+lea \(%rcx,%rcx,8\),%bp
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c 6b d4 03[ ]+\{nf\} imul \$0x3,%sp,%dx
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 0c 6b e4 05[ ]+\{nf\} imul \$0x5,%sp,%sp
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c 6b d1 03[ ]+\{nf\} imulzu \$0x3,%cx,%dx
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[ ]*[a-f0-9]+:[ ]*62 f4 7d 1c 6b c9 05[ ]+\{nf\} imulzu \$0x5,%cx,%cx
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[ ]*[a-f0-9]+:[ ]*66 d5 40 8d 44 6d 00[ ]+lea 0x0\(%rbp,%rbp,2\),%r16w
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[ ]*[a-f0-9]+:[ ]*66 d5 30 8d 54 ad 00[ ]+lea 0x0\(%r21,%r21,4\),%dx
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[ ]*[a-f0-9]+:[ ]*66 d5 70 8d 6c ed 00[ ]+lea 0x0\(%r21,%r21,8\),%r21w
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[ ]*[a-f0-9]+:[ ]*8d 14 49[ ]+lea \(%rcx,%rcx,2\),%edx
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[ ]*[a-f0-9]+:[ ]*8d 54 ad 00[ ]+lea 0x0\(%rbp,%rbp,4\),%edx
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[ ]*[a-f0-9]+:[ ]*8d 2c c9[ ]+lea \(%rcx,%rcx,8\),%ebp
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c 6b d4 03[ ]+\{nf\} imul \$0x3,%esp,%edx
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[ ]*[a-f0-9]+:[ ]*62 f4 7c 0c 6b e4 05[ ]+\{nf\} imul \$0x5,%esp,%esp
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[ ]*[a-f0-9]+:[ ]*48 8d 14 49[ ]+lea \(%rcx,%rcx,2\),%rdx
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[ ]*[a-f0-9]+:[ ]*48 8d 54 ad 00[ ]+lea 0x0\(%rbp,%rbp,4\),%rdx
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[ ]*[a-f0-9]+:[ ]*48 8d 2c c9[ ]+lea \(%rcx,%rcx,8\),%rbp
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c 6b d4 03[ ]+\{nf\} imul \$0x3,%rsp,%rdx
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[ ]*[a-f0-9]+:[ ]*62 f4 fc 0c 6b e4 05[ ]+\{nf\} imul \$0x5,%rsp,%rsp
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#pass
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@ -1453,3 +1453,23 @@ optimize:
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{nf} ro\dir\()q $63, (%rdx)
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{nf} ro\dir $63, (%rdx), %rax
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.endr
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.irp r, "", e, r
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{nf} imul $3, %\r\(cx), %\r\(dx)
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{nf} imul $5, %\r\(bp), %\r\(dx)
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{nf} imul $9, %\r\(cx), %\r\(bp)
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# Note: %\r\(sp) source form needs leaving alone.
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{nf} imul $3, %\r\(sp), %\r\(dx)
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{nf} imul $5, %\r\(sp)
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.ifeqs "\r",""
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# Note: (16-bit) ZU form needs leaving alone.
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{nf} imulzu $3, %cx, %dx
|
||||
{nf} imulzu $5, %cx
|
||||
# Note: 16-bit forms requiring REX2 and Disp8 want leaving alone with -Os.
|
||||
{nf} imul $3, %bp, %r16w
|
||||
{nf} imul $5, %r21w, %dx
|
||||
{nf} imul $9, %r21w
|
||||
.endif
|
||||
.endr
|
||||
|
|
|
|||
|
|
@ -394,6 +394,7 @@ run_dump_test "x86-64-apx-jmpabs-inval"
|
|||
run_dump_test "x86-64-apx-nf"
|
||||
run_dump_test "x86-64-apx-nf-intel"
|
||||
run_dump_test "x86-64-apx-nf-optimize"
|
||||
run_dump_test "x86-64-apx-nf-optimize-size"
|
||||
run_dump_test "x86-64-apx-zu"
|
||||
run_dump_test "x86-64-apx-zu-intel"
|
||||
run_list_test "x86-64-apx-zu-inval"
|
||||
|
|
|
|||
|
|
@ -313,7 +313,7 @@ sti, 0xfb, 0, NoSuf, {}
|
|||
// Arithmetic.
|
||||
|
||||
<alu2:opc:c:optz:optt:opti:optiE:nf, +
|
||||
add:0:C::::Optimize:NF, +
|
||||
add:0:C:::::NF|Optimize, +
|
||||
or:1:C::Optimize:::NF, +
|
||||
adc:2:C:::::, +
|
||||
sbb:3::::::, +
|
||||
|
|
@ -418,7 +418,7 @@ imul, 0xaf, APX_F, C|Modrm|CheckOperandSize|No_bSuf|No_sSuf|DstVVVV|EVexMap4|NF,
|
|||
imul, 0xfaf, i386, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imul, 0xaf, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imul, 0x6b, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imul, 0x6b, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imul, 0x6b, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF|Optimize, { Imm8S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imulzu, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF|ZU, { Imm8S, Reg16|Unspecified|BaseIndex, Reg16 }
|
||||
imul, 0x69, i186, Modrm|CheckOperandSize|No_bSuf|No_sSuf, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
imul, 0x69, APX_F, Modrm|CheckOperandSize|No_bSuf|No_sSuf|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64|Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
|
||||
|
|
@ -427,7 +427,7 @@ imulzu, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|EVexMap4|NF|ZU, { Imm16, Reg16|Unspec
|
|||
// both i.rm.reg & i.rm.regmem fields. RegKludge enables this
|
||||
// transformation.
|
||||
imul, 0x6b, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm8S, Reg16|Reg32|Reg64 }
|
||||
imul, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm8S, Reg16|Reg32|Reg64 }
|
||||
imul, 0x6b, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF|Optimize, { Imm8S, Reg16|Reg32|Reg64 }
|
||||
imul, 0x69, i186, Modrm|No_bSuf|No_sSuf|RegKludge, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
|
||||
imul, 0x69, APX_F, Modrm|No_bSuf|No_sSuf|RegKludge|EVexMap4|NF, { Imm16|Imm32|Imm32S, Reg16|Reg32|Reg64 }
|
||||
// ZU is omitted here, for colliding with RegKludge. process_operands() will
|
||||
|
|
|
|||
|
|
@ -794,7 +794,7 @@ static const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_add, 0x00 <<3, 3, SPACE_EVEXMAP4, None,
|
||||
{ 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 3, 0, 0, 0, 0, 2, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
|
|
@ -816,7 +816,7 @@ static const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 1, 0 } } } },
|
||||
{ MN_add, 0x00 <<3, 2, SPACE_EVEXMAP4, None,
|
||||
{ 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
|
|
@ -3428,7 +3428,7 @@ static const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_imul, 0x6b, 3, SPACE_EVEXMAP4, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
|
|
@ -3474,7 +3474,7 @@ static const insn_template i386_optab[] =
|
|||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_imul, 0x6b, 2, SPACE_EVEXMAP4, None,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 2, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0,
|
||||
1, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue