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Add support for SIGILL (reserved-instruction-exception).

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This commit is contained in:
Andrew Cagney 2000-04-18 07:55:35 +00:00
parent 5ba474214c
commit 27842f65f2
5 changed files with 30 additions and 2 deletions
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5
sim/d10v/ChangeLog
View file

@ -1,3 +1,8 @@
Tue Apr 18 16:26:41 2000 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_resume): Deliver SIGILL.
(lookup_hash): Do not print SIGILL message.
Tue Feb 22 18:24:56 2000 Andrew Cagney <cagney@b1.cygnus.com> Tue Feb 22 18:24:56 2000 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in (SIM_EXTRA_CFLAGS): Define SIM_HAVE_ENVIRONMENT. * Makefile.in (SIM_EXTRA_CFLAGS): Define SIM_HAVE_ENVIRONMENT.

9
sim/d10v/interp.c
View file

@ -99,8 +99,6 @@ lookup_hash (ins, size)
{ {
if (h->next == NULL) if (h->next == NULL)
{ {
(*d10v_callback->printf_filtered)
(d10v_callback, "ERROR: Illegal instruction %x at PC %x\n", ins, PC);
State.exception = SIGILL; State.exception = SIGILL;
State.pc_changed = 1; /* Don't increment the PC. */ State.pc_changed = 1; /* Don't increment the PC. */
return NULL; return NULL;
@ -979,6 +977,13 @@ sim_resume (sd, step, siggnal)
JMP (AE_VECTOR_START); JMP (AE_VECTOR_START);
SLOT_FLUSH (); SLOT_FLUSH ();
break; break;
case SIGILL:
SET_BPC (PC);
SET_BPSW (PSW);
SET_HW_PSW ((PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT)));
JMP (RIE_VECTOR_START);
SLOT_FLUSH ();
break;
default: default:
/* just ignore it */ /* just ignore it */
break; break;

5
sim/testsuite/d10v-elf/ChangeLog
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@ -1,3 +1,8 @@
Tue Apr 18 16:32:07 2000 Andrew Cagney <cagney@b1.cygnus.com>
* t-rie-xx.s (test_rie_xx): New test.
* Makefile.in (TESTS): Update.
Tue Feb 22 17:36:34 2000 Andrew Cagney <cagney@b1.cygnus.com> Tue Feb 22 17:36:34 2000 Andrew Cagney <cagney@b1.cygnus.com>
* Makefile.in: Force d10v into operating mode. * Makefile.in: Force d10v into operating mode.

1
sim/testsuite/d10v-elf/Makefile.in
View file

@ -83,6 +83,7 @@ TESTS = \
t-ae-st2w-ip.ok \ t-ae-st2w-ip.ok \
t-ae-st2w-is.ok \ t-ae-st2w-is.ok \
t-mod-ld-pre.ok \ t-mod-ld-pre.ok \
t-rie-xx.ok \
# #
AS_FOR_TARGET = `\ AS_FOR_TARGET = `\

12
sim/testsuite/d10v-elf/t-rie-xx.s Normal file
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@ -0,0 +1,12 @@
.include "t-macros.i"
start
PSW_BITS = 0
point_dmap_at_imem
check_interrupt (VEC_RIE&DMAP_MASK)+DMAP_BASE PSW_BITS test_rie_xx
test_rie_xx:
.short 0xe120, 0x0000 ;; Example of RIE code
nop
exit47