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sim: mips: delete mmu stubs to move to common sim_{read,write}

Browse source 
The only unique thing about mip's sim_{read,write} helpers is the call to
address_translation on the incoming address.  When we look closer at that
function though, we see it's just a stub that maps physical to virtual,
and the cache/return values are hardcoded.  If we delete this function,
we can then collapse all the callers and drop the custom sim_{read,write}
logic entirely.

Some day we might want to add MMU support, but when we do, we'll want to
have the common layers handle things so all targets benefit.
This commit is contained in:
Mike Frysinger 2015-12-26 11:35:03 -05:00
parent 8b494522f9
commit 26f8bf63bf
6 changed files with 151 additions and 353 deletions
Download patch file Download diff file Expand all files Collapse all files

19
sim/mips/ChangeLog
View file

@ -1,3 +1,22 @@
2015-12-26 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_write, sim_read): Delete.
(store_word): Delete call to AddressTranslation and set paddr=vaddr.
(load_word): Likewise.
* micromips.igen (cache): Likewise.
* mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
do_store_left, do_store_right, do_load_double, do_store_double):
Likewise.
(do_pref): Delete call to AddressTranslation and stub out Prefetch.
(do_prefx): Likewise.
* sim-main.c (address_translation, prefetch): Delete.
(ifetch32, ifetch16): Delete call to AddressTranslation and set
paddr=vaddr.
* sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
address_translation, AddressTranslation, prefetch, Prefetch): Delete.
(LoadMemory, StoreMemory): Delete CCA arg.
2015-12-24 Mike Frysinger <vapier@gentoo.org> 2015-12-24 Mike Frysinger <vapier@gentoo.org>
* configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1. * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.

74
sim/mips/interp.c
View file

@ -840,59 +840,6 @@ mips_sim_close (SIM_DESC sd, int quitting)
#endif #endif
} }
int
sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
{
int index;
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes written, or zero if error. */
#ifdef DEBUG
sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif
/* We use raw read and write routines, since we do not want to count
the GDB memory accesses in our statistics gathering. */
for (index = 0; index < size; index++)
{
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
break;
if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
return(index);
}
int
sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
{
int index;
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* Return the number of bytes read, or zero if error. */
#ifdef DEBUG
sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif /* DEBUG */
for (index = 0; (index < size); index++)
{
address_word vaddr = (address_word)addr + index;
address_word paddr;
int cca;
if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
break;
if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
break;
}
return(index);
}
int int
sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length) sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
{ {
@ -1491,15 +1438,11 @@ store_word (SIM_DESC sd,
uword64 vaddr, uword64 vaddr,
signed_word val) signed_word val)
{ {
address_word paddr; address_word paddr = vaddr;
int uncached;
if ((vaddr & 3) != 0) if ((vaddr & 3) != 0)
SignalExceptionAddressStore (); SignalExceptionAddressStore ();
else else
{
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
isTARGET, isREAL))
{ {
const uword64 mask = 7; const uword64 mask = 7;
uword64 memval; uword64 memval;
@ -1508,10 +1451,9 @@ store_word (SIM_DESC sd,
paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)); paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
byte = (vaddr & mask) ^ (BigEndianCPU << 2); byte = (vaddr & mask) ^ (BigEndianCPU << 2);
memval = ((uword64) val) << (8 * byte); memval = ((uword64) val) << (8 * byte);
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
isREAL); isREAL);
} }
}
} }
/* Load a word from memory. */ /* Load a word from memory. */
@ -1528,12 +1470,7 @@ load_word (SIM_DESC sd,
} }
else else
{ {
address_word paddr; address_word paddr = vaddr;
int uncached;
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
isTARGET, isREAL))
{
const uword64 mask = 0x7; const uword64 mask = 0x7;
const unsigned int reverse = ReverseEndian ? 1 : 0; const unsigned int reverse = ReverseEndian ? 1 : 0;
const unsigned int bigend = BigEndianCPU ? 1 : 0; const unsigned int bigend = BigEndianCPU ? 1 : 0;
@ -1541,12 +1478,11 @@ load_word (SIM_DESC sd,
unsigned int byte; unsigned int byte;
paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2)); paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr, LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
isDATA, isREAL); isREAL);
byte = (vaddr & mask) ^ (bigend << 2); byte = (vaddr & mask) ^ (bigend << 2);
return EXTEND32 (memval >> (8 * byte)); return EXTEND32 (memval >> (8 * byte));
} }
}
return 0; return 0;
} }

5
sim/mips/micromips.igen
View file

@ -845,10 +845,7 @@
address_word base = GPR[BASE]; address_word base = GPR[BASE];
address_word offset = EXTEND12 (IMMEDIATE); address_word offset = EXTEND12 (IMMEDIATE);
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached;
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
isTARGET, isREAL))
CacheOp (OP, vaddr, paddr, instruction_0); CacheOp (OP, vaddr, paddr, instruction_0);
} }

159
sim/mips/mips.igen
View file

@ -782,17 +782,13 @@
address_word offset = EXTEND16 (insn_offset); address_word offset = EXTEND16 (insn_offset);
{ {
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached;
if ((vaddr & 3) != 0) if ((vaddr & 3) != 0)
{ {
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
sim_core_unaligned_signal); sim_core_unaligned_signal);
} }
else else
{
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
isTARGET, isREAL))
{ {
unsigned64 memval = 0; unsigned64 memval = 0;
unsigned64 memval1 = 0; unsigned64 memval1 = 0;
@ -802,14 +798,13 @@
unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
unsigned int byte; unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
LoadMemory (&memval, &memval1, uncached, AccessLength_WORD, paddr, LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
vaddr, isDATA, isREAL); isDATA, isREAL);
byte = ((vaddr & mask) ^ (bigend << shift)); byte = ((vaddr & mask) ^ (bigend << shift));
GPR[rt] = EXTEND32 (memval >> (8 * byte)); GPR[rt] = EXTEND32 (memval >> (8 * byte));
LLBIT = 1; LLBIT = 1;
} }
} }
}
} }
:function:::void:do_lld:int rt, int roffset, int rbase :function:::void:do_lld:int rt, int roffset, int rbase
@ -818,27 +813,23 @@
address_word offset = EXTEND16 (roffset); address_word offset = EXTEND16 (roffset);
{ {
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached;
if ((vaddr & 7) != 0) if ((vaddr & 7) != 0)
{ {
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
sim_core_unaligned_signal); sim_core_unaligned_signal);
} }
else else
{
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
isTARGET, isREAL))
{ {
unsigned64 memval = 0; unsigned64 memval = 0;
unsigned64 memval1 = 0; unsigned64 memval1 = 0;
LoadMemory (&memval, &memval1, uncached, AccessLength_DOUBLEWORD, LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
paddr, vaddr, isDATA, isREAL); isDATA, isREAL);
GPR[rt] = memval; GPR[rt] = memval;
LLBIT = 1; LLBIT = 1;
} }
} }
}
} }
:function:::void:do_lui:int rt, int immediate :function:::void:do_lui:int rt, int immediate
@ -1084,13 +1075,8 @@
address_word offset = EXTEND16 (insn_offset); address_word offset = EXTEND16 (insn_offset);
{ {
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached; /* Prefetch (paddr, vaddr, isDATA, hint); */
{
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
isTARGET, isREAL))
Prefetch (uncached, paddr, vaddr, isDATA, hint);
}
} }
} }
@ -1101,17 +1087,14 @@
address_word offset = EXTEND16 (offsetarg); address_word offset = EXTEND16 (offsetarg);
{ {
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached;
if ((vaddr & 3) != 0) if ((vaddr & 3) != 0)
{ {
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
sim_core_unaligned_signal); sim_core_unaligned_signal);
} }
else else
{
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
isTARGET, isREAL))
{ {
unsigned64 memval = 0; unsigned64 memval = 0;
unsigned64 memval1 = 0; unsigned64 memval1 = 0;
@ -1125,14 +1108,11 @@
byte = ((vaddr & mask) ^ bigendiancpu); byte = ((vaddr & mask) ^ bigendiancpu);
memval = ((unsigned64) GPR[rt] << (8 * byte)); memval = ((unsigned64) GPR[rt] << (8 * byte));
if (LLBIT) if (LLBIT)
{ StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
StoreMemory (uncached, AccessLength_WORD, memval, memval1, isREAL);
paddr, vaddr, isREAL);
}
GPR[rt] = LLBIT; GPR[rt] = LLBIT;
} }
} }
}
} }
:function:::void:do_scd:int rt, int roffset, int rbase :function:::void:do_scd:int rt, int roffset, int rbase
@ -1141,30 +1121,24 @@
address_word offset = EXTEND16 (roffset); address_word offset = EXTEND16 (roffset);
{ {
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached;
if ((vaddr & 7) != 0) if ((vaddr & 7) != 0)
{ {
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
sim_core_unaligned_signal); sim_core_unaligned_signal);
} }
else else
{
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
isTARGET, isREAL))
{ {
unsigned64 memval = 0; unsigned64 memval = 0;
unsigned64 memval1 = 0; unsigned64 memval1 = 0;
memval = GPR[rt]; memval = GPR[rt];
if (LLBIT) if (LLBIT)
{ StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
StoreMemory (uncached, AccessLength_DOUBLEWORD, memval, memval1, isREAL);
paddr, vaddr, isREAL);
}
GPR[rt] = LLBIT; GPR[rt] = LLBIT;
} }
} }
}
} }
:function:::void:do_sub:int rs, int rt, int rd :function:::void:do_sub:int rs, int rt, int rd
@ -1649,11 +1623,8 @@
address_word index = GPR[rindex]; address_word index = GPR[rindex];
{ {
address_word vaddr = loadstore_ea (SD_, base, index); address_word vaddr = loadstore_ea (SD_, base, index);
address_word paddr; address_word paddr = vaddr;
int uncached; /* Prefetch (paddr, vaddr, isDATA, hint); */
if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
isREAL))
Prefetch (uncached, paddr, vaddr, isDATA, hint);
} }
} }
@ -1716,32 +1687,27 @@
check_fpu (SD_); check_fpu (SD_);
{ {
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached;
if ((vaddr & 3) != 0) if ((vaddr & 3) != 0)
{ {
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
write_transfer, sim_core_unaligned_signal); write_transfer, sim_core_unaligned_signal);
} }
else else
{
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
isTARGET, isREAL))
{ {
uword64 memval = 0; uword64 memval = 0;
uword64 memval1 = 0; uword64 memval1 = 0;
uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
address_word reverseendian = address_word reverseendian =
(ReverseEndian ?(mask ^ AccessLength_WORD): 0); (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
address_word bigendiancpu = address_word bigendiancpu =
(BigEndianCPU ?(mask ^ AccessLength_WORD): 0); (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
unsigned int byte; unsigned int byte;
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu); byte = ((vaddr & mask) ^ bigendiancpu);
memval = (((uword64)COP_SW(1, ft)) << (8 * byte)); memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr, StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL);
vaddr, isREAL);
}
} }
} }
} }
@ -1754,17 +1720,14 @@
check_u64 (SD_, instruction_0); check_u64 (SD_, instruction_0);
{ {
address_word vaddr = loadstore_ea (SD_, base, index); address_word vaddr = loadstore_ea (SD_, base, index);
address_word paddr; address_word paddr = vaddr;
int uncached;
if ((vaddr & 3) != 0) if ((vaddr & 3) != 0)
{ {
SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
sim_core_unaligned_signal); sim_core_unaligned_signal);
} }
else else
{
if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
isTARGET, isREAL))
{ {
unsigned64 memval = 0; unsigned64 memval = 0;
unsigned64 memval1 = 0; unsigned64 memval1 = 0;
@ -1777,9 +1740,8 @@
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu); byte = ((vaddr & mask) ^ bigendiancpu);
memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte)); memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr, StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
vaddr, isREAL); isREAL);
}
} }
} }
} }
@ -3163,18 +3125,16 @@
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte; unsigned int byte;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
address_word vaddr; address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0) if ((vaddr & access) != 0)
{ {
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
} }
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL); LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu); byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte)); return (memval >> (8 * byte));
} }
@ -3187,7 +3147,6 @@
unsigned int byte; unsigned int byte;
unsigned int word; unsigned int word;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
address_word vaddr; address_word vaddr;
int nr_lhs_bits; int nr_lhs_bits;
@ -3195,8 +3154,7 @@
unsigned_word lhs_mask; unsigned_word lhs_mask;
unsigned_word temp; unsigned_word temp;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask)); paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0) if (BigEndianMem == 0)
paddr = paddr & ~access; paddr = paddr & ~access;
@ -3213,7 +3171,7 @@
(long) ((unsigned64) paddr >> 32), (long) paddr, (long) ((unsigned64) paddr >> 32), (long) paddr,
word, byte, nr_lhs_bits, nr_rhs_bits); */ word, byte, nr_lhs_bits, nr_rhs_bits); */
LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL); LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
if (word == 0) if (word == 0)
{ {
/* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
@ -3242,19 +3200,17 @@
address_word bigendiancpu = (BigEndianCPU ? -1 : 0); address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte; unsigned int byte;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
address_word vaddr; address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
/* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
paddr = (paddr ^ (reverseendian & mask)); paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0) if (BigEndianMem != 0)
paddr = paddr & ~access; paddr = paddr & ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask)); byte = ((vaddr & mask) ^ (bigendiancpu & mask));
/* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */
LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL); LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL);
/* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
(long) paddr, byte, (long) paddr, (long) memval); */ (long) paddr, byte, (long) paddr, (long) memval); */
{ {
@ -4043,20 +3999,18 @@
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte; unsigned int byte;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
address_word vaddr; address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & access) != 0) if ((vaddr & access) != 0)
{ {
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
} }
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
byte = ((vaddr & mask) ^ bigendiancpu); byte = ((vaddr & mask) ^ bigendiancpu);
memval = (word << (8 * byte)); memval = (word << (8 * byte));
StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL); StoreMemory (access, memval, 0, paddr, vaddr, isREAL);
} }
:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
@ -4067,14 +4021,12 @@
unsigned int byte; unsigned int byte;
unsigned int word; unsigned int word;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
address_word vaddr; address_word vaddr;
int nr_lhs_bits; int nr_lhs_bits;
int nr_rhs_bits; int nr_rhs_bits;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask)); paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem == 0) if (BigEndianMem == 0)
paddr = paddr & ~access; paddr = paddr & ~access;
@ -4101,7 +4053,7 @@
/* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
(long) ((unsigned64) rt >> 32), (long) rt, (long) ((unsigned64) rt >> 32), (long) rt,
(long) ((unsigned64) memval >> 32), (long) memval); */ (long) ((unsigned64) memval >> 32), (long) memval); */
StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL); StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
} }
:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
@ -4111,18 +4063,16 @@
address_word bigendiancpu = (BigEndianCPU ? -1 : 0); address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
unsigned int byte; unsigned int byte;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
address_word vaddr; address_word vaddr;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
paddr = (paddr ^ (reverseendian & mask)); paddr = (paddr ^ (reverseendian & mask));
if (BigEndianMem != 0) if (BigEndianMem != 0)
paddr &= ~access; paddr &= ~access;
byte = ((vaddr & mask) ^ (bigendiancpu & mask)); byte = ((vaddr & mask) ^ (bigendiancpu & mask));
memval = (rt << (byte * 8)); memval = (rt << (byte * 8));
StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL); StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL);
} }
@ -5118,24 +5068,20 @@
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr; address_word vaddr;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
unsigned64 v; unsigned64 v;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & AccessLength_DOUBLEWORD) != 0) if ((vaddr & AccessLength_DOUBLEWORD) != 0)
{ {
SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
AccessLength_DOUBLEWORD + 1, vaddr, read_transfer, AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
sim_core_unaligned_signal); sim_core_unaligned_signal);
} }
AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
isREAL);
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
isDATA, isREAL);
v = (unsigned64)memval; v = (unsigned64)memval;
LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4, LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
isDATA, isREAL); isREAL);
return (bigendian ? ((v << 32) | memval) : (v | (memval << 32))); return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
} }
@ -5156,24 +5102,19 @@
int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
address_word vaddr; address_word vaddr;
address_word paddr; address_word paddr;
int uncached;
unsigned64 memval; unsigned64 memval;
vaddr = loadstore_ea (SD_, base, offset); paddr = vaddr = loadstore_ea (SD_, base, offset);
if ((vaddr & AccessLength_DOUBLEWORD) != 0) if ((vaddr & AccessLength_DOUBLEWORD) != 0)
{ {
SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
AccessLength_DOUBLEWORD + 1, vaddr, write_transfer, AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
sim_core_unaligned_signal); sim_core_unaligned_signal);
} }
AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
isREAL);
memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF)); memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr, StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL);
isREAL);
memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32)); memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL);
isREAL);
} }
@ -6379,10 +6320,8 @@
address_word offset = EXTEND16 (OFFSET); address_word offset = EXTEND16 (OFFSET);
{ {
address_word vaddr = loadstore_ea (SD_, base, offset); address_word vaddr = loadstore_ea (SD_, base, offset);
address_word paddr; address_word paddr = vaddr;
int uncached; CacheOp(OP, vaddr, paddr, instruction_0);
if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
CacheOp(OP,vaddr,paddr,instruction_0);
} }
} }

87
sim/mips/sim-main.c
View file

@ -28,81 +28,6 @@
/*---------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------*/
/* Description from page A-22 of the "MIPS IV Instruction Set" manual
(revision 3.1) */
/* Translate a virtual address to a physical address and cache
coherence algorithm describing the mechanism used to resolve the
memory reference. Given the virtual address vAddr, and whether the
reference is to Instructions ot Data (IorD), find the corresponding
physical address (pAddr) and the cache coherence algorithm (CCA)
used to resolve the reference. If the virtual address is in one of
the unmapped address spaces the physical address and the CCA are
determined directly by the virtual address. If the virtual address
is in one of the mapped address spaces then the TLB is used to
determine the physical address and access type; if the required
translation is not present in the TLB or the desired access is not
permitted the function fails and an exception is taken.
NOTE: Normally (RAW == 0), when address translation fails, this
function raises an exception and does not return. */
INLINE_SIM_MAIN
(int)
address_translation (SIM_DESC sd,
sim_cpu * cpu,
address_word cia,
address_word vAddr,
int IorD,
int LorS,
address_word * pAddr,
int *CCA,
int raw)
{
int res = -1; /* TRUE : Assume good return */
#ifdef DEBUG
sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD"));
#endif
/* Check that the address is valid for this memory model */
/* For a simple (flat) memory model, we simply pass virtual
addressess through (mostly) unchanged. */
vAddr &= 0xFFFFFFFF;
*pAddr = vAddr; /* default for isTARGET */
*CCA = Uncached; /* not used for isHOST */
return (res);
}
/* Description from page A-23 of the "MIPS IV Instruction Set" manual
(revision 3.1) */
/* Prefetch data from memory. Prefetch is an advisory instruction for
which an implementation specific action is taken. The action taken
may increase performance, but must not change the meaning of the
program, or alter architecturally-visible state. */
INLINE_SIM_MAIN (void)
prefetch (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
int CCA,
address_word pAddr,
address_word vAddr,
int DATA,
int hint)
{
#ifdef DEBUG
sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
#endif /* DEBUG */
/* For our simple memory model we do nothing */
return;
}
/* Description from page A-22 of the "MIPS IV Instruction Set" manual /* Description from page A-22 of the "MIPS IV Instruction Set" manual
(revision 3.1) */ (revision 3.1) */
/* Load a value from memory. Use the cache and main memory as /* Load a value from memory. Use the cache and main memory as
@ -337,15 +262,13 @@ ifetch32 (SIM_DESC SD,
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte; unsigned int byte;
address_word paddr; address_word paddr = vaddr;
int uncached;
unsigned64 memval; unsigned64 memval;
if ((vaddr & access) != 0) if ((vaddr & access) != 0)
SignalExceptionInstructionFetch (); SignalExceptionInstructionFetch ();
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL); LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu); byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte)); return (memval >> (8 * byte));
} }
@ -363,15 +286,13 @@ ifetch16 (SIM_DESC SD,
address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
unsigned int byte; unsigned int byte;
address_word paddr; address_word paddr = vaddr;
int uncached;
unsigned64 memval; unsigned64 memval;
if ((vaddr & access) != 0) if ((vaddr & access) != 0)
SignalExceptionInstructionFetch (); SignalExceptionInstructionFetch ();
AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL); LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
byte = ((vaddr & mask) ^ bigendiancpu); byte = ((vaddr & mask) ^ bigendiancpu);
return (memval >> (8 * byte)); return (memval >> (8 * byte));
} }

22
sim/mips/sim-main.h
View file

@ -908,12 +908,6 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
/* The following are generic to all versions of the MIPS architecture /* The following are generic to all versions of the MIPS architecture
to date: */ to date: */
/* Memory Access Types (for CCA): */
#define Uncached (0)
#define CachedNoncoherent (1)
#define CachedCoherent (2)
#define Cached (3)
#define isINSTRUCTION (1 == 0) /* FALSE */ #define isINSTRUCTION (1 == 0) /* FALSE */
#define isDATA (1 == 1) /* TRUE */ #define isDATA (1 == 1) /* TRUE */
#define isLOAD (1 == 0) /* FALSE */ #define isLOAD (1 == 0) /* FALSE */
@ -942,17 +936,13 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
#define PSIZE (WITH_TARGET_ADDRESS_BITSIZE) #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \ #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD) load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr) store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
#define CacheOp(op,pAddr,vAddr,instruction) \ #define CacheOp(op,pAddr,vAddr,instruction) \
@ -962,10 +952,6 @@ INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word c
#define SyncOperation(stype) \ #define SyncOperation(stype) \
sync_operation (SD, CPU, cia, (stype)) sync_operation (SD, CPU, cia, (stype))
INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
void unpredictable_action (sim_cpu *cpu, address_word cia); void unpredictable_action (sim_cpu *cpu, address_word cia);
#define NotWordValue(val) not_word_value (SD_, (val)) #define NotWordValue(val) not_word_value (SD_, (val))
#define Unpredictable() unpredictable (SD_) #define Unpredictable() unpredictable (SD_)