x86: fold SReg{2,3}
They're the only exception to there generally being no mix of register kinds possible in an insn operand template, and there being two bits per operand for their representation is also quite wasteful, considering the low number of uses. Fold both bits and deal with the little bit of fallout. Also take the liberty and drop dead code trying to set REX_B: No segment register has RegRex set on it. Additionally I was quite surprised that PUSH/POP with the permitted segment registers is not covered by the test cases. Add the missing pieces.
This commit is contained in:
Jan Beulich
parent
206e6c58a7
commit
21df382b91
15 changed files with 13780 additions and 24056 deletions
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@ -1,3 +1,17 @@
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2019-07-16 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (type_names): Replace SReg entries.
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(pi, check_byte_reg, build_modrm_byte, i386_att_operand,
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parse_real_register): Switch to using sreg field.
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(process_operands): Likewise. Extend handling of PUSH/POP of
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segment registers. Drop dead setting of REX_B.
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* config/tc-i386-intel.c (i386_intel_simplify_register,
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i386_intel_operand): Switch to using sreg field.
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* testsuite/gas/i386/x86-64-opcode.s: Add PUSH/POP of %fs/%gs.
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* testsuite/gas/i386/x86-64-opcode.d: Adjust expectations.
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* testsuite/gas/i386/ilp32/x86-64-opcode.d: Use parent dir
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expectations.
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2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
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* testsuite/gas/bpf/mem.s: ldabs instructions do not take a `src'
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@ -283,7 +283,7 @@ i386_intel_simplify_register (expressionS *e)
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as_bad (_("invalid use of register"));
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return 0;
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}
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if (i386_regtab[reg_num].reg_type.bitfield.sreg3
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if (i386_regtab[reg_num].reg_type.bitfield.sreg
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&& i386_regtab[reg_num].reg_num == RegFlat)
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{
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as_bad (_("invalid use of pseudo-register"));
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@ -984,8 +984,7 @@ i386_intel_operand (char *operand_string, int got_a_float)
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as_bad (_("segment register name expected"));
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return 0;
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}
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if (!i386_regtab[expP->X_add_number].reg_type.bitfield.sreg2
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&& !i386_regtab[expP->X_add_number].reg_type.bitfield.sreg3)
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if (!i386_regtab[expP->X_add_number].reg_type.bitfield.sreg)
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{
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as_bad (_("invalid use of register"));
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return 0;
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@ -3031,8 +3031,7 @@ pi (const char *line, i386_insn *x)
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if (x->types[j].bitfield.reg
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|| x->types[j].bitfield.regmmx
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|| x->types[j].bitfield.regsimd
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|| x->types[j].bitfield.sreg2
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|| x->types[j].bitfield.sreg3
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|| x->types[j].bitfield.sreg
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|| x->types[j].bitfield.control
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|| x->types[j].bitfield.debug
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|| x->types[j].bitfield.test)
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@ -3129,8 +3128,7 @@ const type_names[] =
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{ OPERAND_TYPE_DEBUG, "debug reg" },
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{ OPERAND_TYPE_FLOATREG, "FReg" },
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{ OPERAND_TYPE_FLOATACC, "FAcc" },
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{ OPERAND_TYPE_SREG2, "SReg2" },
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{ OPERAND_TYPE_SREG3, "SReg3" },
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{ OPERAND_TYPE_SREG, "SReg" },
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{ OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
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{ OPERAND_TYPE_REGMMX, "rMMX" },
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{ OPERAND_TYPE_REGXMM, "rXMM" },
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@ -6575,8 +6573,7 @@ check_byte_reg (void)
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if (i.types[op].bitfield.reg
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|| i.types[op].bitfield.regmmx
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|| i.types[op].bitfield.regsimd
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|| i.types[op].bitfield.sreg2
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|| i.types[op].bitfield.sreg3
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|| i.types[op].bitfield.sreg
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|| i.types[op].bitfield.control
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|| i.types[op].bitfield.debug
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|| i.types[op].bitfield.test)
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@ -6994,18 +6991,24 @@ duplicate:
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if (i.tm.opcode_modifier.shortform)
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{
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if (i.types[0].bitfield.sreg2
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|| i.types[0].bitfield.sreg3)
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if (i.types[0].bitfield.sreg)
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{
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if (i.tm.base_opcode == POP_SEG_SHORT
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&& i.op[0].regs->reg_num == 1)
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if (flag_code != CODE_64BIT
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? i.tm.base_opcode == POP_SEG_SHORT
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&& i.op[0].regs->reg_num == 1
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: (i.tm.base_opcode | 1) == POP_SEG_SHORT
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&& i.op[0].regs->reg_num < 4)
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{
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as_bad (_("you can't `pop %scs'"), register_prefix);
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as_bad (_("you can't `%s %s%s'"),
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i.tm.name, register_prefix, i.op[0].regs->reg_name);
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return 0;
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}
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if ( i.op[0].regs->reg_num > 3 )
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{
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i.tm.base_opcode ^= POP_SEG_SHORT ^ POP_SEG386_SHORT;
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i.tm.opcode_length = 2;
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}
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i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
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if ((i.op[0].regs->reg_flags & RegRex) != 0)
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i.rex |= REX_B;
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}
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else
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{
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@ -7652,8 +7655,7 @@ build_modrm_byte (void)
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if (i.types[op].bitfield.reg
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|| i.types[op].bitfield.regbnd
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|| i.types[op].bitfield.regmask
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|| i.types[op].bitfield.sreg2
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|| i.types[op].bitfield.sreg3
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|| i.types[op].bitfield.sreg
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|| i.types[op].bitfield.control
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|| i.types[op].bitfield.debug
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|| i.types[op].bitfield.test)
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@ -10029,9 +10031,7 @@ i386_att_operand (char *operand_string)
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op_string = end_op;
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if (is_space_char (*op_string))
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++op_string;
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if (*op_string == ':'
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&& (r->reg_type.bitfield.sreg2
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|| r->reg_type.bitfield.sreg3))
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if (*op_string == ':' && r->reg_type.bitfield.sreg)
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{
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switch (r->reg_num)
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{
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@ -10894,7 +10894,7 @@ parse_real_register (char *reg_string, char **end_op)
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return (const reg_entry *) NULL;
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if ((r->reg_type.bitfield.dword
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|| r->reg_type.bitfield.sreg3
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|| (r->reg_type.bitfield.sreg && r->reg_num > 3)
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|| r->reg_type.bitfield.control
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|| r->reg_type.bitfield.debug
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|| r->reg_type.bitfield.test)
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@ -10942,7 +10942,7 @@ parse_real_register (char *reg_string, char **end_op)
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&& flag_code != CODE_64BIT)
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return (const reg_entry *) NULL;
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if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
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if (r->reg_type.bitfield.sreg && r->reg_num == RegFlat && !intel_syntax)
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return (const reg_entry *) NULL;
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return r;
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@ -2,308 +2,4 @@
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#as: -J
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#objdump: -drw
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#name: x86-64 (ILP32) opcode
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.*: +file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: 41 ff 10 callq \*\(%r8\)
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[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\)
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[ ]*[a-f0-9]+: 41 ff 10 callq \*\(%r8\)
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[ ]*[a-f0-9]+: ff 10 callq \*\(%rax\)
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[ ]*[a-f0-9]+: cb lret
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[ ]*[a-f0-9]+: c3 retq
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[ ]*[a-f0-9]+: cf iret
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[ ]*[a-f0-9]+: 66 cf iretw
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[ ]*[a-f0-9]+: 48 cf iretq
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[ ]*[a-f0-9]+: 41 8c 08 mov %cs,\(%r8\)
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[ ]*[a-f0-9]+: 8c 08 mov %cs,\(%rax\)
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[ ]*[a-f0-9]+: 41 8c 10 mov %ss,\(%r8\)
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[ ]*[a-f0-9]+: 8c 10 mov %ss,\(%rax\)
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[ ]*[a-f0-9]+: 41 8c 20 mov %fs,\(%r8\)
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[ ]*[a-f0-9]+: 8c 20 mov %fs,\(%rax\)
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[ ]*[a-f0-9]+: 41 8e 10 mov \(%r8\),%ss
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[ ]*[a-f0-9]+: 8e 10 mov \(%rax\),%ss
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[ ]*[a-f0-9]+: 41 8e 20 mov \(%r8\),%fs
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[ ]*[a-f0-9]+: 8e 20 mov \(%rax\),%fs
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[ ]*[a-f0-9]+: 41 c6 00 00 movb \$0x0,\(%r8\)
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[ ]*[a-f0-9]+: c6 00 00 movb \$0x0,\(%rax\)
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[ ]*[a-f0-9]+: 66 41 c7 00 00 70 movw \$0x7000,\(%r8\)
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[ ]*[a-f0-9]+: 66 c7 00 00 70 movw \$0x7000,\(%rax\)
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[ ]*[a-f0-9]+: 41 c7 00 00 00 00 70 movl \$0x70000000,\(%r8\)
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[ ]*[a-f0-9]+: c7 00 00 00 00 70 movl \$0x70000000,\(%rax\)
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[ ]*[a-f0-9]+: 41 c6 00 00 movb \$0x0,\(%r8\)
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[ ]*[a-f0-9]+: c6 00 00 movb \$0x0,\(%rax\)
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[ ]*[a-f0-9]+: 66 41 c7 00 00 70 movw \$0x7000,\(%r8\)
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[ ]*[a-f0-9]+: 66 c7 00 00 70 movw \$0x7000,\(%rax\)
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[ ]*[a-f0-9]+: c7 00 00 00 00 70 movl \$0x70000000,\(%rax\)
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[ ]*[a-f0-9]+: 41 c6 00 00 movb \$0x0,\(%r8\)
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[ ]*[a-f0-9]+: c6 00 00 movb \$0x0,\(%rax\)
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[ ]*[a-f0-9]+: 66 41 c7 00 00 70 movw \$0x7000,\(%r8\)
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[ ]*[a-f0-9]+: 66 c7 00 00 70 movw \$0x7000,\(%rax\)
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[ ]*[a-f0-9]+: 41 c7 00 00 00 00 70 movl \$0x70000000,\(%r8\)
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[ ]*[a-f0-9]+: c7 00 00 00 00 70 movl \$0x70000000,\(%rax\)
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[ ]*[a-f0-9]+: 49 c7 00 00 00 00 70 movq \$0x70000000,\(%r8\)
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[ ]*[a-f0-9]+: 48 c7 00 00 00 00 70 movq \$0x70000000,\(%rax\)
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[ ]*[a-f0-9]+: 41 0f c3 00 movnti %eax,\(%r8\)
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[ ]*[a-f0-9]+: 0f c3 00 movnti %eax,\(%rax\)
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[ ]*[a-f0-9]+: 49 0f c3 00 movnti %rax,\(%r8\)
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[ ]*[a-f0-9]+: 48 0f c3 00 movnti %rax,\(%rax\)
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[ ]*[a-f0-9]+: 4d 0f c3 00 movnti %r8,\(%r8\)
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[ ]*[a-f0-9]+: 4c 0f c3 00 movnti %r8,\(%rax\)
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[ ]*[a-f0-9]+: e2 fe loop 0x[0-9a-f]+
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[ ]*[a-f0-9]+: e2 fe loop 0x[0-9a-f]+
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[ ]*[a-f0-9]+: 67 e2 fd loopl 0x[0-9a-f]+
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[ ]*[a-f0-9]+: e3 fe jrcxz 0x[0-9a-f]+
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[ ]*[a-f0-9]+: 67 e3 fd jecxz 0x[0-9a-f]+
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[ ]*[a-f0-9]+: 41 f6 38 idivb \(%r8\)
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[ ]*[a-f0-9]+: f6 38 idivb \(%rax\)
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[ ]*[a-f0-9]+: 66 41 f7 38 idivw \(%r8\)
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[ ]*[a-f0-9]+: 66 f7 38 idivw \(%rax\)
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[ ]*[a-f0-9]+: 41 f7 38 idivl \(%r8\)
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[ ]*[a-f0-9]+: f7 38 idivl \(%rax\)
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[ ]*[a-f0-9]+: 49 f7 38 idivq \(%r8\)
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[ ]*[a-f0-9]+: 48 f7 38 idivq \(%rax\)
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[ ]*[a-f0-9]+: 41 f6 28 imulb \(%r8\)
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[ ]*[a-f0-9]+: f6 28 imulb \(%rax\)
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[ ]*[a-f0-9]+: 66 41 f7 28 imulw \(%r8\)
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[ ]*[a-f0-9]+: 66 f7 28 imulw \(%rax\)
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[ ]*[a-f0-9]+: 41 f7 28 imull \(%r8\)
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[ ]*[a-f0-9]+: f7 28 imull \(%rax\)
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[ ]*[a-f0-9]+: 49 f7 28 imulq \(%r8\)
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[ ]*[a-f0-9]+: 48 f7 28 imulq \(%rax\)
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[ ]*[a-f0-9]+: 66 41 0f 58 00 addpd \(%r8\),%xmm0
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[ ]*[a-f0-9]+: 66 0f 58 00 addpd \(%rax\),%xmm0
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[ ]*[a-f0-9]+: 66 45 0f 58 38 addpd \(%r8\),%xmm15
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[ ]*[a-f0-9]+: 66 44 0f 58 38 addpd \(%rax\),%xmm15
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[ ]*[a-f0-9]+: 66 45 0f 58 00 addpd \(%r8\),%xmm8
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[ ]*[a-f0-9]+: 66 44 0f 58 00 addpd \(%rax\),%xmm8
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[ ]*[a-f0-9]+: 66 41 0f 58 38 addpd \(%r8\),%xmm7
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[ ]*[a-f0-9]+: 66 0f 58 38 addpd \(%rax\),%xmm7
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[ ]*[a-f0-9]+: 66 0f 58 c0 addpd %xmm0,%xmm0
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[ ]*[a-f0-9]+: 66 45 0f 58 ff addpd %xmm15,%xmm15
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[ ]*[a-f0-9]+: 66 45 0f 58 c7 addpd %xmm15,%xmm8
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[ ]*[a-f0-9]+: f2 49 0f 2d 00 cvtsd2si \(%r8\),%rax
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[ ]*[a-f0-9]+: f2 48 0f 2d 00 cvtsd2si \(%rax\),%rax
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[ ]*[a-f0-9]+: f2 4d 0f 2d 00 cvtsd2si \(%r8\),%r8
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[ ]*[a-f0-9]+: f2 4c 0f 2d 00 cvtsd2si \(%rax\),%r8
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[ ]*[a-f0-9]+: f2 48 0f 2d c0 cvtsd2si %xmm0,%rax
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[ ]*[a-f0-9]+: f2 4d 0f 2d c7 cvtsd2si %xmm15,%r8
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[ ]*[a-f0-9]+: f2 49 0f 2d c7 cvtsd2si %xmm15,%rax
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[ ]*[a-f0-9]+: f2 4d 0f 2d c0 cvtsd2si %xmm8,%r8
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[ ]*[a-f0-9]+: f2 49 0f 2d c0 cvtsd2si %xmm8,%rax
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[ ]*[a-f0-9]+: f2 4c 0f 2d c7 cvtsd2si %xmm7,%r8
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[ ]*[a-f0-9]+: f2 48 0f 2d c7 cvtsd2si %xmm7,%rax
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[ ]*[a-f0-9]+: f2 4c 0f 2d c0 cvtsd2si %xmm0,%r8
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[ ]*[a-f0-9]+: f2 49 0f 2c 00 cvttsd2si \(%r8\),%rax
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[ ]*[a-f0-9]+: f2 48 0f 2c 00 cvttsd2si \(%rax\),%rax
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[ ]*[a-f0-9]+: f2 4d 0f 2c 00 cvttsd2si \(%r8\),%r8
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[ ]*[a-f0-9]+: f2 4c 0f 2c 00 cvttsd2si \(%rax\),%r8
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[ ]*[a-f0-9]+: f2 48 0f 2c c0 cvttsd2si %xmm0,%rax
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[ ]*[a-f0-9]+: f2 4d 0f 2c c7 cvttsd2si %xmm15,%r8
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[ ]*[a-f0-9]+: f2 49 0f 2c c7 cvttsd2si %xmm15,%rax
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[ ]*[a-f0-9]+: f2 4d 0f 2c c0 cvttsd2si %xmm8,%r8
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[ ]*[a-f0-9]+: f2 49 0f 2c c0 cvttsd2si %xmm8,%rax
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[ ]*[a-f0-9]+: f2 4c 0f 2c c7 cvttsd2si %xmm7,%r8
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[ ]*[a-f0-9]+: f2 48 0f 2c c7 cvttsd2si %xmm7,%rax
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[ ]*[a-f0-9]+: f2 4c 0f 2c c0 cvttsd2si %xmm0,%r8
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[ ]*[a-f0-9]+: f3 49 0f 2d 00 cvtss2si \(%r8\),%rax
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[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si \(%rax\),%rax
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[ ]*[a-f0-9]+: f3 4d 0f 2d 00 cvtss2si \(%r8\),%r8
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[ ]*[a-f0-9]+: f3 4c 0f 2d 00 cvtss2si \(%rax\),%r8
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[ ]*[a-f0-9]+: f3 48 0f 2d c0 cvtss2si %xmm0,%rax
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[ ]*[a-f0-9]+: f3 4d 0f 2d c7 cvtss2si %xmm15,%r8
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[ ]*[a-f0-9]+: f3 49 0f 2d c7 cvtss2si %xmm15,%rax
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[ ]*[a-f0-9]+: f3 4d 0f 2d c0 cvtss2si %xmm8,%r8
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[ ]*[a-f0-9]+: f3 49 0f 2d c0 cvtss2si %xmm8,%rax
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[ ]*[a-f0-9]+: f3 4c 0f 2d c7 cvtss2si %xmm7,%r8
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[ ]*[a-f0-9]+: f3 48 0f 2d c7 cvtss2si %xmm7,%rax
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[ ]*[a-f0-9]+: f3 4c 0f 2d c0 cvtss2si %xmm0,%r8
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[ ]*[a-f0-9]+: f3 49 0f 2c 00 cvttss2si \(%r8\),%rax
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[ ]*[a-f0-9]+: f3 48 0f 2c 00 cvttss2si \(%rax\),%rax
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[ ]*[a-f0-9]+: f3 4d 0f 2c 00 cvttss2si \(%r8\),%r8
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[ ]*[a-f0-9]+: f3 4c 0f 2c 00 cvttss2si \(%rax\),%r8
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[ ]*[a-f0-9]+: f3 48 0f 2c c0 cvttss2si %xmm0,%rax
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[ ]*[a-f0-9]+: f3 4d 0f 2c c7 cvttss2si %xmm15,%r8
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[ ]*[a-f0-9]+: f3 49 0f 2c c7 cvttss2si %xmm15,%rax
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[ ]*[a-f0-9]+: f3 4d 0f 2c c0 cvttss2si %xmm8,%r8
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[ ]*[a-f0-9]+: f3 49 0f 2c c0 cvttss2si %xmm8,%rax
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[ ]*[a-f0-9]+: f3 4c 0f 2c c7 cvttss2si %xmm7,%r8
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[ ]*[a-f0-9]+: f3 48 0f 2c c7 cvttss2si %xmm7,%rax
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[ ]*[a-f0-9]+: f3 4c 0f 2c c0 cvttss2si %xmm0,%r8
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[ ]*[a-f0-9]+: f3 41 0f 2a 00 cvtsi2ssl \(%r8\),%xmm0
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[ ]*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
|
||||
[ ]*[a-f0-9]+: f3 45 0f 2a 38 cvtsi2ssl \(%r8\),%xmm15
|
||||
[ ]*[a-f0-9]+: f3 44 0f 2a 38 cvtsi2ssl \(%rax\),%xmm15
|
||||
[ ]*[a-f0-9]+: f3 45 0f 2a 00 cvtsi2ssl \(%r8\),%xmm8
|
||||
[ ]*[a-f0-9]+: f3 44 0f 2a 00 cvtsi2ssl \(%rax\),%xmm8
|
||||
[ ]*[a-f0-9]+: f3 41 0f 2a 38 cvtsi2ssl \(%r8\),%xmm7
|
||||
[ ]*[a-f0-9]+: f3 0f 2a 38 cvtsi2ssl \(%rax\),%xmm7
|
||||
[ ]*[a-f0-9]+: f3 0f 2a c0 cvtsi2ss %eax,%xmm0
|
||||
[ ]*[a-f0-9]+: f3 44 0f 2a f8 cvtsi2ss %eax,%xmm15
|
||||
[ ]*[a-f0-9]+: f3 44 0f 2a c0 cvtsi2ss %eax,%xmm8
|
||||
[ ]*[a-f0-9]+: f3 0f 2a f8 cvtsi2ss %eax,%xmm7
|
||||
[ ]*[a-f0-9]+: f3 41 0f 2a 00 cvtsi2ssl \(%r8\),%xmm0
|
||||
[ ]*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
|
||||
[ ]*[a-f0-9]+: f3 45 0f 2a 38 cvtsi2ssl \(%r8\),%xmm15
|
||||
[ ]*[a-f0-9]+: f3 44 0f 2a 38 cvtsi2ssl \(%rax\),%xmm15
|
||||
[ ]*[a-f0-9]+: f3 45 0f 2a 00 cvtsi2ssl \(%r8\),%xmm8
|
||||
[ ]*[a-f0-9]+: f3 44 0f 2a 00 cvtsi2ssl \(%rax\),%xmm8
|
||||
[ ]*[a-f0-9]+: f3 41 0f 2a 38 cvtsi2ssl \(%r8\),%xmm7
|
||||
[ ]*[a-f0-9]+: f3 0f 2a 38 cvtsi2ssl \(%rax\),%xmm7
|
||||
[ ]*[a-f0-9]+: f2 41 0f 2a 00 cvtsi2sdl \(%r8\),%xmm0
|
||||
[ ]*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
|
||||
[ ]*[a-f0-9]+: f2 45 0f 2a 38 cvtsi2sdl \(%r8\),%xmm15
|
||||
[ ]*[a-f0-9]+: f2 44 0f 2a 38 cvtsi2sdl \(%rax\),%xmm15
|
||||
[ ]*[a-f0-9]+: f2 45 0f 2a 00 cvtsi2sdl \(%r8\),%xmm8
|
||||
[ ]*[a-f0-9]+: f2 44 0f 2a 00 cvtsi2sdl \(%rax\),%xmm8
|
||||
[ ]*[a-f0-9]+: f2 41 0f 2a 38 cvtsi2sdl \(%r8\),%xmm7
|
||||
[ ]*[a-f0-9]+: f2 0f 2a 38 cvtsi2sdl \(%rax\),%xmm7
|
||||
[ ]*[a-f0-9]+: f2 0f 2a c0 cvtsi2sd %eax,%xmm0
|
||||
[ ]*[a-f0-9]+: f2 44 0f 2a f8 cvtsi2sd %eax,%xmm15
|
||||
[ ]*[a-f0-9]+: f2 44 0f 2a c0 cvtsi2sd %eax,%xmm8
|
||||
[ ]*[a-f0-9]+: f2 0f 2a f8 cvtsi2sd %eax,%xmm7
|
||||
[ ]*[a-f0-9]+: f2 41 0f 2a 00 cvtsi2sdl \(%r8\),%xmm0
|
||||
[ ]*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
|
||||
[ ]*[a-f0-9]+: f2 45 0f 2a 38 cvtsi2sdl \(%r8\),%xmm15
|
||||
[ ]*[a-f0-9]+: f2 44 0f 2a 38 cvtsi2sdl \(%rax\),%xmm15
|
||||
[ ]*[a-f0-9]+: f2 45 0f 2a 00 cvtsi2sdl \(%r8\),%xmm8
|
||||
[ ]*[a-f0-9]+: f2 44 0f 2a 00 cvtsi2sdl \(%rax\),%xmm8
|
||||
[ ]*[a-f0-9]+: f2 41 0f 2a 38 cvtsi2sdl \(%r8\),%xmm7
|
||||
[ ]*[a-f0-9]+: f2 0f 2a 38 cvtsi2sdl \(%rax\),%xmm7
|
||||
[ ]*[a-f0-9]+: 66 41 0f 6e 00 movd \(%r8\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 0f 6e 00 movd \(%rax\),%xmm0
|
||||
[ ]*[a-f0-9]+: 66 45 0f 6e 38 movd \(%r8\),%xmm15
|
||||
[ ]*[a-f0-9]+: 66 44 0f 6e 38 movd \(%rax\),%xmm15
|
||||
[ ]*[a-f0-9]+: 66 45 0f 6e 00 movd \(%r8\),%xmm8
|
||||
[ ]*[a-f0-9]+: 66 44 0f 6e 00 movd \(%rax\),%xmm8
|
||||
[ ]*[a-f0-9]+: 66 41 0f 6e 38 movd \(%r8\),%xmm7
|
||||
[ ]*[a-f0-9]+: 66 0f 6e 38 movd \(%rax\),%xmm7
|
||||
[ ]*[a-f0-9]+: 66 0f 6e c0 movd %eax,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 44 0f 6e f8 movd %eax,%xmm15
|
||||
[ ]*[a-f0-9]+: 66 44 0f 6e c0 movd %eax,%xmm8
|
||||
[ ]*[a-f0-9]+: 66 0f 6e f8 movd %eax,%xmm7
|
||||
[ ]*[a-f0-9]+: 66 41 0f 7e 00 movd %xmm0,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 66 0f 7e 00 movd %xmm0,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 45 0f 7e 38 movd %xmm15,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 66 44 0f 7e 38 movd %xmm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 45 0f 7e 00 movd %xmm8,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 66 44 0f 7e 00 movd %xmm8,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 41 0f 7e 38 movd %xmm7,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 66 0f 7e 38 movd %xmm7,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 0f 7e c0 movd %xmm0,%eax
|
||||
[ ]*[a-f0-9]+: 66 44 0f 7e f8 movd %xmm15,%eax
|
||||
[ ]*[a-f0-9]+: 66 44 0f 7e c0 movd %xmm8,%eax
|
||||
[ ]*[a-f0-9]+: 66 0f 7e f8 movd %xmm7,%eax
|
||||
[ ]*[a-f0-9]+: 66 48 0f 6e c0 movq %rax,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 49 0f 6e c0 movq %r8,%xmm0
|
||||
[ ]*[a-f0-9]+: 66 4d 0f 6e f8 movq %r8,%xmm15
|
||||
[ ]*[a-f0-9]+: 66 48 0f 7e c0 movq %xmm0,%rax
|
||||
[ ]*[a-f0-9]+: 66 49 0f 7e c0 movq %xmm0,%r8
|
||||
[ ]*[a-f0-9]+: 66 49 0f 7e f8 movq %xmm7,%r8
|
||||
[ ]*[a-f0-9]+: f3 41 0f 7e 00 movq \(%r8\),%xmm0
|
||||
[ ]*[a-f0-9]+: f3 0f 7e 00 movq \(%rax\),%xmm0
|
||||
[ ]*[a-f0-9]+: f3 45 0f 7e 38 movq \(%r8\),%xmm15
|
||||
[ ]*[a-f0-9]+: f3 44 0f 7e 38 movq \(%rax\),%xmm15
|
||||
[ ]*[a-f0-9]+: f3 45 0f 7e 00 movq \(%r8\),%xmm8
|
||||
[ ]*[a-f0-9]+: f3 44 0f 7e 00 movq \(%rax\),%xmm8
|
||||
[ ]*[a-f0-9]+: f3 41 0f 7e 38 movq \(%r8\),%xmm7
|
||||
[ ]*[a-f0-9]+: f3 0f 7e 38 movq \(%rax\),%xmm7
|
||||
[ ]*[a-f0-9]+: f3 0f 7e c0 movq %xmm0,%xmm0
|
||||
[ ]*[a-f0-9]+: f3 45 0f 7e ff movq %xmm15,%xmm15
|
||||
[ ]*[a-f0-9]+: f3 45 0f 7e c7 movq %xmm15,%xmm8
|
||||
[ ]*[a-f0-9]+: f3 41 0f 7e ff movq %xmm15,%xmm7
|
||||
[ ]*[a-f0-9]+: f3 41 0f 7e c7 movq %xmm15,%xmm0
|
||||
[ ]*[a-f0-9]+: f3 45 0f 7e f8 movq %xmm8,%xmm15
|
||||
[ ]*[a-f0-9]+: f3 45 0f 7e c0 movq %xmm8,%xmm8
|
||||
[ ]*[a-f0-9]+: f3 41 0f 7e f8 movq %xmm8,%xmm7
|
||||
[ ]*[a-f0-9]+: f3 41 0f 7e c0 movq %xmm8,%xmm0
|
||||
[ ]*[a-f0-9]+: f3 44 0f 7e ff movq %xmm7,%xmm15
|
||||
[ ]*[a-f0-9]+: f3 44 0f 7e c7 movq %xmm7,%xmm8
|
||||
[ ]*[a-f0-9]+: f3 0f 7e ff movq %xmm7,%xmm7
|
||||
[ ]*[a-f0-9]+: f3 0f 7e c7 movq %xmm7,%xmm0
|
||||
[ ]*[a-f0-9]+: f3 44 0f 7e f8 movq %xmm0,%xmm15
|
||||
[ ]*[a-f0-9]+: f3 44 0f 7e c0 movq %xmm0,%xmm8
|
||||
[ ]*[a-f0-9]+: f3 0f 7e f8 movq %xmm0,%xmm7
|
||||
[ ]*[a-f0-9]+: 66 41 0f d6 00 movq %xmm0,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 66 0f d6 00 movq %xmm0,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 45 0f d6 38 movq %xmm15,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 66 44 0f d6 38 movq %xmm15,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 45 0f d6 00 movq %xmm8,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 66 44 0f d6 00 movq %xmm8,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 66 41 0f d6 38 movq %xmm7,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 41 0f 6e 00 movd \(%r8\),%mm0
|
||||
[ ]*[a-f0-9]+: 0f 6e 00 movd \(%rax\),%mm0
|
||||
[ ]*[a-f0-9]+: 41 0f 6e 38 movd \(%r8\),%mm7
|
||||
[ ]*[a-f0-9]+: 0f 6e 38 movd \(%rax\),%mm7
|
||||
[ ]*[a-f0-9]+: 0f 6e c0 movd %eax,%mm0
|
||||
[ ]*[a-f0-9]+: 0f 6e f8 movd %eax,%mm7
|
||||
[ ]*[a-f0-9]+: 41 0f 7e 00 movd %mm0,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 0f 7e 00 movd %mm0,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 0f 7e 38 movd %mm7,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 0f 7e 38 movd %mm7,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f 7e c0 movd %mm0,%eax
|
||||
[ ]*[a-f0-9]+: 0f 7e f8 movd %mm7,%eax
|
||||
[ ]*[a-f0-9]+: 41 0f 6f 00 movq \(%r8\),%mm0
|
||||
[ ]*[a-f0-9]+: 0f 6f 00 movq \(%rax\),%mm0
|
||||
[ ]*[a-f0-9]+: 41 0f 6f 38 movq \(%r8\),%mm7
|
||||
[ ]*[a-f0-9]+: 0f 6f 38 movq \(%rax\),%mm7
|
||||
[ ]*[a-f0-9]+: 41 0f 7f 00 movq %mm0,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 0f 7f 00 movq %mm0,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 0f 7f 38 movq %mm7,\(%r8\)
|
||||
[ ]*[a-f0-9]+: 0f 7f 38 movq %mm7,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 8f 00 popq \(%r8\)
|
||||
[ ]*[a-f0-9]+: 8f 00 popq \(%rax\)
|
||||
[ ]*[a-f0-9]+: 9d popfq
|
||||
[ ]*[a-f0-9]+: 41 ff 30 pushq \(%r8\)
|
||||
[ ]*[a-f0-9]+: ff 30 pushq \(%rax\)
|
||||
[ ]*[a-f0-9]+: 9c pushfq
|
||||
[ ]*[a-f0-9]+: 0f 77 emms
|
||||
[ ]*[a-f0-9]+: 0f 0e femms
|
||||
[ ]*[a-f0-9]+: 0f 08 invd
|
||||
[ ]*[a-f0-9]+: 41 0f 01 38 invlpg \(%r8\)
|
||||
[ ]*[a-f0-9]+: 0f 01 38 invlpg \(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 0f 01 38 invlpg \(%r8\)
|
||||
[ ]*[a-f0-9]+: 0f 01 38 invlpg \(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 0f 01 38 invlpg \(%r8\)
|
||||
[ ]*[a-f0-9]+: 0f 01 38 invlpg \(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f 00 c0 sldt %eax
|
||||
[ ]*[a-f0-9]+: 0f 00 c0 sldt %eax
|
||||
[ ]*[a-f0-9]+: 66 0f 00 c0 sldt %ax
|
||||
[ ]*[a-f0-9]+: 0f 00 00 sldt \(%rax\)
|
||||
[ ]*[a-f0-9]+: e6 00 out %al,\$0x0
|
||||
[ ]*[a-f0-9]+: 66 e7 00 out %ax,\$0x0
|
||||
[ ]*[a-f0-9]+: e7 00 out %eax,\$0x0
|
||||
[ ]*[a-f0-9]+: 66 90 xchg %ax,%ax
|
||||
[ ]*[a-f0-9]+: 87 c0 xchg %eax,%eax
|
||||
[ ]*[a-f0-9]+: 90 nop
|
||||
[ ]*[a-f0-9]+: 48 90 rex.W nop
|
||||
[ ]*[a-f0-9]+: 49 90 xchg %rax,%r8
|
||||
[ ]*[a-f0-9]+: 41 90 xchg %eax,%r8d
|
||||
[ ]*[a-f0-9]+: 41 90 xchg %eax,%r8d
|
||||
[ ]*[a-f0-9]+: 41 91 xchg %eax,%r9d
|
||||
[ ]*[a-f0-9]+: 41 91 xchg %eax,%r9d
|
||||
[ ]*[a-f0-9]+: 93 xchg %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 93 xchg %eax,%ebx
|
||||
[ ]*[a-f0-9]+: 66 41 90 xchg %ax,%r8w
|
||||
[ ]*[a-f0-9]+: 66 41 90 xchg %ax,%r8w
|
||||
[ ]*[a-f0-9]+: 66 41 91 xchg %ax,%r9w
|
||||
[ ]*[a-f0-9]+: 66 41 91 xchg %ax,%r9w
|
||||
[ ]*[a-f0-9]+: 48 0f 01 e0 smsw %rax
|
||||
[ ]*[a-f0-9]+: 0f 01 e0 smsw %eax
|
||||
[ ]*[a-f0-9]+: 66 0f 01 e0 smsw %ax
|
||||
[ ]*[a-f0-9]+: 0f 01 20 smsw \(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f 00 c8 str %eax
|
||||
[ ]*[a-f0-9]+: 0f 00 c8 str %eax
|
||||
[ ]*[a-f0-9]+: 66 0f 00 c8 str %ax
|
||||
[ ]*[a-f0-9]+: 0f 00 08 str \(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f 05 syscall
|
||||
[ ]*[a-f0-9]+: 0f 07 sysret
|
||||
[ ]*[a-f0-9]+: 0f 01 f8 swapgs
|
||||
[ ]*[a-f0-9]+: 66 68 22 22 pushw \$0x2222
|
||||
[ ]*[a-f0-9]+: f6 c9 01 test \$(0x)?0*1,%cl
|
||||
[ ]*[a-f0-9]+: 66 f7 c9 02 00 test \$(0x)?0*2,%cx
|
||||
[ ]*[a-f0-9]+: f7 c9 04 00 00 00 test \$(0x)?0*4,%ecx
|
||||
[ ]*[a-f0-9]+: 48 f7 c9 08 00 00 00 test \$(0x)?0*8,%rcx
|
||||
#pass
|
||||
#dump: ../x86-64-opcode.d
|
||||
|
|
|
|||
|
|
@ -254,9 +254,13 @@ Disassembly of section .text:
|
|||
[ ]*[a-f0-9]+: 0f 7f 38 movq %mm7,\(%rax\)
|
||||
[ ]*[a-f0-9]+: 41 8f 00 popq \(%r8\)
|
||||
[ ]*[a-f0-9]+: 8f 00 popq \(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f a1 popq %fs
|
||||
[ ]*[a-f0-9]+: 0f a9 popq %gs
|
||||
[ ]*[a-f0-9]+: 9d popfq
|
||||
[ ]*[a-f0-9]+: 41 ff 30 pushq \(%r8\)
|
||||
[ ]*[a-f0-9]+: ff 30 pushq \(%rax\)
|
||||
[ ]*[a-f0-9]+: 0f a0 pushq %fs
|
||||
[ ]*[a-f0-9]+: 0f a8 pushq %gs
|
||||
[ ]*[a-f0-9]+: 9c pushfq
|
||||
[ ]*[a-f0-9]+: 0f 77 emms
|
||||
[ ]*[a-f0-9]+: 0f 0e femms
|
||||
|
|
|
|||
|
|
@ -322,11 +322,15 @@
|
|||
# POP
|
||||
POPq (%r8) # -- -- -- 41 8F 00 ; REX to access upper reg.
|
||||
POPq (%rax) # -- -- -- -- 8F 00
|
||||
POP %fs # -- -- -- -- 0F A1
|
||||
POP %gs # -- -- -- -- 0F A9
|
||||
POPFQ # -- -- -- -- 9D
|
||||
|
||||
# PUSH
|
||||
PUSHq (%r8) # -- -- -- 41 FF 30 ; REX to access upper reg.
|
||||
PUSHq (%rax) # -- -- -- -- FF 30
|
||||
PUSH %fs # -- -- -- -- 0F A0
|
||||
PUSH %gs # -- -- -- -- 0F A8
|
||||
PUSHFQ # -- -- -- -- 9C
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2019-07-16 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* opcode/i386.h (POP_SEG386_SHORT): New.
|
||||
|
||||
2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
|
||||
|
||||
* opcode/aarch64.h (enum aarch64_insn_class): sve_size_013
|
||||
|
|
|
|||
|
|
@ -46,6 +46,7 @@
|
|||
|
||||
#define MOV_AX_DISP32 0xa0
|
||||
#define POP_SEG_SHORT 0x07
|
||||
#define POP_SEG386_SHORT 0xfa1
|
||||
#define JUMP_PC_RELATIVE 0xeb
|
||||
#define INT_OPCODE 0xcd
|
||||
#define INT3_OPCODE 0xcc
|
||||
|
|
|
|||
|
|
@ -1,3 +1,16 @@
|
|||
2019-07-16 Jan Beulich <jbeulich@suse.com>
|
||||
|
||||
* i386-gen.c (operand_type_init, operand_types): Replace SReg
|
||||
entries.
|
||||
* i386-opc.h (SReg2, SReg3): Replace by ...
|
||||
(SReg): ... this.
|
||||
(union i386_operand_type): Replace sreg fields.
|
||||
* i386-opc.tbl (mov, ): Use SReg.
|
||||
(push, pop): Likewies. Drop i386 and x86-64 specific segment
|
||||
register flavors.
|
||||
* i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
|
||||
* opcodes/i386-init.h, i386-tbl.h: Re-generate.
|
||||
|
||||
2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||||
|
||||
* bpf-desc.c: Regenerate.
|
||||
|
|
|
|||
|
|
@ -440,10 +440,8 @@ static initializer operand_type_init[] =
|
|||
"FloatReg" },
|
||||
{ "OPERAND_TYPE_FLOATACC",
|
||||
"FloatAcc" },
|
||||
{ "OPERAND_TYPE_SREG2",
|
||||
"SReg2" },
|
||||
{ "OPERAND_TYPE_SREG3",
|
||||
"SReg3" },
|
||||
{ "OPERAND_TYPE_SREG",
|
||||
"SReg" },
|
||||
{ "OPERAND_TYPE_JUMPABSOLUTE",
|
||||
"JumpAbsolute" },
|
||||
{ "OPERAND_TYPE_REGMMX",
|
||||
|
|
@ -702,8 +700,7 @@ static bitfield operand_types[] =
|
|||
BITFIELD (Control),
|
||||
BITFIELD (Debug),
|
||||
BITFIELD (Test),
|
||||
BITFIELD (SReg2),
|
||||
BITFIELD (SReg3),
|
||||
BITFIELD (SReg),
|
||||
BITFIELD (Acc),
|
||||
BITFIELD (JumpAbsolute),
|
||||
BITFIELD (EsSeg),
|
||||
|
|
|
|||
|
|
@ -1349,245 +1349,192 @@
|
|||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG8 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG16 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG32 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REG64 \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM1 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM8S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_BASEINDEX \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_INOUTPORTREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SHIFTCOUNT \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_CONTROL \
|
||||
{ { 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_TEST \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DEBUG \
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATREG \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_FLOATACC \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG2 \
|
||||
#define OPERAND_TYPE_SREG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
|
||||
#define OPERAND_TYPE_SREG3 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_JUMPABSOLUTE \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMMX \
|
||||
{ { 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGXMM \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGYMM \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGZMM \
|
||||
{ { 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGMASK \
|
||||
{ { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ESSEG \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC8 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC16 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ACC64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_DISP16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_ANYDISP \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM16_32_32S \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM64_DISP64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_IMM32_32S_64_DISP32_64 \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0 } }
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define OPERAND_TYPE_REGBND \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } }
|
||||
|
|
|
|||
|
|
@ -706,10 +706,8 @@ enum
|
|||
Debug,
|
||||
/* Test register */
|
||||
Test,
|
||||
/* 2 bit segment register */
|
||||
SReg2,
|
||||
/* 3 bit segment register */
|
||||
SReg3,
|
||||
/* Segment register */
|
||||
SReg,
|
||||
/* 1 bit immediate */
|
||||
Imm1,
|
||||
/* 8 bit immediate */
|
||||
|
|
@ -811,8 +809,7 @@ typedef union i386_operand_type
|
|||
unsigned int control:1;
|
||||
unsigned int debug:1;
|
||||
unsigned int test:1;
|
||||
unsigned int sreg2:1;
|
||||
unsigned int sreg3:1;
|
||||
unsigned int sreg:1;
|
||||
unsigned int imm1:1;
|
||||
unsigned int imm8:1;
|
||||
unsigned int imm8s:1;
|
||||
|
|
|
|||
|
|
@ -63,9 +63,9 @@ mov, 2, 0xb0, None, 1, Cpu64, W|ShortForm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldS
|
|||
// size prefix. When moving to a 32 bit register, the upper 16 bits
|
||||
// are set to an implementation defined value (on the Pentium Pro, the
|
||||
// implementation defined value is zero).
|
||||
mov, 2, 0x8c, None, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg2|SReg3, Reg16|Reg32|Reg64|RegMem }
|
||||
mov, 2, 0x8c, None, 1, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2|SReg3, Word|Unspecified|BaseIndex }
|
||||
mov, 2, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg2|Sreg3 }
|
||||
mov, 2, 0x8c, None, 1, 0, Modrm|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { SReg, Reg16|Reg32|Reg64|RegMem }
|
||||
mov, 2, 0x8c, None, 1, 0, D|Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Word|Unspecified|BaseIndex }
|
||||
mov, 2, 0x8e, None, 1, 0, Modrm|IgnoreSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg16|Reg32|Reg64, SReg }
|
||||
// Move to/from control debug registers. In the 16 or 32bit modes
|
||||
// they are 32bit. In the 64bit mode they are 64bit.
|
||||
mov, 2, 0xf20, None, 2, Cpu386|CpuNo64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_qSuf|No_ldSuf, { Control, Reg32|RegMem }
|
||||
|
|
@ -113,26 +113,22 @@ push, 1, 0x50, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|N
|
|||
push, 1, 0xff, 0x6, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
|
||||
push, 1, 0x6a, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8S }
|
||||
push, 1, 0x68, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm16|Imm32 }
|
||||
push, 1, 0x6, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2 }
|
||||
push, 1, 0xfa0, None, 2, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3 }
|
||||
push, 1, 0x6, None, 1, 0, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
|
||||
// In 64bit mode, the operand size is implicitly 64bit.
|
||||
push, 1, 0x50, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
|
||||
push, 1, 0xff, 0x6, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
|
||||
push, 1, 0x6a, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm8S }
|
||||
push, 1, 0x68, None, 1, Cpu64, DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Imm16|Imm32S }
|
||||
push, 1, 0xfa0, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg3 }
|
||||
|
||||
pusha, 0, 0x60, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
// Pop instructions.
|
||||
pop, 1, 0x58, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32 }
|
||||
pop, 1, 0x8f, 0x0, 1, CpuNo64, Modrm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg16|Reg32|Word|Dword|Unspecified|BaseIndex }
|
||||
pop, 1, 0x7, None, 1, CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2 }
|
||||
pop, 1, 0xfa1, None, 2, Cpu386|CpuNo64, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg3 }
|
||||
pop, 1, 0x7, None, 1, 0, ShortForm|DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg }
|
||||
// In 64bit mode, the operand size is implicitly 64bit.
|
||||
pop, 1, 0x58, None, 1, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64 }
|
||||
pop, 1, 0x8f, 0x0, 1, Cpu64, Modrm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { Reg16|Reg64|Word|Qword|Unspecified|BaseIndex }
|
||||
pop, 1, 0xfa1, None, 2, Cpu64, ShortForm|DefaultSize|No_bSuf|No_lSuf|No_sSuf|No_ldSuf|NoRex64, { SReg3 }
|
||||
|
||||
popa, 0, 0x61, None, 1, Cpu186|CpuNo64, DefaultSize|No_bSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
|
||||
|
||||
|
|
@ -987,7 +983,7 @@ movq, 2, 0xf6f, None, 2, CpuMMX, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_s
|
|||
movq, 2, 0xf6e, None, 2, Cpu64, D|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Size64, { Reg64|Unspecified|BaseIndex, RegMMX }
|
||||
// The segment register moves accept Reg64 so that a segment register
|
||||
// can be copied to a 64 bit register, and vice versa.
|
||||
movq, 2, 0x8c, None, 1, Cpu64, D|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg2|SReg3, Reg64|RegMem }
|
||||
movq, 2, 0x8c, None, 1, Cpu64, D|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { SReg, Reg64|RegMem }
|
||||
// Move to/from control debug registers. In the 16 or 32bit modes they
|
||||
// are 32bit. In the 64bit mode they are 64bit.
|
||||
movq, 2, 0xf20, None, 2, Cpu64, D|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Control, Reg64|RegMem }
|
||||
|
|
|
|||
|
|
@ -105,13 +105,13 @@ k5, RegMask, 0, 5, 98, 123
|
|||
k6, RegMask, 0, 6, 99, 124
|
||||
k7, RegMask, 0, 7, 100, 125
|
||||
// Segment registers.
|
||||
es, SReg2, 0, 0, 40, 50
|
||||
cs, SReg2, 0, 1, 41, 51
|
||||
ss, SReg2, 0, 2, 42, 52
|
||||
ds, SReg2, 0, 3, 43, 53
|
||||
fs, SReg3, 0, 4, 44, 54
|
||||
gs, SReg3, 0, 5, 45, 55
|
||||
flat, SReg3, 0, RegFlat, Dw2Inval, Dw2Inval
|
||||
es, SReg, 0, 0, 40, 50
|
||||
cs, SReg, 0, 1, 41, 51
|
||||
ss, SReg, 0, 2, 42, 52
|
||||
ds, SReg, 0, 3, 43, 53
|
||||
fs, SReg, 0, 4, 44, 54
|
||||
gs, SReg, 0, 5, 45, 55
|
||||
flat, SReg, 0, RegFlat, Dw2Inval, Dw2Inval
|
||||
// Control registers.
|
||||
cr0, Control, 0, 0, Dw2Inval, Dw2Inval
|
||||
cr1, Control, 0, 1, Dw2Inval, Dw2Inval
|
||||
|
|
|
|||
37202
opcodes/i386-tbl.h
37202
opcodes/i386-tbl.h
File diff suppressed because it is too large
Load diff
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Add table
Add a link
Reference in a new issue