[BZ 21005] Add support for Intel 64 rdrand and rdseed record/replay
This patch addresses BZ 21005, which is gdb failing to recognize an rdrand instruction. It enables support for both rdrand and rdseed and handles extended register addressing (R8~R15) for 16-bit, 32-bit and 64-bit. gdb/ChangeLog 2017-02-06 Luis Machado <lgustavo@codesourcery.com> * NEWS: Mention support for record/replay of Intel 64 rdrand and rdseed instructions. i386-tdep.c (i386_process_record): Handle Intel 64 rdrand and rseed. gdb/testsuite/ChangeLog: 2017-02-06 Luis Machado <lgustavo@codesourcery.com> * gdb.reverse/insn-reverse.c: Include insn-reverse-x86.c. * gdb.reverse/insn-reverse-x86.c: New file.
This commit is contained in:
Luis Machado
parent
3f7b46f2da
commit
20b477a75c
6 changed files with 303 additions and 4 deletions
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@ -1,3 +1,9 @@
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2017-02-06 Luis Machado <lgustavo@codesourcery.com>
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* NEWS: Mention support for record/replay of Intel 64 rdrand and
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rdseed instructions.
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i386-tdep.c (i386_process_record): Handle Intel 64 rdrand and rseed.
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2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
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PR tdep/20936
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3
gdb/NEWS
3
gdb/NEWS
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@ -3,6 +3,9 @@
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*** Changes since GDB 7.12
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* GDB now supports recording and replaying rdrand and rdseed Intel 64
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instructions.
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* Building GDB and GDBserver now requires a C++11 compiler.
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For example, GCC 4.8 or later.
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@ -5501,14 +5501,36 @@ i386_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
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I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
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break;
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case 0x0fc7: /* cmpxchg8b */
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case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
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if (i386_record_modrm (&ir))
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return -1;
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if (ir.mod == 3)
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{
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ir.addr -= 2;
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opcode = opcode << 8 | ir.modrm;
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goto no_support;
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/* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
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an extended opcode. rdrand has bits 110 (/6) and rdseed
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has bits 111 (/7). */
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if (ir.reg == 6 || ir.reg == 7)
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{
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/* The storage register is described by the 3 R/M bits, but the
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REX.B prefix may be used to give access to registers
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R8~R15. In this case ir.rex_b + R/M will give us the register
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in the range R8~R15.
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REX.W may also be used to access 64-bit registers, but we
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already record entire registers and not just partial bits
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of them. */
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I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir.rex_b + ir.rm);
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/* These instructions also set conditional bits. */
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I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM);
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break;
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}
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else
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{
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/* We don't handle this particular instruction yet. */
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ir.addr -= 2;
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opcode = opcode << 8 | ir.modrm;
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goto no_support;
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}
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}
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I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM);
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I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM);
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@ -1,3 +1,8 @@
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2017-02-06 Luis Machado <lgustavo@codesourcery.com>
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* gdb.reverse/insn-reverse.c: Include insn-reverse-x86.c.
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* gdb.reverse/insn-reverse-x86.c: New file.
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2017-02-06 Ivo Raisr <ivo.raisr@oracle.com>
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PR tdep/20936
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261
gdb/testsuite/gdb.reverse/insn-reverse-x86.c
Normal file
261
gdb/testsuite/gdb.reverse/insn-reverse-x86.c
Normal file
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@ -0,0 +1,261 @@
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/* This testcase is part of GDB, the GNU debugger.
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Copyright 2017 Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <cpuid.h>
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#include <stdint.h>
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/* 0 if the CPU supports rdrand/rdseed and non-zero otherwise. */
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static unsigned int supports_rdrand;
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/* Returns non-zero if rdrand/rdseed instructions are supported and
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zero otherwise. */
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static unsigned int
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check_rdrand_support (void)
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{
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unsigned int rdrand_mask = (1 << 30);
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unsigned int eax, ebx, ecx, edx;
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__get_cpuid (1, &eax, &ebx, &ecx, &edx);
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return ((ecx & rdrand_mask) == rdrand_mask);
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}
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/* Test rdrand support for various output registers. */
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void
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rdrand (void)
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{
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/* Get a random number from the rdrand assembly instruction. */
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register uint64_t number;
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if (!supports_rdrand)
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return;
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/* 16-bit random numbers. */
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__asm__ volatile ("rdrand %%ax;" : "=r" (number));
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__asm__ volatile ("rdrand %%bx;" : "=r" (number));
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__asm__ volatile ("rdrand %%cx;" : "=r" (number));
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__asm__ volatile ("rdrand %%dx;" : "=r" (number));
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__asm__ volatile ("mov %%di, %%ax;" : "=r" (number));
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__asm__ volatile ("rdrand %%di;" : "=r" (number));
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__asm__ volatile ("mov %%ax, %%di;" : "=r" (number));
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__asm__ volatile ("mov %%si, %%ax;" : "=r" (number));
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__asm__ volatile ("rdrand %%si;" : "=r" (number));
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__asm__ volatile ("mov %%ax, %%si;" : "=r" (number));
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__asm__ volatile ("mov %%bp, %%ax;" : "=r" (number));
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__asm__ volatile ("rdrand %%bp;" : "=r" (number));
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__asm__ volatile ("mov %%ax, %%bp;" : "=r" (number));
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__asm__ volatile ("mov %%sp, %%ax;" : "=r" (number));
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__asm__ volatile ("rdrand %%sp;" : "=r" (number));
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__asm__ volatile ("mov %%ax, %%sp;" : "=r" (number));
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__asm__ volatile ("rdrand %%r8w;" : "=r" (number));
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__asm__ volatile ("rdrand %%r9w;" : "=r" (number));
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__asm__ volatile ("rdrand %%r10w;" : "=r" (number));
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__asm__ volatile ("rdrand %%r11w;" : "=r" (number));
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__asm__ volatile ("rdrand %%r12w;" : "=r" (number));
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__asm__ volatile ("rdrand %%r13w;" : "=r" (number));
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__asm__ volatile ("rdrand %%r14w;" : "=r" (number));
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__asm__ volatile ("rdrand %%r15w;" : "=r" (number));
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/* 32-bit random numbers. */
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__asm__ volatile ("rdrand %%eax;" : "=r" (number));
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__asm__ volatile ("rdrand %%ebx;" : "=r" (number));
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__asm__ volatile ("rdrand %%ecx;" : "=r" (number));
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__asm__ volatile ("rdrand %%edx;" : "=r" (number));
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__asm__ volatile ("mov %%rdi, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%edi;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rdi;" : "=r" (number));
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__asm__ volatile ("mov %%rsi, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%esi;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rsi;" : "=r" (number));
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__asm__ volatile ("mov %%rbp, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%ebp;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rbp;" : "=r" (number));
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__asm__ volatile ("mov %%rsp, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%esp;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rsp;" : "=r" (number));
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__asm__ volatile ("rdrand %%r8d;" : "=r" (number));
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__asm__ volatile ("rdrand %%r9d;" : "=r" (number));
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__asm__ volatile ("rdrand %%r10d;" : "=r" (number));
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__asm__ volatile ("rdrand %%r11d;" : "=r" (number));
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__asm__ volatile ("rdrand %%r12d;" : "=r" (number));
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__asm__ volatile ("rdrand %%r13d;" : "=r" (number));
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__asm__ volatile ("rdrand %%r14d;" : "=r" (number));
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__asm__ volatile ("rdrand %%r15d;" : "=r" (number));
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/* 64-bit random numbers. */
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__asm__ volatile ("rdrand %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%rbx;" : "=r" (number));
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__asm__ volatile ("rdrand %%rcx;" : "=r" (number));
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__asm__ volatile ("rdrand %%rdx;" : "=r" (number));
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__asm__ volatile ("mov %%rdi, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%rdi;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rdi;" : "=r" (number));
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__asm__ volatile ("mov %%rsi, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%rsi;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rsi;" : "=r" (number));
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__asm__ volatile ("mov %%rbp, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%rbp;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rbp;" : "=r" (number));
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__asm__ volatile ("mov %%rsp, %%rax;" : "=r" (number));
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__asm__ volatile ("rdrand %%rsp;" : "=r" (number));
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__asm__ volatile ("mov %%rax, %%rsp;" : "=r" (number));
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__asm__ volatile ("rdrand %%r8;" : "=r" (number));
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__asm__ volatile ("rdrand %%r9;" : "=r" (number));
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__asm__ volatile ("rdrand %%r10;" : "=r" (number));
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__asm__ volatile ("rdrand %%r11;" : "=r" (number));
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__asm__ volatile ("rdrand %%r12;" : "=r" (number));
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__asm__ volatile ("rdrand %%r13;" : "=r" (number));
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__asm__ volatile ("rdrand %%r14;" : "=r" (number));
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__asm__ volatile ("rdrand %%r15;" : "=r" (number));
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}
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/* Test rdseed support for various output registers. */
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void
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rdseed (void)
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{
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/* Get a random seed from the rdseed assembly instruction. */
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register long seed;
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if (!supports_rdrand)
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return;
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/* 16-bit random seeds. */
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__asm__ volatile ("rdseed %%ax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%bx;" : "=r" (seed));
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__asm__ volatile ("rdseed %%cx;" : "=r" (seed));
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__asm__ volatile ("rdseed %%dx;" : "=r" (seed));
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__asm__ volatile ("mov %%di, %%ax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%di;" : "=r" (seed));
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__asm__ volatile ("mov %%ax, %%di;" : "=r" (seed));
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__asm__ volatile ("mov %%si, %%ax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%si;" : "=r" (seed));
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__asm__ volatile ("mov %%ax, %%si;" : "=r" (seed));
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__asm__ volatile ("mov %%bp, %%ax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%bp;" : "=r" (seed));
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__asm__ volatile ("mov %%ax, %%bp;" : "=r" (seed));
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__asm__ volatile ("mov %%sp, %%ax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%sp;" : "=r" (seed));
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__asm__ volatile ("mov %%ax, %%sp;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r8w;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r9w;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r10w;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r11w;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r12w;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r13w;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r14w;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r15w;" : "=r" (seed));
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/* 32-bit random seeds. */
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__asm__ volatile ("rdseed %%eax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%ebx;" : "=r" (seed));
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__asm__ volatile ("rdseed %%ecx;" : "=r" (seed));
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__asm__ volatile ("rdseed %%edx;" : "=r" (seed));
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__asm__ volatile ("mov %%rdi, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%edi;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rdi;" : "=r" (seed));
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__asm__ volatile ("mov %%rsi, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%esi;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rsi;" : "=r" (seed));
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__asm__ volatile ("mov %%rbp, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%ebp;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rbp;" : "=r" (seed));
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__asm__ volatile ("mov %%rsp, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%esp;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rsp;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r8d;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r9d;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r10d;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r11d;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r12d;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r13d;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r14d;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r15d;" : "=r" (seed));
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/* 64-bit random seeds. */
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__asm__ volatile ("rdseed %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%rbx;" : "=r" (seed));
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__asm__ volatile ("rdseed %%rcx;" : "=r" (seed));
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__asm__ volatile ("rdseed %%rdx;" : "=r" (seed));
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__asm__ volatile ("mov %%rdi, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%rdi;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rdi;" : "=r" (seed));
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__asm__ volatile ("mov %%rsi, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%rsi;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rsi;" : "=r" (seed));
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__asm__ volatile ("mov %%rbp, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%rbp;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rbp;" : "=r" (seed));
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__asm__ volatile ("mov %%rsp, %%rax;" : "=r" (seed));
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__asm__ volatile ("rdseed %%rsp;" : "=r" (seed));
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__asm__ volatile ("mov %%rax, %%rsp;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r8;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r9;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r10;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r11;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r12;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r13;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r14;" : "=r" (seed));
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__asm__ volatile ("rdseed %%r15;" : "=r" (seed));
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}
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/* Initialize arch-specific bits. */
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static void
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initialize (void)
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{
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/* Initialize supported features. */
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supports_rdrand = check_rdrand_support ();
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}
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/* Functions testing instruction decodings. GDB will test all of these. */
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static testcase_ftype testcases[] =
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{
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rdrand,
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rdseed
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};
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@ -24,6 +24,8 @@ typedef void (*testcase_ftype) (void);
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#include "insn-reverse-aarch64.c"
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#elif (defined __arm__)
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#include "insn-reverse-arm.c"
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#elif (defined __x86_64__) || (defined __i386__)
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#include "insn-reverse-x86.c"
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#else
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/* We get here if the current architecture being tested doesn't have any
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record/replay instruction decoding tests implemented. */
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