FreeChainXenon/binutils-gdb
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

2003-07-08 Michael Snyder <msnyder@redhat.com>

Browse source 
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
	fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
	float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s,
	fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s,
	shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
This commit is contained in:
Michael Snyder 2003-07-23 21:40:43 +00:00
parent c13a4caaf8
commit 20358547b7
26 changed files with 2293 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
sim/testsuite/sim/sh/ChangeLog Normal file
View file

@ -0,0 +1,14 @@
2003-07-08 Michael Snyder <msnyder@redhat.com>
* allinsn.exp, testutils.inc, add.s, fabs.s, fadd.s, fcmpeq.s,
fcmpgt.s, fcnvds.s, fcnvsd.s, fdiv.s, fldi0.s, fldi1.s, flds.s,
float.s, fmac.s, fmov.s, fmul.s, fneg.s, frchg.s, fschg.s,
fsqrt.s, fsub.s, ftrc.s, shll16.s, shll2.s, shll8.s, shll.s,
shlr16.s, shlr2.s, shlr8.s, shlr.s, swap.s: New files.
Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:

86
sim/testsuite/sim/sh/add.s Normal file
View file

@ -0,0 +1,86 @@
# sh testcase for add
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
.align 2
_x: .long 1
_y: .long 1
start
add_reg_reg_direct:
set_grs_a5a5
mov.l i, r1
mov.l j, r2
add r1, r2
test_gr0_a5a5
assertreg 2 r1
assertreg 4 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
add_reg_reg_indirect:
set_grs_a5a5
mov.l x, r1
mov.l y, r2
mov.l @r1, r1
mov.l @r2, r2
add r1, r2
test_gr0_a5a5
assertreg 1 r1
assertreg 2 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
add_imm_reg:
set_grs_a5a5
add #0x16, r1
test_gr0_a5a5
assertreg 0xa5a5a5bb r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
.align 2
x: .long _x
y: .long _y
i: .long 2
j: .long 2

37
sim/testsuite/sim/sh/allinsn.exp Normal file
View file

@ -0,0 +1,37 @@
# sh tests
set all "sh shdsp"
if [istarget sh-*elf] {
run_sim_test add.s $all
run_sim_test fabs.s sh
run_sim_test fadd.s sh
run_sim_test fcmpeq.s sh
run_sim_test fcmpgt.s sh
run_sim_test fcnvds.s sh
run_sim_test fcnvsd.s sh
run_sim_test fdiv.s sh
run_sim_test fldi0.s sh
run_sim_test fldi1.s sh
run_sim_test flds.s sh
run_sim_test float.s sh
run_sim_test fmac.s sh
run_sim_test fmov.s sh
run_sim_test fmul.s sh
run_sim_test fneg.s sh
run_sim_test frchg.s sh
run_sim_test fschg.s sh
run_sim_test fsqrt.s sh
run_sim_test fsub.s sh
run_sim_test ftrc.s sh
run_sim_test pmuls.s shdsp
run_sim_test shll.s $all
run_sim_test shll2.s $all
run_sim_test shll8.s $all
run_sim_test shll16.s $all
run_sim_test shlr.s $all
run_sim_test shlr2.s $all
run_sim_test shlr8.s $all
run_sim_test shlr16.s $all
run_sim_test swap.s $all
}

115
sim/testsuite/sim/sh/fabs.s Normal file
View file

@ -0,0 +1,115 @@
# sh testcase for fabs
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fabs_freg_b0:
single_prec
bank0
set_grs_a5a5
set_fprs_a5a5
# fabs(0.0) = 0.0.
fldi0 fr0
fabs fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# fabs(1.0) = 1.0.
fldi1 fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
fabs fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L3
fail
.L3:
test_grs_a5a5
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fabs_dreg_b0:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
double_prec
# fabs(0.0) = 0.0.
fldi0 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 0 dr0
# fabs(1.0) = 1.0.
fldi1 fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L4
fail
.L4:
# fabs(-1.0) = 1.0.
fldi1 fr0
fneg fr0
flds fr0, fpul
fcnvsd fpul, dr0
fabs dr0
assert_dpreg_i 1 dr0
# check.
fldi1 fr2
flds fr2, fpul
fcnvsd fpul, dr2
fcmp/eq dr0, dr2
bt .L5
fail
.L5:
test_grs_a5a5
assert_dpreg_i 1 dr0
assert_dpreg_i 1 dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

75
sim/testsuite/sim/sh/fadd.s Normal file
View file

@ -0,0 +1,75 @@
# sh testcase for fadd
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fadd_freg_freg_b0:
set_grs_a5a5
set_fprs_a5a5
bank0
fldi1 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 2 fr1
fldi0 fr0
fldi1 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
fldi1 fr0
fldi0 fr1
fadd fr0, fr1
assert_fpreg_i 1 fr1
test_grs_a5a5
assert_fpreg_i 1 fr0
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fadd_dreg_dreg_b0:
set_grs_a5a5
set_fprs_a5a5
double_prec
fldi1 fr0
fldi1 fr2
flds fr0, fpul
fcnvsd fpul, dr0
flds fr2, fpul
fcnvsd fpul, dr2
fadd dr0, dr2
fcnvds dr2, fpul
fsts fpul, fr0
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_dpreg_i 2, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

119
sim/testsuite/sim/sh/fcmpeq.s Normal file
View file

@ -0,0 +1,119 @@
# sh testcase for fcmpeq
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpeq_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 == 1.0.
fldi1 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# 0.0 != 1.0.
fldi0 fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L1
fail
.L1:
# 1.0 != 0.0.
fldi1 fr0
fldi0 fr1
fcmp/eq fr0, fr1
bf .L2
fail
.L2:
# 2.0 != 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/eq fr0, fr1
bf .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 1, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fcmpeq_double:
# 1.0 == 1.0
set_grs_a5a5
set_fprs_a5a5
double_prec
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# 0.0 != 1.0
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L11
fail
.L11:
# 1.0 != 0.0
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L12
fail
.L12:
# 2.0 != 1.0
fldi1 fr0
single_prec
fadd fr0, fr0
double_prec
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/eq dr0, dr2
bf .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

119
sim/testsuite/sim/sh/fcmpgt.s Normal file
View file

@ -0,0 +1,119 @@
# sh testcase for fcmpgt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fcmpgt_single:
set_grs_a5a5
set_fprs_a5a5
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L0
fail
.L0:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr1
fcmp/gt fr0, fr1
bt .L1
fail
.L1:
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr1
fcmp/gt fr0, fr1
bf .L2
fail
.L2:
# 2.0 > 1.0
fldi1 fr0
fadd fr0, fr0
fldi1 fr1
fcmp/gt fr0, fr1
bf .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 1, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fcmpgt_double:
# double precision tests.
set_grs_a5a5
set_fprs_a5a5
double_prec
# 1.0 !> 1.0.
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L10
fail
.L10:
# 0.0 !> 1.0.
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bt .L11
fail
.L11:
# 1.0 > 0.0.
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L12
fail
.L12:
# 2.0 > 1.0.
fldi1 fr0
single_prec
fadd fr0, fr0
double_prec
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fcmp/gt dr0, dr2
bf .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 1, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

56
sim/testsuite/sim/sh/fcnvds.s Normal file
View file

@ -0,0 +1,56 @@
# sh testcase for fcnvds
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
double_prec
sz_64
set_grs_a5a5
set_fprs_a5a5
mov.l ax, r0
fmov @r0, dr0
fcnvds dr0, fpul
fsts fpul, fr2
assert_dpreg_i 5, dr0
single_prec
assert_fpreg_i 5, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
assertreg0 x
test_gr_a5a5 r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0
.align 2
x: .double 5.0
ax: .long x

40
sim/testsuite/sim/sh/fcnvsd.s Normal file
View file

@ -0,0 +1,40 @@
# sh testcase for fcnvsd
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
set_grs_a5a5
set_fprs_a5a5
double_prec
fldi1 fr0
flds fr0, fpul
fcnvsd fpul, dr2
assert_dpreg_i 1, dr2
# Convert back.
fcnvds dr2, fpul
fsts fpul, fr1
single_prec
assert_fpreg_i 1, fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
test_grs_a5a5
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

91
sim/testsuite/sim/sh/fdiv.s Normal file
View file

@ -0,0 +1,91 @@
# sh testcase for fdiv
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fdiv_single:
# Single test
set_grs_a5a5
set_fprs_a5a5
single_prec
# 1.0 / 0.0 should be INF
# (and not crash the sim).
fldi0 fr0
fldi1 fr1
fdiv fr0, fr1
assert_fpreg_x 0x7f800000, fr1
# 0.0 / 1.0 == 0.0.
fldi0 fr0
fldi1 fr1
fdiv fr1, fr0
assert_fpreg_x 0, fr0
# 2.0 / 1.0 == 2.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr1, fr2
assert_fpreg_i 2, fr2
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
fldi1 fr2
fadd fr2, fr2
fdiv fr2, fr1
# fr1 should contain 0.5.
fadd fr1, fr1
assert_fpreg_i 1, fr1
test_grs_a5a5
assert_fpreg_i 2, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fdiv_double:
# Double test
set_grs_a5a5
set_fprs_a5a5
# (1.0 / 2.0) + (1.0 / 2.0) == 1.0.
fldi1 fr1
fldi1 fr2
# This add must be in single precision. The rest must be in double.
fadd fr2, fr2
double_prec
_s2d fr1, dr0
_s2d fr2, dr2
fdiv dr2, dr0
# dr0 should contain 0.5.
# double it, expect 1.0.
fadd dr0, dr0
assert_dpreg_i 1, dr0
assert_dpreg_i 2, dr2
test_grs_a5a5
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

37
sim/testsuite/sim/sh/fldi0.s Normal file
View file

@ -0,0 +1,37 @@
# sh testcase for fldi0 $frn
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fldi0_single:
set_grs_a5a5
set_fprs_a5a5
fldi0 fr0
fldi0 fr2
fldi0 fr4
fldi0 fr6
fldi0 fr8
fldi0 fr10
fldi0 fr12
fldi0 fr14
test_grs_a5a5
assert_fpreg_i 0 fr0
assert_fpreg_i 0 fr2
assert_fpreg_i 0 fr4
assert_fpreg_i 0 fr6
assert_fpreg_i 0 fr8
assert_fpreg_i 0 fr10
assert_fpreg_i 0 fr12
assert_fpreg_i 0 fr14
assert_fpreg_x 0xa5a5a5a5 fr1
assert_fpreg_x 0xa5a5a5a5 fr3
assert_fpreg_x 0xa5a5a5a5 fr5
assert_fpreg_x 0xa5a5a5a5 fr7
assert_fpreg_x 0xa5a5a5a5 fr9
assert_fpreg_x 0xa5a5a5a5 fr11
assert_fpreg_x 0xa5a5a5a5 fr13
assert_fpreg_x 0xa5a5a5a5 fr15
pass
exit 0

38
sim/testsuite/sim/sh/fldi1.s Normal file
View file

@ -0,0 +1,38 @@
# sh testcase for fldi1 $frn
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fldi1_single:
set_grs_a5a5
set_fprs_a5a5
fldi1 fr1
fldi1 fr3
fldi1 fr5
fldi1 fr7
fldi1 fr9
fldi1 fr11
fldi1 fr13
fldi1 fr15
test_grs_a5a5
assert_fpreg_x 0xa5a5a5a5 fr0
assert_fpreg_x 0xa5a5a5a5 fr2
assert_fpreg_x 0xa5a5a5a5 fr4
assert_fpreg_x 0xa5a5a5a5 fr6
assert_fpreg_x 0xa5a5a5a5 fr8
assert_fpreg_x 0xa5a5a5a5 fr10
assert_fpreg_x 0xa5a5a5a5 fr12
assert_fpreg_x 0xa5a5a5a5 fr14
assert_fpreg_i 1 fr1
assert_fpreg_i 1 fr3
assert_fpreg_i 1 fr5
assert_fpreg_i 1 fr7
assert_fpreg_i 1 fr9
assert_fpreg_i 1 fr11
assert_fpreg_i 1 fr13
assert_fpreg_i 1 fr15
pass
exit 0

43
sim/testsuite/sim/sh/flds.s Normal file
View file

@ -0,0 +1,43 @@
# sh testcase for flds
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
flds_zero:
set_grs_a5a5
set_fprs_a5a5
fldi0 fr0
flds fr0, fpul
fsts fpul, fr1
fcmp/eq fr0, fr1
bt flds_one
fail
flds_one:
fldi1 fr0
flds fr0, fpul
fsts fpul, fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
test_grs_a5a5
assert_fpreg_i 1, fr0
assert_fpreg_i 1, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

120
sim/testsuite/sim/sh/fsqrt.s Normal file
View file

@ -0,0 +1,120 @@
# sh testcase for fsqrt
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsqrt_single:
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
fsqrt fr0
fldi0 fr1
fcmp/eq fr0, fr1
bt .L0
fail
.L0:
# sqrt(1.0) = 1.0.
fldi1 fr0
fsqrt fr0
fldi1 fr1
fcmp/eq fr0, fr1
bt .L1
fail
.L1:
# sqrt(4.0) = 2.0
fldi1 fr0
# Double it.
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
fsqrt fr0
fldi1 fr1
# Double it.
fadd fr1, fr1
fcmp/eq fr0, fr1
bt .L2
fail
.L2:
test_grs_a5a5
assert_fpreg_i 2, fr0
assert_fpreg_i 2, fr1
test_fpr_a5a5 fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fsqrt_double:
double_prec
set_grs_a5a5
set_fprs_a5a5
# sqrt(0.0) = 0.0.
fldi0 fr0
_s2d fr0, dr0
fsqrt dr0
fldi0 fr2
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L10
fail
.L10:
# sqrt(1.0) = 1.0.
fldi1 fr0
_s2d fr0, dr0
fsqrt dr0
fldi1 fr2
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L11
fail
.L11:
# sqrt(4.0) = 2.0.
fldi1 fr0
# Double it.
single_prec
fadd fr0, fr0
# Double it again.
fadd fr0, fr0
double_prec
_s2d fr0, dr0
fsqrt dr0
fldi1 fr2
# Double it.
single_prec
fadd fr2, fr2
double_prec
_s2d fr2, dr2
fcmp/eq dr0, dr2
bt .L12
fail
.L12:
test_grs_a5a5
assert_dpreg_i 2, dr0
assert_dpreg_i 2, dr2
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

136
sim/testsuite/sim/sh/fsub.s Normal file
View file

@ -0,0 +1,136 @@
# sh testcase for fsub
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
fsub_single:
set_grs_a5a5
set_fprs_a5a5
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L0
fail
.L0:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr1
fsub fr0, fr1
fldi1 fr2
fcmp/eq fr1, fr2
bt .L1
fail
.L1:
# 1.0 - 1.0 = 0.0.
fldi1 fr0
fldi1 fr1
fsub fr0, fr1
fldi0 fr2
fcmp/eq fr1, fr2
bt .L2
fail
.L2:
# 0.0 - 1.0 = -1.0.
fldi1 fr0
fldi0 fr1
fsub fr0, fr1
fldi1 fr2
fneg fr2
fcmp/eq fr1, fr2
bt .L3
fail
.L3:
test_grs_a5a5
assert_fpreg_i 1, fr0
assert_fpreg_i -1, fr1
assert_fpreg_i -1, fr2
test_fpr_a5a5 fr3
test_fpr_a5a5 fr4
test_fpr_a5a5 fr5
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
fsub_double:
set_grs_a5a5
set_fprs_a5a5
double_prec
# 0.0 - 0.0 = 0.0.
fldi0 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi0 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L10
fail
.L10:
# 1.0 - 0.0 = 1.0.
fldi0 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi1 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L11
fail
.L11:
# 1.0 - 1.0 = 0.0.
fldi1 fr0
fldi1 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi0 fr4
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L12
fail
.L12:
# 0.0 - 1.0 = -1.0.
fldi1 fr0
fldi0 fr2
_s2d fr0, dr0
_s2d fr2, dr2
fsub dr0, dr2
fldi1 fr4
single_prec
fneg fr4
double_prec
_s2d fr4, dr4
fcmp/eq dr2, dr4
bt .L13
fail
.L13:
test_grs_a5a5
assert_dpreg_i 1, dr0
assert_dpreg_i -1, dr2
assert_dpreg_i -1, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

156
sim/testsuite/sim/sh/ftrc.s Normal file
View file

@ -0,0 +1,156 @@
# sh testcase for ftrc
# mach: sh
# as(sh): -defsym sim_cpu=0
.include "testutils.inc"
start
ftrc_single:
set_grs_a5a5
set_fprs_a5a5
# ftrc(0.0) = 0.
fldi0 fr0
ftrc fr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L0
fail
.L0:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr1
fldi1 fr2
# double it.
fadd fr2, fr2
# form the fraction.
fdiv fr2, fr1
fadd fr1, fr0
# now we've got 1.5 in fr0.
ftrc fr0, fpul
# check results.
mov #1, r0
sts fpul, r1
cmp/eq r0, r1
bt .L1
fail
.L1:
# ftrc(-1.5) = -1.
fldi1 fr0
fneg fr0
fldi1 fr1
fldi1 fr2
# double it.
fadd fr2, fr2
# form the fraction.
fdiv fr2, fr1
fneg fr1
# -1 + -0.5 = -1.5.
fadd fr1, fr0
# now we've got 1.5 in fr0.
ftrc fr0, fpul
# check results.
mov #1, r0
neg r0, r0
sts fpul, r1
cmp/eq r0, r1
bt ftrc_double
fail
ftrc_double:
double_prec
# ftrc(0.0) = 0.
fldi0 fr0
_s2d fr0, dr0
ftrc dr0, fpul
# check results.
mov #0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L10
fail
.L10:
# ftrc(1.5) = 1.
fldi1 fr0
fldi1 fr2
fldi1 fr4
# double it.
single_prec
fadd fr4, fr4
# form 0.5.
fdiv fr4, fr2
fadd fr2, fr0
double_prec
# now we've got 1.5 in fr0, so do some single->double
# conversions and perform the ftrc.
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
ftrc dr0, fpul
# check results.
mov #1, r0
sts fpul, r1
cmp/eq r0, r1
bt .L11
fail
.L11:
# ftrc(-1.5) = -1.
fldi1 fr0
fneg fr0
fldi1 fr2
fldi1 fr4
single_prec
# double it.
fadd fr4, fr4
# form the fraction.
fdiv fr4, fr2
fneg fr2
# -1 + -0.5 = -1.5.
fadd fr2, fr0
double_prec
# now we've got 1.5 in fr0, so do some single->double
# conversions and perform the ftrc.
_s2d fr0, dr0
_s2d fr2, dr2
_s2d fr4, dr4
ftrc dr0, fpul
# check results.
mov #1, r0
neg r0, r0
sts fpul, r1
cmp/eq r0, r1
bt .L12
fail
.L12:
assertreg0 -1
assertreg -1, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
assert_dpreg_i 2, dr4
test_fpr_a5a5 fr6
test_fpr_a5a5 fr7
test_fpr_a5a5 fr8
test_fpr_a5a5 fr9
test_fpr_a5a5 fr10
test_fpr_a5a5 fr11
test_fpr_a5a5 fr12
test_fpr_a5a5 fr13
test_fpr_a5a5 fr14
test_fpr_a5a5 fr15
pass
exit 0

91
sim/testsuite/sim/sh/shll.s Normal file
View file

@ -0,0 +1,91 @@
# sh testcase for shll
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll:
set_grs_a5a5
mov #1, r1
shll r1
assertreg 2, r1
shll r1
assertreg 4, r1
shll r1
assertreg 8, r1
shll r1
assertreg 16, r1
shll r1
assertreg 32, r1
shll r1
assertreg 64, r1
shll r1
assertreg 0x80, r1
shll r1
assertreg 0x100, r1
shll r1
assertreg 0x200, r1
shll r1
assertreg 0x400, r1
shll r1
assertreg 0x800, r1
shll r1
assertreg 0x1000, r1
shll r1
assertreg 0x2000, r1
shll r1
assertreg 0x4000, r1
shll r1
assertreg 0x8000, r1
shll r1
assertreg 0x10000, r1
shll r1
assertreg 0x20000, r1
shll r1
assertreg 0x40000, r1
shll r1
assertreg 0x80000, r1
shll r1
assertreg 0x100000, r1
shll r1
assertreg 0x200000, r1
shll r1
assertreg 0x400000, r1
shll r1
assertreg 0x800000, r1
shll r1
assertreg 0x1000000, r1
shll r1
assertreg 0x2000000, r1
shll r1
assertreg 0x4000000, r1
shll r1
assertreg 0x8000000, r1
shll r1
assertreg 0x10000000, r1
shll r1
assertreg 0x20000000, r1
shll r1
assertreg 0x40000000, r1
shll r1
assertreg 0x80000000, r1
shll r1
assertreg 0, r1
shll r1
assertreg 0, r1
# another:
mov #1, r1
shll r1
shll r1
shll r1
assertreg 8, r1
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0

46
sim/testsuite/sim/sh/shll16.s Normal file
View file

@ -0,0 +1,46 @@
# sh testcase for shll16
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll16:
set_grs_a5a5
mov #0x18, r1
shll16 r1
assertreg 0x180000, r1
shll16 r1
assertreg 0, r1
# another:
mov #1, r1
shll16 r1
mov #1, r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
shll r7
cmp/eq r1, r7
bt okay
fail
okay:
set_greg 0xa5a5a5a5, r1
set_greg 0xa5a5a5a5, r7
test_grs_a5a5
pass
exit 0

51
sim/testsuite/sim/sh/shll2.s Normal file
View file

@ -0,0 +1,51 @@
# sh testcase for shll2
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll2:
set_grs_a5a5
mov #1, r1
shll2 r1
assertreg 4, r1
shll2 r1
assertreg 16, r1
shll2 r1
assertreg 64, r1
shll2 r1
assertreg 0x100, r1
shll2 r1
assertreg 0x400, r1
shll2 r1
assertreg 0x1000, r1
shll2 r1
assertreg 0x4000, r1
shll2 r1
assertreg 0x10000, r1
shll2 r1
assertreg 0x40000, r1
shll2 r1
assertreg 0x100000, r1
shll2 r1
assertreg 0x400000, r1
shll2 r1
assertreg 0x1000000, r1
shll2 r1
assertreg 0x4000000, r1
shll2 r1
assertreg 0x10000000, r1
shll2 r1
assertreg 0x40000000, r1
shll2 r1
assertreg 0, r1
set_greg 0xa5a5a5a5, r1
test_grs_a5a5
pass
exit 0

42
sim/testsuite/sim/sh/shll8.s Normal file
View file

@ -0,0 +1,42 @@
# sh testcase for shll8
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shll8:
set_grs_a5a5
mov #1, r1
shll8 r1
assertreg 0x100, r1
shll8 r1
assertreg 0x10000, r1
shll8 r1
assertreg 0x1000000, r1
shll8 r1
assertreg 0, r1
# another:
mov #1, r1
shll8 r1
mov #1, r2
shll r2
shll r2
shll r2
shll r2
shll r2
shll r2
shll r2
shll r2
cmp/eq r1, r2
bt okay
fail
okay:
set_greg 0xa5a5a5a5, r1
set_greg 0xa5a5a5a5, r2
test_grs_a5a5
pass
exit 0

42
sim/testsuite/sim/sh/shlr.s Normal file
View file

@ -0,0 +1,42 @@
# sh testcase for shlr
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shlr:
set_grs_a5a5
mov #0, r0
or #192, r0
shlr r0
assertreg0 96
shlr r0
assertreg0 48
shlr r0
assertreg0 24
shlr r0
assertreg0 12
shlr r0
assertreg0 6
shlr r0
assertreg0 3
# Make sure a bit is shifted into T.
shlr r0
bf wrong
assertreg0 1
# Ditto.
shlr r0
bf wrong
assertreg0 0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
pass
exit 0
wrong:
fail

20
sim/testsuite/sim/sh/shlr16.s Normal file
View file

@ -0,0 +1,20 @@
# sh testcase for shlr16
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shrl16:
set_grs_a5a5
shlr16 r0
assertreg0 0xa5a5
shlr16 r0
assertreg0 0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
pass
exit 0

48
sim/testsuite/sim/sh/shlr2.s Normal file
View file

@ -0,0 +1,48 @@
# sh testcase for shlr2
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shrl2:
set_grs_a5a5
shlr2 r0
assertreg0 0x29696969
shlr2 r0
assertreg0 0x0a5a5a5a
shlr2 r0
assertreg0 0x02969696
shlr2 r0
assertreg0 0x00a5a5a5
shlr2 r0
assertreg0 0x00296969
shlr2 r0
assertreg0 0x000a5a5a
shlr2 r0
assertreg0 0x00029696
shlr2 r0
assertreg0 0x0000a5a5
shlr2 r0
assertreg0 0x00002969
shlr2 r0
assertreg0 0x00000a5a
shlr2 r0
assertreg0 0x00000296
shlr2 r0
assertreg0 0x000000a5
shlr2 r0
assertreg0 0x00000029
shlr2 r0
assertreg0 0x0000000a
shlr2 r0
assertreg0 0x00000002
shlr2 r0
assertreg0 0
set_greg 0xa5a5a5a5 r0
test_grs_a5a5
pass
exit 0

24
sim/testsuite/sim/sh/shlr8.s Normal file
View file

@ -0,0 +1,24 @@
# sh testcase for shlr8
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
shrl8:
set_grs_a5a5
shlr8 r0
assertreg0 0xa5a5a5
shlr8 r0
assertreg0 0xa5a5
shlr8 r0
assertreg0 0xa5
shlr8 r0
assertreg0 0x0
set_greg 0xa5a5a5a5, r0
test_grs_a5a5
pass
exit 0

59
sim/testsuite/sim/sh/swap.s Normal file
View file

@ -0,0 +1,59 @@
# sh testcase for swap
# mach: all
# as(sh): -defsym sim_cpu=0
# as(shdsp): -defsym sim_cpu=1 -dsp
.include "testutils.inc"
start
swapb:
set_grs_a5a5
mov #0x5a, r0
shll8 r0
or #0xa5, r0
assertreg0 0x5aa5
swap.b r0, r1
assertreg 0xa55a, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
swapw:
set_grs_a5a5
mov #0x5a, r0
shll16 r0
or #0xa5, r0
assertreg0 0x5a00a5
swap.w r0, r1
assertreg 0xa5005a, r1
test_gr_a5a5 r2
test_gr_a5a5 r3
test_gr_a5a5 r4
test_gr_a5a5 r5
test_gr_a5a5 r6
test_gr_a5a5 r7
test_gr_a5a5 r8
test_gr_a5a5 r9
test_gr_a5a5 r10
test_gr_a5a5 r11
test_gr_a5a5 r12
test_gr_a5a5 r13
test_gr_a5a5 r14
pass
exit 0

588
sim/testsuite/sim/sh/testutils.inc Normal file
View file

@ -0,0 +1,588 @@
# Support macros for the sh assembly test cases.
.equ no_dsp, 0
.equ yes_dsp, 1
.section .rodata
.align 2
_pass: .string "pass\n"
_fail: .string "fail\n"
_stack: .fill 128, 4, 0
stackt:
.macro push reg
mov.l \reg, @-r15
.endm
.macro pop reg
mov.l @r15+, \reg
.endm
.macro start
.text
.align 1
.global start
start: mov.l stackp, r15
bra main
nop
.align 2
stackp: .long stackt
mpass:
mov #4, r4
mov #1, r5
mov.l ppass, r6
mov #5, r7
trapa #34
rts
nop
mfail:
mov #4, r4
mov #1, r5
mov.l pfail, r6
mov #5, r7
trapa #34
mov #1, r5
mexit:
mov #1, r4
mov #0, r6
mov #0, r7
trapa #34
.align 2
ppass: .long _pass
pfail: .long _fail
mtesta5:
push r0
mov.l a5a5, r0
cmp/eq r1, r0
bf mfail
cmp/eq r2, r0
bf mfail
cmp/eq r3, r0
bf mfail
cmp/eq r4, r0
bf mfail
cmp/eq r5, r0
bf mfail
cmp/eq r6, r0
bf mfail
cmp/eq r7, r0
bf mfail
cmp/eq r8, r0
bf mfail
cmp/eq r9, r0
bf mfail
cmp/eq r10, r0
bf mfail
cmp/eq r11, r0
bf mfail
cmp/eq r12, r0
bf mfail
cmp/eq r13, r0
bf mfail
cmp/eq r14, r0
bf mfail
# restore and check r0
pop r0
cmp/eq r0, r1
bf mfail
# pass
rts
nop
.if (sim_cpu == no_dsp)
mtesta5_fp:
push r0
flds fr0, fpul
sts fpul, r0
push r0
mov.l a5a5, r0
lds r0, fpul
fsts fpul, fr0
fcmp/eq fr1, fr0
bf mfail
fcmp/eq fr2, fr0
bf mfail
fcmp/eq fr3, fr0
bf mfail
fcmp/eq fr4, fr0
bf mfail
fcmp/eq fr5, fr0
bf mfail
fcmp/eq fr6, fr0
bf mfail
fcmp/eq fr7, fr0
bf mfail
fcmp/eq fr8, fr0
bf mfail
fcmp/eq fr9, fr0
bf mfail
fcmp/eq fr10, fr0
bf mfail
fcmp/eq fr11, fr0
bf mfail
fcmp/eq fr12, fr0
bf mfail
fcmp/eq fr13, fr0
bf mfail
fcmp/eq fr14, fr0
bf mfail
fcmp/eq fr15, fr0
bf mfail
# restore and check fr0
pop r0
lds r0, fpul
fsts fpul, fr0
fcmp/eq fr0, fr1
bf mfail
# restore r0 and pass
pop r0
rts
nop
.endif
mseta5:
mov.l a5a5, r0
mov.l a5a5, r1
mov.l a5a5, r2
mov.l a5a5, r3
mov.l a5a5, r4
mov.l a5a5, r5
mov.l a5a5, r6
mov.l a5a5, r7
mov.l a5a5, r8
mov.l a5a5, r9
mov.l a5a5, r10
mov.l a5a5, r11
mov.l a5a5, r12
mov.l a5a5, r13
mov.l a5a5, r14
rts
nop
.if (sim_cpu == no_dsp)
mseta5_fp:
push r0
mov.l a5a5, r0
lds r0, fpul
fsts fpul, fr0
fsts fpul, fr1
fsts fpul, fr2
fsts fpul, fr3
fsts fpul, fr4
fsts fpul, fr5
fsts fpul, fr6
fsts fpul, fr7
fsts fpul, fr8
fsts fpul, fr9
fsts fpul, fr10
fsts fpul, fr11
fsts fpul, fr12
fsts fpul, fr13
fsts fpul, fr14
fsts fpul, fr15
pop r0
rts
nop
.endif
.align 2
a5a5: .long 0xa5a5a5a5
main:
.endm
.macro exit val
mov #\val, r5
bra mexit
nop
.endm
.macro pass
bsr mpass
nop
.endm
.macro fail
bra mfail
nop
.endm
# Assert value of register (any general register but r0)
# Preserves r0 on stack, restores it on success.
.macro assertreg val reg
push r0
mov.l .Larval\@, r0
cmp/eq r0, \reg
bt .Lar\@
fail
.align 2
.Larval\@:
.long \val
.Lar\@: pop r0
.endm
# Assert value of register zero
# Preserves r1 on stack, restores it on success.
.macro assertreg0 val
push r1
mov.l .Lazval\@, r1
cmp/eq r1, r0
bt .Laz\@
fail
.align 2
.Lazval\@:
.long \val
.Laz\@: pop r1
.endm
# Assert value of system register
# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
.macro assert_sreg val reg
push r0
sts \reg, r0
assertreg0 \val
pop r0
.endm
# Assert value of system register that isn't directly stc-able
# [a1, m0, m1, ...]
.macro assert_sreg2 val reg
push r0
sts a0, r0
push r0
pcopy \reg, a0
sts a0, r0
assertreg0 \val
pop r0
lds r0, a0
pop r0
.endm
# Assert value of control register
# [gbr, vbr, ssr, spc, sgr, dbr, r[0-7]_bank, sr, mod, re, rs, ...]
.macro assert_creg val reg
push r0
stc \reg, r0
assertreg0 \val
pop r0
.endm
# Assert integer value of fp register
# Preserves r0 on stack, restores it on success
# Assumes single-precision fp mode
.macro assert_fpreg_i val freg
push r0
ftrc \freg, fpul
sts fpul, r0
assertreg0 \val
pop r0
.endm
# Assert integer value of dp register
# Preserves r0 on stack, restores it on success
# Assumes double-precision fp mode
.macro assert_dpreg_i val dreg
push r0
ftrc \dreg, fpul
sts fpul, r0
assertreg0 \val
pop r0
.endm
# Assert hex value of fp register
# Preserves r0 on stack, restores it on success
# Assumes single-precision fp mode
.macro assert_fpreg_x val freg
push r0
flds \freg, fpul
sts fpul, r0
assertreg0 \val
pop r0
.endm
# Set FP bank 0
# Saves and restores r0 and r1
.macro bank0
push r0
push r1
mov #32, r1
shll16 r1
not r1, r1
sts fpscr, r0
and r1, r0
lds r0, fpscr
pop r1
pop r0
.endm
# Set FP bank 1
.macro bank1
push r0
push r1
mov #32, r1
shll16 r1
sts fpscr, r0
or r1, r0
lds r0, fpscr
pop r1
pop r0
.endm
# Set FP 32-bit xfer
.macro sz_32
push r0
push r1
mov #16, r1
shll16 r1
not r1, r1
sts fpscr, r0
and r1, r0
lds r0, fpscr
pop r1
pop r0
.endm
# Set FP 64-bit xfer
.macro sz_64
push r0
push r1
mov #16, r1
shll16 r1
sts fpscr, r0
or r1, r0
lds r0, fpscr
pop r1
pop r0
.endm
# Set FP single precision
.macro single_prec
push r0
push r1
mov #8, r1
shll16 r1
not r1, r1
sts fpscr, r0
and r1, r0
lds r0, fpscr
pop r1
pop r0
.endm
# Set FP double precision
.macro double_prec
push r0
push r1
mov #8, r1
shll16 r1
sts fpscr, r0
or r1, r0
lds r0, fpscr
pop r1
pop r0
.endm
.macro set_carry
sett
.endm
.macro set_ovf
sett
.endm
.macro clear_carry
clrt
.endm
.macro clear_ovf
clrt
.endm
# sets, clrs
.macro set_grs_a5a5
bsr mseta5
nop
.endm
.macro set_greg val greg
mov.l gregval\@, \greg
bra set_greg\@
nop
.align 2
gregval\@: .long \val
set_greg\@:
.endm
.macro set_fprs_a5a5
bsr mseta5_fp
nop
.endm
.macro test_grs_a5a5
bsr mtesta5
nop
.endm
.macro test_fprs_a5a5
bsr mtesta5_fp
nop
.endm
.macro test_gr_a5a5 reg
assertreg 0xa5a5a5a5 \reg
.endm
.macro test_fpr_a5a5 reg
assert_fpreg_x 0xa5a5a5a5 \reg
.endm
.macro test_gr0_a5a5
assertreg0 0xa5a5a5a5
.endm
# Perform a single to double precision floating point conversion.
# Assumes correct settings of fpscr.
.macro _s2d fpr dpr
flds \fpr, fpul
fcnvsd fpul, \dpr
.endm
# Manipulate the status register
.macro set_sr val
push r0
mov.l .Lsrval\@, r0
ldc r0, sr
pop r0
bra .Lsetsr\@
nop
.align 2
.Lsrval\@:
.long \val
.Lsetsr\@:
.endm
.macro get_sr reg
stc sr, \reg
.endm
.macro test_sr val
push r0
get_sr r0
assertreg0 \val
pop r0
.endm
.macro set_sr_bit
push r0
push r1
get_sr r0
mov.l .Lsrbitval\@, r1
or r1, r0
ldc r0, sr
pop r1
pop r0
bra .Lsrbit\@
nop
.align 2
.Lsrbitval:
.long \val
.Lsrbit:
.endm
.macro test_sr_bit_set val
push r0
push r1
get_sr r0
mov.l .Ltsbsval\@, r1
tst r1, r0
bf .Ltsbs\@
fail
.align 2
.Ltsbsval\@:
.long \val
.Ltsbs\@:
pop r1
pop r0
.endm
.macro test_sr_bit_clear val
push r0
push r1
get_sr r0
mov.l .Ltsbcval\@, r1
not r0, r0
tst r1, r0
bf .Ltsbc\@
fail
.align 2
.Ltsbcval\@:
.long \val
.Ltsbc\@:
pop r1
pop r0
.endm
# Set system registers
.macro set_sreg val reg
# [mach, macl, pr, dsr, a0, x0, x1, y0, y1, ...]
push r0
mov.l .Lssrval\@, r0
lds r0, \reg
pop r0
bra .Lssr\@
nop
.Lssrval\@:
.long \val
.Lssr\@:
.endm
.macro set_sreg2 val reg
# [a1, m0, m1, ...]
push r0
sts a0, r0
push r0
mov.l .Lssr2val\@, r0
lds r0, a0
pcopy a0, \reg
pop r0
lds r0, a0
pop r0
bra .Lssr2_\@
nop
.Lssr2val\@:
.long \val
.Lssr2_\@:
.endm
.macro set_creg val reg
#
push r0
mov.l .Lscrval\@, r0
ldc r0, \reg
pop r0
bra .Lscr\@
nop
.Lscrval\@:
.long \val
.Lscr\@:
.endm
.macro set_dctrue
push r0
sts dsr, r0
or #1, r0
lds r0, dsr
pop r0
.endm
.macro set_dcfalse
push r0
sts dsr, r0
not r0, r0
or #1, r0
not r0, r0
lds r0, dsr
pop r0
.endm