* tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
correctly. Add support for printing TIC80_OPERAND_BITNUM and TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic form. * tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM, CC, SICR, and LICR table entries. (tic80_opcodes): Add and test "nop", "br", "bbo", "bbz", "bcnd", and "brcr" opcodes.
This commit is contained in:
Fred Fish
parent
872dc6f0bc
commit
1f8c8c60a1
3 changed files with 214 additions and 23 deletions
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@ -1,3 +1,16 @@
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start-sanitize-tic80
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Sat Jan 4 19:05:05 1997 Fred Fish <fnf@cygnus.com>
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* tic80-dis.c (print_insn_tic80): Print TIC80_OPERAND_RELATIVE
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correctly. Add support for printing TIC80_OPERAND_BITNUM and
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TIC80_OPERAND_CC, and TIC80_OPERAND_CR operands in symbolic
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form.
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* tic80-opc.c (tic80_operands): Add SSOFF, LSOFF, BITNUM,
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CC, SICR, and LICR table entries.
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(tic80_opcodes): Add and test "nop", "br", "bbo", "bbz",
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"bcnd", and "brcr" opcodes.
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end-sanitize-tic80
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Fri Jan 3 18:32:11 1997 Fred Fish <fnf@cygnus.com>
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* ppc-opc.c (powerpc_operands): Make comment match the
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@ -144,31 +144,123 @@ print_insn_tic80 (memaddr, info)
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}
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else if ((operand -> flags & TIC80_OPERAND_RELATIVE) != 0)
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{
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(*info -> print_address_func) (memaddr + value, info);
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(*info -> print_address_func) (memaddr + 4 * value, info);
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}
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else if ((operand -> flags & TIC80_OPERAND_CC_SZ) != 0)
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else if ((operand -> flags & TIC80_OPERAND_BITNUM) != 0)
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{
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#if 0 /* FIXME */
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if (operand -> bits == 3)
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(*info -> fprintf_func) (info -> stream, "cr%d", value);
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char *syms[30] = {
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"eq.b", "ne.b", "gt.b", "le.b", "lt.b", "ge.b",
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"hi.b", "ls.b", "lo.b", "hs.b", "eq.h", "ne.h",
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"gt.h", "le.h", "lt.h", "ge.h", "hi.h", "ls.h",
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"lo.h", "hs.h", "eq.w", "ne.w", "gt.w", "le.w",
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"lt.w", "ge.w", "hi.w", "ls.w", "lo.w", "hs.w"
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};
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int bitnum = ~value & 0x1F;
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if (bitnum < 30)
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{
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/* Found a value within range */
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(*info -> fprintf_func) (info -> stream, "%s", syms[bitnum]);
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}
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else
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{
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static const char *cbnames[4] = { "lt", "gt", "eq", "so" };
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int cr;
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int cc;
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cr = value >> 2;
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if (cr != 0)
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(*info -> fprintf_func) (info -> stream, "4*cr%d", cr);
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cc = value & 3;
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if (cc != 0)
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{
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if (cr != 0)
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(*info -> fprintf_func) (info -> stream, "+");
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(*info -> fprintf_func) (info -> stream, "%s", cbnames[cc]);
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}
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/* Not in range, just print as bit number */
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(*info -> fprintf_func) (info -> stream, "%ld", bitnum);
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}
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}
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else if ((operand -> flags & TIC80_OPERAND_CC) != 0)
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{
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char *syms[24] = {
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"nev.b", "gt0.b", "eq0.b", "ge0.b", "lt0.b", "ne0.b", "le0.b", "alw.b",
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"nev.h", "gt0.h", "eq0.h", "ge0.h", "lt0.h", "ne0.h", "le0.h", "alw.h",
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"nev.w", "gt0.w", "eq0.w", "ge0.w", "lt0.w", "ne0.w", "le0.w", "alw.w"
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};
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if (value < 24)
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{
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/* Found a value within range */
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(*info -> fprintf_func) (info -> stream, "%s", syms[value]);
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}
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else
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{
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/* Not in range, just print as decimal digit. */
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(*info -> fprintf_func) (info -> stream, "%ld", value);
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}
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}
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else if ((operand -> flags & TIC80_OPERAND_CR) != 0)
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{
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char *tmp;
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switch (value)
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{
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case 0: tmp = "EPC"; break;
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case 1: tmp = "EIP"; break;
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case 2: tmp = "CONFIG"; break;
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case 4: tmp = "INTPEN"; break;
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case 6: tmp = "IE"; break;
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case 8: tmp = "FPST"; break;
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case 0xA: tmp = "PPERROR"; break;
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case 0xD: tmp = "PKTREQ"; break;
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case 0xE: tmp = "TCOUNT"; break;
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case 0xF: tmp = "TSCALE"; break;
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case 0x10: tmp = "FLTOP"; break;
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case 0x11: tmp = "FLTADR"; break;
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case 0x12: tmp = "FLTTAG"; break;
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case 0x13: tmp = "FLTDTL"; break;
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case 0x14: tmp = "FLTDTH"; break;
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case 0x20: tmp = "SYSSTK"; break;
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case 0x21: tmp = "SYSTMP"; break;
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case 0x30: tmp = "MPC"; break;
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case 0x31: tmp = "MIP"; break;
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case 0x33: tmp = "ECOMCNTL"; break;
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case 0x34: tmp = "ANASTAT"; break;
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case 0x39: tmp = "BRK1"; break;
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case 0x3A: tmp = "BRK2"; break;
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case 0x200: tmp = "ITAG0"; break;
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case 0x201: tmp = "ITAG1"; break;
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case 0x202: tmp = "ITAG2"; break;
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case 0x203: tmp = "ITAG3"; break;
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case 0x204: tmp = "ITAG4"; break;
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case 0x205: tmp = "ITAG5"; break;
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case 0x206: tmp = "ITAG6"; break;
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case 0x207: tmp = "ITAG7"; break;
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case 0x208: tmp = "ITAG8"; break;
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case 0x209: tmp = "ITAG9"; break;
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case 0x20A: tmp = "ITAG10"; break;
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case 0x20B: tmp = "ITAG11"; break;
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case 0x20C: tmp = "ITAG12"; break;
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case 0x20D: tmp = "ITAG13"; break;
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case 0x20E: tmp = "ITAG14"; break;
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case 0x20F: tmp = "ITAG15"; break;
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case 0x300: tmp = "ILRU"; break;
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case 0x400: tmp = "DTAG0"; break;
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case 0x401: tmp = "DTAG1"; break;
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case 0x402: tmp = "DTAG2"; break;
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case 0x403: tmp = "DTAG3"; break;
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case 0x404: tmp = "DTAG4"; break;
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case 0x405: tmp = "DTAG5"; break;
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case 0x406: tmp = "DTAG6"; break;
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case 0x407: tmp = "DTAG7"; break;
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case 0x408: tmp = "DTAG8"; break;
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case 0x409: tmp = "DTAG9"; break;
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case 0x40A: tmp = "DTAG10"; break;
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case 0x40B: tmp = "DTAG11"; break;
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case 0x40C: tmp = "DTAG12"; break;
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case 0x40D: tmp = "DTAG13"; break;
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case 0x40E: tmp = "DTAG14"; break;
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case 0x40F: tmp = "DTAG15"; break;
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case 0x500: tmp = "DLRU"; break;
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case 0x4000: tmp = "IN0P"; break;
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case 0x4001: tmp = "IN1P"; break;
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case 0x4002: tmp = "OUTP"; break;
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default: tmp = NULL; break;
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}
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if (tmp != NULL)
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{
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(*info -> fprintf_func) (info -> stream, "%s", tmp);
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}
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else
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{
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(*info -> fprintf_func) (info -> stream, "%#lx", value);
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}
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#endif
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}
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else
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{
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@ -92,6 +92,36 @@ const struct tic80_operand tic80_operands[] =
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#define REG27 (REG22 + 1)
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{ 5, 27, NULL, NULL, TIC80_OPERAND_GPR },
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/* Short signed offset in bits 14-0 */
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#define SSOFF (REG27 + 1)
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{ 15, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
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/* Long signed offset in following 32 bit word */
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#define LSOFF (SSOFF + 1)
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{32, 0, NULL, NULL, TIC80_OPERAND_RELATIVE | TIC80_OPERAND_SIGNED },
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/* BITNUM in bits 31-27 */
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#define BITNUM (LSOFF + 1)
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{ 5, 27, NULL, NULL, TIC80_OPERAND_BITNUM },
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/* Condition code in bits 31-27 */
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#define CC (BITNUM + 1)
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{ 5, 27, NULL, NULL, TIC80_OPERAND_CC },
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/* Control register number in bits 14-0 */
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#define SICR (CC + 1)
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{ 15, 0, NULL, NULL, TIC80_OPERAND_CR },
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/* Control register number in next 32 bit word */
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#define LICR (SICR + 1)
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{ 32, 0, NULL, NULL, TIC80_OPERAND_CR },
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};
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const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
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@ -118,6 +148,23 @@ const int tic80_num_operands = sizeof (tic80_operands)/sizeof(*tic80_operands);
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const struct tic80_opcode tic80_opcodes[] = {
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/* The "nop" instruction is really "rdcr 0,r0". We put it first so that this
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specific bit pattern will get dissembled as a nop rather than an rdcr. The
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mask of all ones ensures that this will happen. */
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{"nop", OP_SI(0x4), ~0, 0, {0} },
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/* The "br" instruction is really "bbz target,r0,31". We put it first so that
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this specific bit pattern will get disassembled as a br rather than bbz. */
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{"br", OP_SI(0x48), 0xFFFF8000, 0, {SSOFF} },
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{"br", OP_LI(0x391), 0xFFFFF000, 0, {LSOFF} },
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{"br", OP_REG(0x390), 0xFFFFF000, 0, {REG0} },
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{"br.a", OP_SI(0x49), 0xFFFF8000, 0, {SSOFF} },
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{"br.a", OP_LI(0x393), 0xFFFFF000, 0, {LSOFF} },
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{"br.a", OP_REG(0x392), 0xFFFFF000, 0, {REG0} },
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/* Signed integer ADD */
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{"add", OP_SI(0x58), MASK_SI, FMT_SI, {SSI, REG22, REG27} },
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@ -158,11 +205,50 @@ const struct tic80_opcode tic80_opcodes[] = {
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{"and.tf", OP_LI(0x325), MASK_LI, FMT_LI, {LUBF, REG22, REG27} },
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{"and.tf", OP_REG(0x324), MASK_REG, FMT_REG, {REG0, REG22, REG27} },
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/* Branch Bit One - nonannulled */
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{"bbo", OP_SI(0x4A), MASK_SI, FMT_SI, {SSOFF, REG22, BITNUM} },
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{"bbo", OP_LI(0x395), MASK_LI, FMT_LI, {LSOFF, REG22, BITNUM} },
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{"bbo", OP_REG(0x394), MASK_REG, FMT_REG, {REG0, REG22, BITNUM} },
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/* Branch Bit One - annulled */
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{"bbo.a", OP_SI(0x4B), MASK_SI, FMT_SI, {SSOFF, REG22, BITNUM} },
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{"bbo.a", OP_LI(0x397), MASK_LI, FMT_LI, {LSOFF, REG22, BITNUM} },
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{"bbo.a", OP_REG(0x396), MASK_REG, FMT_REG, {REG0, REG22, BITNUM} },
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/* Branch Bit Zero - nonannulled */
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{"bbz", OP_SI(0x48), MASK_SI, FMT_SI, {SSOFF, REG22, BITNUM} },
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{"bbz", OP_LI(0x391), MASK_LI, FMT_LI, {LSOFF, REG22, BITNUM} },
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{"bbz", OP_REG(0x390), MASK_REG, FMT_REG, {REG0, REG22, BITNUM} },
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/* Branch Bit Zero - annulled */
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{"bbz.a", OP_SI(0x49), MASK_SI, FMT_SI, {SSOFF, REG22, BITNUM} },
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{"bbz.a", OP_LI(0x393), MASK_LI, FMT_LI, {LSOFF, REG22, BITNUM} },
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{"bbz.a", OP_REG(0x392), MASK_REG, FMT_REG, {REG0, REG22, BITNUM} },
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/* Branch Conditional - nonannulled */
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{"bcnd", OP_SI(0x4C), MASK_SI, FMT_SI, {SSOFF, REG22, CC} },
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{"bcnd", OP_LI(0x399), MASK_LI, FMT_LI, {LSOFF, REG22, CC} },
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{"bcnd", OP_REG(0x398), MASK_REG, FMT_REG, {REG0, REG22, CC} },
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/* Branch Conditional - annulled */
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{"bcnd.a", OP_SI(0x4D), MASK_SI, FMT_SI, {SSOFF, REG22, CC} },
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{"bcnd.a", OP_LI(0x39B), MASK_LI, FMT_LI, {LSOFF, REG22, CC} },
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{"bcnd.a", OP_REG(0x39A), MASK_REG, FMT_REG, {REG0, REG22, CC} },
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/* Branch Control Register */
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{"brcr", OP_SI(0x6), MASK_SI, FMT_SI, {SICR} },
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{"brcr", OP_LI(0x30D), MASK_LI, FMT_LI, {LICR} },
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{"brcr", OP_REG(0x30C), MASK_REG, FMT_REG, {REG0} },
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/* WORK IN PROGRESS BELOW THIS POINT */
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{"brcr", OP_LI(0x30D), MASK_LI, FMT_LI, FIXME},
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{"brcr", OP_REG(0x30C), MASK_REG, FMT_REG, FIXME},
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{"brcr", OP_SI(0x6), MASK_SI, FMT_SI, FIXME},
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{"cmnd", OP_LI(0x305), MASK_LI, FMT_LI, FIXME},
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{"cmnd", OP_REG(0x304), MASK_REG, FMT_REG, FIXME},
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{"cmnd", OP_SI(0x2), MASK_SI, FMT_SI, FIXME},
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