x86: make code size vs CPU arch checking consistent
While update_code_flag() checks for LM / i386, set_cpu_arch() so far didn't, allowing e.g. 64-bit code to be emitted after ".arch generic32". Oddly enough a few of our testcases actually exhibit bad behavior (and hence need minor adjustments).
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8 changed files with 25 additions and 6 deletions
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@ -2928,6 +2928,24 @@ set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
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{
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check_cpu_arch_compatible (string, cpu_arch[j].enable);
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if (flag_code == CODE_64BIT && !cpu_arch[j].enable.bitfield.cpulm )
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{
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as_bad (_("64bit mode not supported on `%s'."),
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cpu_arch[j].name);
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(void) restore_line_pointer (e);
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ignore_rest_of_line ();
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return;
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}
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if (flag_code == CODE_32BIT && !cpu_arch[j].enable.bitfield.cpui386)
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{
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as_bad (_("32bit mode not supported on `%s'."),
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cpu_arch[j].name);
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(void) restore_line_pointer (e);
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ignore_rest_of_line ();
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return;
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}
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cpu_arch_name = cpu_arch[j].name;
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free (cpu_sub_arch_name);
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cpu_sub_arch_name = NULL;
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@ -1,9 +1,9 @@
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# Check 287-only instructions.
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.text
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.code16
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.arch i286
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.arch .287
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.code16
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_8087:
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fnsetpm
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frstpm
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@ -1,9 +1,9 @@
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# Check 8087-only instructions.
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.text
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.code16
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.arch i8086
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.arch .8087
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.code16
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_8087:
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fdisi
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feni
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@ -1,8 +1,8 @@
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.text
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.att_syntax noprefix
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.arch i286
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.code16
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.arch i286
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mov eax, ax ; add al, (bx,si)
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mov rax, ax ; add al, (bx,si)
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mov axl, ax ; add al, (bx,si)
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@ -3,8 +3,8 @@
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mov eax, tmm1
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.arch i286
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.code16
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.arch i286
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mov ax, eax ; add [bx+si], al
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mov ax, rax ; add [bx+si], al
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mov ax, axl ; add [bx+si], al
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@ -10,7 +10,7 @@ GAS LISTING .*
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[ ]*1[ ]+\.text
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[ ]*2[ ]+\.arch i186; \.code16
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[ ]*2[ ]+\.code16; \.arch i186
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[ ]*3[ ]+vmovapd %xmm0,%xmm1
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[ ]*4[ ]+vaddsd %xmm4, %xmm5, %xmm6\{%k7\}
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[ ]*5[ ]+vfrczpd %xmm7,%xmm7
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@ -1,5 +1,5 @@
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.text
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.arch i186; .code16
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.code16; .arch i186
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vmovapd %xmm0,%xmm1
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vaddsd %xmm4, %xmm5, %xmm6{%k7}
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vfrczpd %xmm7,%xmm7
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@ -1,4 +1,5 @@
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.text
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.code32
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.arch i386
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i386:
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movsbl %al,%esi
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