Add support for AVX512BW instructions and their AVX512VL versions.
gas/ * config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS. * doc/c-i386.texi: Document avx512bw/.avx512bw. gas/testsuite/ * gas/i386/avx512bw-intel.d: New. * gas/i386/avx512bw-opts-intel.d: New. * gas/i386/avx512bw-opts.d: New. * gas/i386/avx512bw-opts.s: New. * gas/i386/avx512bw-wig.s: New. * gas/i386/avx512bw-wig1-intel.d: New. * gas/i386/avx512bw-wig1.d: New. * gas/i386/avx512bw.d: New. * gas/i386/avx512bw.s: New. * gas/i386/avx512bw_vl-intel.d: New. * gas/i386/avx512bw_vl-opts-intel.d: New. * gas/i386/avx512bw_vl-opts.d: New. * gas/i386/avx512bw_vl-opts.s: New. * gas/i386/avx512bw_vl-wig.s: New. * gas/i386/avx512bw_vl-wig1-intel.d: New. * gas/i386/avx512bw_vl-wig1.d: New. * gas/i386/avx512bw_vl.d: New. * gas/i386/avx512bw_vl.s: New. * gas/i386/i386.exp: Run new AVX-512 tests. * gas/i386/x86-64-avx512bw-intel.d: New. * gas/i386/x86-64-avx512bw-opts-intel.d: New. * gas/i386/x86-64-avx512bw-opts.d: New. * gas/i386/x86-64-avx512bw-opts.s: New. * gas/i386/x86-64-avx512bw-wig.s: New. * gas/i386/x86-64-avx512bw-wig1-intel.d: New. * gas/i386/x86-64-avx512bw-wig1.d: New. * gas/i386/x86-64-avx512bw.d: New. * gas/i386/x86-64-avx512bw.s: New. * gas/i386/x86-64-avx512bw_vl-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts-intel.d: New. * gas/i386/x86-64-avx512bw_vl-opts.d: New. * gas/i386/x86-64-avx512bw_vl-opts.s: New. * gas/i386/x86-64-avx512bw_vl-wig.s: New. * gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New. * gas/i386/x86-64-avx512bw_vl-wig1.d: New. * gas/i386/x86-64-avx512bw_vl.d: New. * gas/i386/x86-64-avx512bw_vl.s: New. opcodes/ * i386-dis-evex.h: Add new instructions (prefixes bellow). * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE. (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71. (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63, PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68, PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE, PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1, PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D, PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830, PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A, PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42. (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0, VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0, VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0. (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3, EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2, EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2, EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2. (prefix_table): Add entries for new instructions. (vex_table) : Ditto. (vex_len_table): Ditto. (vex_w_table): Ditto. (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode handling. (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode handling. (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling. (OP_EX): Add dqw_swap_mode handling. (OP_VEX): Add mask_bd_mode handling. (OP_Mask): Add mask_bd_mode handling. * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS. (cpu_flags): Add CpuAVX512BW. * i386-init.h: Regenerated. * i386-opc.h (CpuAVX512BW): New. (i386_cpu_flags): Add cpuavx512bw. * i386-opc.tbl: Add AVX512BW instructions. * i386-tbl.h: Regenerate.
This commit is contained in:
Ilya Tocar
H.J. Lu
parent
99282af656
commit
1ba585e8f4
49 changed files with 57825 additions and 5278 deletions
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@ -1,3 +1,17 @@
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2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Sergey Lega <sergey.s.lega@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* config/tc-i386.c (cpu_arch): Add .avx512bw, CPU_AVX512BW_FLAGS.
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* doc/c-i386.texi: Document avx512bw/.avx512bw.
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2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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@ -916,6 +916,8 @@ static const arch_entry cpu_arch[] =
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CPU_PREFETCHWT1_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".se1"), PROCESSOR_UNKNOWN,
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CPU_SE1_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".avx512bw"), PROCESSOR_UNKNOWN,
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CPU_AVX512BW_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".avx512vl"), PROCESSOR_UNKNOWN,
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CPU_AVX512VL_FLAGS, 0, 0 },
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};
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@ -188,6 +188,7 @@ accept various extension mnemonics. For example,
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@code{svme},
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@code{abm} and
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@code{padlock}.
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@code{avx512bw},
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@code{avx512vl},
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Note that rather than extending a basic instruction set, the extension
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mnemonics starting with @code{no} revoke the respective functionality.
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@ -1071,7 +1072,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.smap} @tab @samp{.sha}
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@item @samp{.smap} @tab @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves}
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@item @samp{.smap} @tab @samp{.prefetchwt1}
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@item @samp{.smap} @tab @samp{.avx512vl}
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@item @samp{.smap} @tab @samp{.avx512vl} @tab @samp{.avx512bw}
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@item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
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@item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
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@item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
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@ -1,3 +1,52 @@
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2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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Sergey Lega <sergey.s.lega@intel.com>
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Anna Tikhonova <anna.tikhonova@intel.com>
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Ilya Tocar <ilya.tocar@intel.com>
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Andrey Turetskiy <andrey.turetskiy@intel.com>
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Ilya Verbin <ilya.verbin@intel.com>
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Kirill Yukhin <kirill.yukhin@intel.com>
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Michael Zolotukhin <michael.v.zolotukhin@intel.com>
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* gas/i386/avx512bw-intel.d: New.
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* gas/i386/avx512bw-opts-intel.d: New.
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* gas/i386/avx512bw-opts.d: New.
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* gas/i386/avx512bw-opts.s: New.
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* gas/i386/avx512bw-wig.s: New.
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* gas/i386/avx512bw-wig1-intel.d: New.
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* gas/i386/avx512bw-wig1.d: New.
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* gas/i386/avx512bw.d: New.
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* gas/i386/avx512bw.s: New.
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* gas/i386/avx512bw_vl-intel.d: New.
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* gas/i386/avx512bw_vl-opts-intel.d: New.
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* gas/i386/avx512bw_vl-opts.d: New.
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* gas/i386/avx512bw_vl-opts.s: New.
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* gas/i386/avx512bw_vl-wig.s: New.
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* gas/i386/avx512bw_vl-wig1-intel.d: New.
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* gas/i386/avx512bw_vl-wig1.d: New.
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* gas/i386/avx512bw_vl.d: New.
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* gas/i386/avx512bw_vl.s: New.
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* gas/i386/i386.exp: Run new AVX-512 tests.
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* gas/i386/x86-64-avx512bw-intel.d: New.
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* gas/i386/x86-64-avx512bw-opts-intel.d: New.
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* gas/i386/x86-64-avx512bw-opts.d: New.
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* gas/i386/x86-64-avx512bw-opts.s: New.
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* gas/i386/x86-64-avx512bw-wig.s: New.
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* gas/i386/x86-64-avx512bw-wig1-intel.d: New.
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* gas/i386/x86-64-avx512bw-wig1.d: New.
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* gas/i386/x86-64-avx512bw.d: New.
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* gas/i386/x86-64-avx512bw.s: New.
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* gas/i386/x86-64-avx512bw_vl-intel.d: New.
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* gas/i386/x86-64-avx512bw_vl-opts-intel.d: New.
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* gas/i386/x86-64-avx512bw_vl-opts.d: New.
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* gas/i386/x86-64-avx512bw_vl-opts.s: New.
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* gas/i386/x86-64-avx512bw_vl-wig.s: New.
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* gas/i386/x86-64-avx512bw_vl-wig1-intel.d: New.
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* gas/i386/x86-64-avx512bw_vl-wig1.d: New.
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* gas/i386/x86-64-avx512bw_vl.d: New.
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* gas/i386/x86-64-avx512bw_vl.s: New.
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2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
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Alexander Ivchenko <alexander.ivchenko@intel.com>
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Maxim Kuznetsov <maxim.kuznetsov@intel.com>
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1602
gas/testsuite/gas/i386/avx512bw-intel.d
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1602
gas/testsuite/gas/i386/avx512bw-intel.d
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File diff suppressed because it is too large
Load diff
60
gas/testsuite/gas/i386/avx512bw-opts-intel.d
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60
gas/testsuite/gas/i386/avx512bw-opts-intel.d
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@ -0,0 +1,60 @@
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#as:
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#objdump: -dw -Mintel -Msuffix
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#name: i386 AVX512BW opts insns (Intel disassembly)
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#source: avx512bw-opts.s
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.*: +file format .*
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Disassembly of section \.text:
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00000000 <_start>:
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|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 7f ee[ ]*vmovdqu16\.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 6f f5[ ]*vmovdqu16 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 7f ee[ ]*vmovdqu16\.s zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 6f f5[ ]*vmovdqu16 zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 7f ee[ ]*vmovdqu16\.s zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 6f f5[ ]*vmovdqu16 zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 7f ee[ ]*vmovdqu16\.s zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 6f f5[ ]*vmovdqu16 zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 7f ee[ ]*vmovdqu16\.s zmm6\{k7\}\{z\},zmm5
|
||||
#pass
|
||||
60
gas/testsuite/gas/i386/avx512bw-opts.d
Normal file
60
gas/testsuite/gas/i386/avx512bw-opts.d
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
#as:
|
||||
#objdump: -dw -Msuffix
|
||||
#name: i386 AVX512BW opts insns
|
||||
#source: avx512bw-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 6f f5[ ]*vmovdqu8 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 6f f5[ ]*vmovdqu8 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 6f f5[ ]*vmovdqu16 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 6f f5[ ]*vmovdqu16 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 6f f5[ ]*vmovdqu8 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 6f f5[ ]*vmovdqu8 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 48 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 6f f5[ ]*vmovdqu8 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f cf 7f ee[ ]*vmovdqu8\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 6f f5[ ]*vmovdqu16 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 6f f5[ ]*vmovdqu16 %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 6f f5[ ]*vmovdqu16 %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 7f ee[ ]*vmovdqu16\.s %zmm5,%zmm6\{%k7\}\{z\}
|
||||
#pass
|
||||
55
gas/testsuite/gas/i386/avx512bw-opts.s
Normal file
55
gas/testsuite/gas/i386/avx512bw-opts.s
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
# Check 32bit AVX512BW swap instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vmovdqu8 %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu8.s %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu8 %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu8.s %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu8 %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vmovdqu8.s %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vmovdqu8 %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu8.s %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu8 %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu8.s %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu8 %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vmovdqu8.s %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vmovdqu16 %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu16.s %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu16 %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu16.s %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu16 %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vmovdqu16.s %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vmovdqu16 %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu16.s %zmm5, %zmm6 # AVX512BW
|
||||
vmovdqu16 %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu16.s %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vmovdqu16 %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vmovdqu16.s %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
|
||||
.intel_syntax noprefix
|
||||
vmovdqu8 zmm6, zmm5 # AVX512BW
|
||||
vmovdqu8.s zmm6, zmm5 # AVX512BW
|
||||
vmovdqu8 zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu8.s zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu8 zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vmovdqu8.s zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vmovdqu8 zmm6, zmm5 # AVX512BW
|
||||
vmovdqu8.s zmm6, zmm5 # AVX512BW
|
||||
vmovdqu8 zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu8.s zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu8 zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vmovdqu8.s zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vmovdqu16 zmm6, zmm5 # AVX512BW
|
||||
vmovdqu16.s zmm6, zmm5 # AVX512BW
|
||||
vmovdqu16 zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu16.s zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu16 zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vmovdqu16.s zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vmovdqu16 zmm6, zmm5 # AVX512BW
|
||||
vmovdqu16.s zmm6, zmm5 # AVX512BW
|
||||
vmovdqu16 zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu16.s zmm6{k7}, zmm5 # AVX512BW
|
||||
vmovdqu16 zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vmovdqu16.s zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
983
gas/testsuite/gas/i386/avx512bw-wig.s
Normal file
983
gas/testsuite/gas/i386/avx512bw-wig.s
Normal file
|
|
@ -0,0 +1,983 @@
|
|||
# Check 32bit AVX512BW WIG instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpabsb %zmm5, %zmm6 # AVX512BW
|
||||
vpabsb %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpabsb %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpabsb (%ecx), %zmm6 # AVX512BW
|
||||
vpabsb -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpabsb 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpabsb 8192(%edx), %zmm6 # AVX512BW
|
||||
vpabsb -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpabsb -8256(%edx), %zmm6 # AVX512BW
|
||||
vpabsw %zmm5, %zmm6 # AVX512BW
|
||||
vpabsw %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpabsw %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpabsw (%ecx), %zmm6 # AVX512BW
|
||||
vpabsw -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpabsw 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpabsw 8192(%edx), %zmm6 # AVX512BW
|
||||
vpabsw -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpabsw -8256(%edx), %zmm6 # AVX512BW
|
||||
vpacksswb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpacksswb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpacksswb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpacksswb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpacksswb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpacksswb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpacksswb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpacksswb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpacksswb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpackuswb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpackuswb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpackuswb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpackuswb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpackuswb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpackuswb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpackuswb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpackuswb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpackuswb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpaddb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpaddb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpaddb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpaddsb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpaddsb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddsb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddsb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpaddsw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpaddsw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddsw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddsw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddsw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpaddusb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpaddusb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddusb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddusb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpaddusw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpaddusw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddusw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddusw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddusw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpaddw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpaddw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpaddw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpaddw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpaddw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpalignr $0xab, %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpalignr $0xab, %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpalignr $0xab, %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpalignr $123, %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpalignr $123, (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpalignr $123, -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpalignr $123, 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpalignr $123, 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpalignr $123, -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpalignr $123, -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpavgb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpavgb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpavgb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpavgb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpavgb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpavgw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpavgw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpavgw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpavgw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpavgw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpavgw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpcmpeqb %zmm5, %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqb %zmm5, %zmm6, %k5{%k7} # AVX512BW
|
||||
vpcmpeqb (%ecx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqb -123456(%esp,%esi,8), %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqb 8128(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpeqb 8192(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqb -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpeqb -8256(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqw %zmm5, %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqw %zmm5, %zmm6, %k5{%k7} # AVX512BW
|
||||
vpcmpeqw (%ecx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqw -123456(%esp,%esi,8), %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqw 8128(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpeqw 8192(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpeqw -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpeqw -8256(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtb %zmm5, %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtb %zmm5, %zmm6, %k5{%k7} # AVX512BW
|
||||
vpcmpgtb (%ecx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtb -123456(%esp,%esi,8), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtb 8128(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpgtb 8192(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtb -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpgtb -8256(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtw %zmm5, %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtw %zmm5, %zmm6, %k5{%k7} # AVX512BW
|
||||
vpcmpgtw (%ecx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtw -123456(%esp,%esi,8), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtw 8128(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpgtw 8192(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpcmpgtw -8192(%edx), %zmm6, %k5 # AVX512BW Disp8
|
||||
vpcmpgtw -8256(%edx), %zmm6, %k5 # AVX512BW
|
||||
vpmaddubsw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddubsw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmaddubsw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmaddubsw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddubsw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddubsw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaddubsw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddubsw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaddubsw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddwd %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddwd %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmaddwd %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmaddwd (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddwd -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddwd 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaddwd 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaddwd -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaddwd -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmaxsb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmaxsb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxsb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxsb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmaxsw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmaxsw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxsw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxsw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxsw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxub %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxub %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmaxub %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmaxub (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxub -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxub 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxub 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxub -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxub -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxuw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxuw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmaxuw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmaxuw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxuw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxuw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxuw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmaxuw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmaxuw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpminsb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpminsb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpminsb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminsb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminsb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpminsw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpminsw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpminsw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminsw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminsw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminsw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminub %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpminub %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpminub %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpminub (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminub -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpminub 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminub 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminub -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminub -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminuw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpminuw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpminuw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpminuw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminuw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpminuw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminuw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpminuw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpminuw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmovsxbw %ymm5, %zmm6{%k7} # AVX512BW
|
||||
vpmovsxbw %ymm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmovsxbw (%ecx), %zmm6{%k7} # AVX512BW
|
||||
vpmovsxbw -123456(%esp,%esi,8), %zmm6{%k7} # AVX512BW
|
||||
vpmovsxbw 4064(%edx), %zmm6{%k7} # AVX512BW Disp8
|
||||
vpmovsxbw 4096(%edx), %zmm6{%k7} # AVX512BW
|
||||
vpmovsxbw -4096(%edx), %zmm6{%k7} # AVX512BW Disp8
|
||||
vpmovsxbw -4128(%edx), %zmm6{%k7} # AVX512BW
|
||||
vpmovzxbw %ymm5, %zmm6{%k7} # AVX512BW
|
||||
vpmovzxbw %ymm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmovzxbw (%ecx), %zmm6{%k7} # AVX512BW
|
||||
vpmovzxbw -123456(%esp,%esi,8), %zmm6{%k7} # AVX512BW
|
||||
vpmovzxbw 4064(%edx), %zmm6{%k7} # AVX512BW Disp8
|
||||
vpmovzxbw 4096(%edx), %zmm6{%k7} # AVX512BW
|
||||
vpmovzxbw -4096(%edx), %zmm6{%k7} # AVX512BW Disp8
|
||||
vpmovzxbw -4128(%edx), %zmm6{%k7} # AVX512BW
|
||||
vpmulhrsw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhrsw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmulhrsw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmulhrsw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhrsw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhrsw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmulhrsw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhrsw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmulhrsw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhuw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhuw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmulhuw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmulhuw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhuw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhuw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmulhuw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhuw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmulhuw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmulhw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmulhw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmulhw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmulhw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmulhw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmullw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpmullw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpmullw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpmullw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmullw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpmullw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmullw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpmullw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpmullw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsadbw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpsadbw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsadbw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpsadbw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsadbw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsadbw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsadbw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpshufb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpshufb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpshufb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpshufb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpshufb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpshufb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpshufb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpshufb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpshufb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpshufhw $0xab, %zmm5, %zmm6 # AVX512BW
|
||||
vpshufhw $0xab, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpshufhw $0xab, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpshufhw $123, %zmm5, %zmm6 # AVX512BW
|
||||
vpshufhw $123, (%ecx), %zmm6 # AVX512BW
|
||||
vpshufhw $123, -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpshufhw $123, 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpshufhw $123, 8192(%edx), %zmm6 # AVX512BW
|
||||
vpshufhw $123, -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpshufhw $123, -8256(%edx), %zmm6 # AVX512BW
|
||||
vpshuflw $0xab, %zmm5, %zmm6 # AVX512BW
|
||||
vpshuflw $0xab, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpshuflw $0xab, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpshuflw $123, %zmm5, %zmm6 # AVX512BW
|
||||
vpshuflw $123, (%ecx), %zmm6 # AVX512BW
|
||||
vpshuflw $123, -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpshuflw $123, 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpshuflw $123, 8192(%edx), %zmm6 # AVX512BW
|
||||
vpshuflw $123, -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpshuflw $123, -8256(%edx), %zmm6 # AVX512BW
|
||||
vpsllw %xmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsllw %xmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsllw (%ecx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsllw -123456(%esp,%esi,8), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsllw 2032(%edx), %zmm5, %zmm6{%k7} # AVX512BW Disp8
|
||||
vpsllw 2048(%edx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsllw -2048(%edx), %zmm5, %zmm6{%k7} # AVX512BW Disp8
|
||||
vpsllw -2064(%edx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsraw %xmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsraw %xmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsraw (%ecx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsraw -123456(%esp,%esi,8), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsraw 2032(%edx), %zmm5, %zmm6{%k7} # AVX512BW Disp8
|
||||
vpsraw 2048(%edx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsraw -2048(%edx), %zmm5, %zmm6{%k7} # AVX512BW Disp8
|
||||
vpsraw -2064(%edx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsrlw %xmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsrlw %xmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsrlw (%ecx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsrlw -123456(%esp,%esi,8), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsrlw 2032(%edx), %zmm5, %zmm6{%k7} # AVX512BW Disp8
|
||||
vpsrlw 2048(%edx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsrlw -2048(%edx), %zmm5, %zmm6{%k7} # AVX512BW Disp8
|
||||
vpsrlw -2064(%edx), %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsrldq $0xab, %zmm5, %zmm6 # AVX512BW
|
||||
vpsrldq $123, %zmm5, %zmm6 # AVX512BW
|
||||
vpsrldq $123, (%ecx), %zmm6 # AVX512BW
|
||||
vpsrldq $123, -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpsrldq $123, 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsrldq $123, 8192(%edx), %zmm6 # AVX512BW
|
||||
vpsrldq $123, -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsrldq $123, -8256(%edx), %zmm6 # AVX512BW
|
||||
vpsrlw $0xab, %zmm5, %zmm6 # AVX512BW
|
||||
vpsrlw $0xab, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsrlw $0xab, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsrlw $123, %zmm5, %zmm6 # AVX512BW
|
||||
vpsrlw $123, (%ecx), %zmm6 # AVX512BW
|
||||
vpsrlw $123, -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpsrlw $123, 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsrlw $123, 8192(%edx), %zmm6 # AVX512BW
|
||||
vpsrlw $123, -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsrlw $123, -8256(%edx), %zmm6 # AVX512BW
|
||||
vpsraw $0xab, %zmm5, %zmm6 # AVX512BW
|
||||
vpsraw $0xab, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsraw $0xab, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsraw $123, %zmm5, %zmm6 # AVX512BW
|
||||
vpsraw $123, (%ecx), %zmm6 # AVX512BW
|
||||
vpsraw $123, -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpsraw $123, 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsraw $123, 8192(%edx), %zmm6 # AVX512BW
|
||||
vpsraw $123, -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsraw $123, -8256(%edx), %zmm6 # AVX512BW
|
||||
vpsubb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpsubb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsubb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsubb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsubsb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsubsb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubsb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubsb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsubsw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsubsw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubsw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubsw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubsw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusb %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusb %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsubusb %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsubusb (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusb -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusb 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubusb 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusb -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubusb -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsubusw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsubusw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubusw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubusw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubusw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpsubw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsubw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsubw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpsubw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpsubw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhbw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhbw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpunpckhbw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpunpckhbw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhbw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhbw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpckhbw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhbw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpckhbw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhwd %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhwd %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpunpckhwd %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpunpckhwd (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhwd -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhwd 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpckhwd 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpckhwd -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpckhwd -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklbw %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklbw %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpunpcklbw %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpunpcklbw (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklbw -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklbw 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpcklbw 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklbw -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpcklbw -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklwd %zmm4, %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklwd %zmm4, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpunpcklwd %zmm4, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpunpcklwd (%ecx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklwd -123456(%esp,%esi,8), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklwd 8128(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpcklwd 8192(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpunpcklwd -8192(%edx), %zmm5, %zmm6 # AVX512BW Disp8
|
||||
vpunpcklwd -8256(%edx), %zmm5, %zmm6 # AVX512BW
|
||||
vpslldq $0xab, %zmm5, %zmm6 # AVX512BW
|
||||
vpslldq $123, %zmm5, %zmm6 # AVX512BW
|
||||
vpslldq $123, (%ecx), %zmm6 # AVX512BW
|
||||
vpslldq $123, -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpslldq $123, 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpslldq $123, 8192(%edx), %zmm6 # AVX512BW
|
||||
vpslldq $123, -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpslldq $123, -8256(%edx), %zmm6 # AVX512BW
|
||||
vpsllw $0xab, %zmm5, %zmm6 # AVX512BW
|
||||
vpsllw $0xab, %zmm5, %zmm6{%k7} # AVX512BW
|
||||
vpsllw $0xab, %zmm5, %zmm6{%k7}{z} # AVX512BW
|
||||
vpsllw $123, %zmm5, %zmm6 # AVX512BW
|
||||
vpsllw $123, (%ecx), %zmm6 # AVX512BW
|
||||
vpsllw $123, -123456(%esp,%esi,8), %zmm6 # AVX512BW
|
||||
vpsllw $123, 8128(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsllw $123, 8192(%edx), %zmm6 # AVX512BW
|
||||
vpsllw $123, -8192(%edx), %zmm6 # AVX512BW Disp8
|
||||
vpsllw $123, -8256(%edx), %zmm6 # AVX512BW
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpabsb zmm6, zmm5 # AVX512BW
|
||||
vpabsb zmm6{k7}, zmm5 # AVX512BW
|
||||
vpabsb zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vpabsb zmm6, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpabsb zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpabsb zmm6, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpabsb zmm6, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpabsb zmm6, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpabsb zmm6, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpabsw zmm6, zmm5 # AVX512BW
|
||||
vpabsw zmm6{k7}, zmm5 # AVX512BW
|
||||
vpabsw zmm6{k7}{z}, zmm5 # AVX512BW
|
||||
vpabsw zmm6, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpabsw zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpabsw zmm6, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpabsw zmm6, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpabsw zmm6, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpabsw zmm6, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpacksswb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpacksswb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpacksswb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpacksswb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpacksswb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpacksswb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpacksswb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpacksswb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpacksswb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpackuswb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpackuswb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpackuswb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpackuswb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpackuswb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpackuswb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpackuswb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpackuswb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpackuswb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpaddb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpaddb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpaddb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpaddb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpaddb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpaddb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpaddb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpaddb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpaddb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpaddsb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpaddsb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpaddsb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpaddsb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpaddsb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpaddsb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpaddsb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpaddsb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpaddsb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpaddsw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpaddsw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpaddsw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpaddsw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpaddsw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpaddsw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpaddsw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpaddsw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpaddsw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpaddusb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpaddusb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpaddusb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpaddusb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpaddusb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpaddusb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpaddusb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpaddusb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpaddusb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpaddusw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpaddusw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpaddusw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpaddusw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpaddusw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpaddusw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpaddusw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpaddusw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpaddusw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpaddw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpaddw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpaddw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpaddw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpaddw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpaddw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpaddw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpaddw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpaddw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpalignr zmm6, zmm5, zmm4, 0xab # AVX512BW
|
||||
vpalignr zmm6{k7}, zmm5, zmm4, 0xab # AVX512BW
|
||||
vpalignr zmm6{k7}{z}, zmm5, zmm4, 0xab # AVX512BW
|
||||
vpalignr zmm6, zmm5, zmm4, 123 # AVX512BW
|
||||
vpalignr zmm6, zmm5, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpalignr zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpalignr zmm6, zmm5, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpalignr zmm6, zmm5, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpalignr zmm6, zmm5, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpalignr zmm6, zmm5, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
vpavgb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpavgb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpavgb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpavgb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpavgb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpavgb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpavgb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpavgb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpavgb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpavgw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpavgw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpavgw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpavgw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpavgw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpavgw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpavgw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpavgw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpavgw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpcmpeqb k5, zmm6, zmm5 # AVX512BW
|
||||
vpcmpeqb k5{k7}, zmm6, zmm5 # AVX512BW
|
||||
vpcmpeqb k5, zmm6, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpcmpeqb k5, zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpcmpeqb k5, zmm6, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpcmpeqb k5, zmm6, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpcmpeqb k5, zmm6, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpcmpeqb k5, zmm6, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpcmpeqw k5, zmm6, zmm5 # AVX512BW
|
||||
vpcmpeqw k5{k7}, zmm6, zmm5 # AVX512BW
|
||||
vpcmpeqw k5, zmm6, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpcmpeqw k5, zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpcmpeqw k5, zmm6, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpcmpeqw k5, zmm6, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpcmpeqw k5, zmm6, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpcmpeqw k5, zmm6, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpcmpgtb k5, zmm6, zmm5 # AVX512BW
|
||||
vpcmpgtb k5{k7}, zmm6, zmm5 # AVX512BW
|
||||
vpcmpgtb k5, zmm6, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpcmpgtb k5, zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpcmpgtb k5, zmm6, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpcmpgtb k5, zmm6, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpcmpgtb k5, zmm6, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpcmpgtb k5, zmm6, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpcmpgtw k5, zmm6, zmm5 # AVX512BW
|
||||
vpcmpgtw k5{k7}, zmm6, zmm5 # AVX512BW
|
||||
vpcmpgtw k5, zmm6, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpcmpgtw k5, zmm6, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpcmpgtw k5, zmm6, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpcmpgtw k5, zmm6, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpcmpgtw k5, zmm6, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpcmpgtw k5, zmm6, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmaddubsw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmaddubsw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmaddubsw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmaddubsw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmaddubsw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmaddubsw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmaddubsw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmaddubsw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmaddubsw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmaddwd zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmaddwd zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmaddwd zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmaddwd zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmaddwd zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmaddwd zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmaddwd zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmaddwd zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmaddwd zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmaxsb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmaxsb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxsb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxsb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmaxsb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmaxsb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmaxsb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmaxsb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmaxsb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmaxsw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmaxsw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxsw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxsw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmaxsw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmaxsw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmaxsw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmaxsw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmaxsw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmaxub zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmaxub zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxub zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxub zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmaxub zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmaxub zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmaxub zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmaxub zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmaxub zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmaxuw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmaxuw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxuw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmaxuw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmaxuw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmaxuw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmaxuw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmaxuw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmaxuw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpminsb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpminsb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpminsb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpminsb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpminsb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpminsb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpminsb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpminsb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpminsb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpminsw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpminsw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpminsw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpminsw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpminsw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpminsw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpminsw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpminsw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpminsw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpminub zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpminub zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpminub zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpminub zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpminub zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpminub zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpminub zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpminub zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpminub zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpminuw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpminuw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpminuw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpminuw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpminuw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpminuw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpminuw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpminuw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpminuw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmovsxbw zmm6{k7}, ymm5 # AVX512BW
|
||||
vpmovsxbw zmm6{k7}{z}, ymm5 # AVX512BW
|
||||
vpmovsxbw zmm6{k7}, YMMWORD PTR [ecx] # AVX512BW
|
||||
vpmovsxbw zmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmovsxbw zmm6{k7}, YMMWORD PTR [edx+4064] # AVX512BW Disp8
|
||||
vpmovsxbw zmm6{k7}, YMMWORD PTR [edx+4096] # AVX512BW
|
||||
vpmovsxbw zmm6{k7}, YMMWORD PTR [edx-4096] # AVX512BW Disp8
|
||||
vpmovsxbw zmm6{k7}, YMMWORD PTR [edx-4128] # AVX512BW
|
||||
vpmovzxbw zmm6{k7}, ymm5 # AVX512BW
|
||||
vpmovzxbw zmm6{k7}{z}, ymm5 # AVX512BW
|
||||
vpmovzxbw zmm6{k7}, YMMWORD PTR [ecx] # AVX512BW
|
||||
vpmovzxbw zmm6{k7}, YMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmovzxbw zmm6{k7}, YMMWORD PTR [edx+4064] # AVX512BW Disp8
|
||||
vpmovzxbw zmm6{k7}, YMMWORD PTR [edx+4096] # AVX512BW
|
||||
vpmovzxbw zmm6{k7}, YMMWORD PTR [edx-4096] # AVX512BW Disp8
|
||||
vpmovzxbw zmm6{k7}, YMMWORD PTR [edx-4128] # AVX512BW
|
||||
vpmulhrsw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmulhrsw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmulhrsw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmulhrsw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmulhrsw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmulhrsw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmulhrsw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmulhrsw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmulhrsw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmulhuw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmulhuw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmulhuw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmulhuw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmulhuw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmulhuw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmulhuw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmulhuw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmulhuw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmulhw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmulhw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmulhw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmulhw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmulhw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmulhw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmulhw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmulhw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmulhw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpmullw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpmullw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpmullw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpmullw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpmullw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpmullw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpmullw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpmullw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpmullw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpsadbw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpsadbw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpsadbw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsadbw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpsadbw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpsadbw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpsadbw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpshufb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpshufb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpshufb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpshufb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpshufb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpshufb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpshufb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpshufb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpshufb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpshufhw zmm6, zmm5, 0xab # AVX512BW
|
||||
vpshufhw zmm6{k7}, zmm5, 0xab # AVX512BW
|
||||
vpshufhw zmm6{k7}{z}, zmm5, 0xab # AVX512BW
|
||||
vpshufhw zmm6, zmm5, 123 # AVX512BW
|
||||
vpshufhw zmm6, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpshufhw zmm6, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpshufhw zmm6, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpshufhw zmm6, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpshufhw zmm6, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpshufhw zmm6, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
vpshuflw zmm6, zmm5, 0xab # AVX512BW
|
||||
vpshuflw zmm6{k7}, zmm5, 0xab # AVX512BW
|
||||
vpshuflw zmm6{k7}{z}, zmm5, 0xab # AVX512BW
|
||||
vpshuflw zmm6, zmm5, 123 # AVX512BW
|
||||
vpshuflw zmm6, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpshuflw zmm6, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpshuflw zmm6, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpshuflw zmm6, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpshuflw zmm6, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpshuflw zmm6, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
vpsllw zmm6{k7}, zmm5, xmm4 # AVX512BW
|
||||
vpsllw zmm6{k7}{z}, zmm5, xmm4 # AVX512BW
|
||||
vpsllw zmm6{k7}, zmm5, XMMWORD PTR [ecx] # AVX512BW
|
||||
vpsllw zmm6{k7}, zmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsllw zmm6{k7}, zmm5, XMMWORD PTR [edx+2032] # AVX512BW Disp8
|
||||
vpsllw zmm6{k7}, zmm5, XMMWORD PTR [edx+2048] # AVX512BW
|
||||
vpsllw zmm6{k7}, zmm5, XMMWORD PTR [edx-2048] # AVX512BW Disp8
|
||||
vpsllw zmm6{k7}, zmm5, XMMWORD PTR [edx-2064] # AVX512BW
|
||||
vpsraw zmm6{k7}, zmm5, xmm4 # AVX512BW
|
||||
vpsraw zmm6{k7}{z}, zmm5, xmm4 # AVX512BW
|
||||
vpsraw zmm6{k7}, zmm5, XMMWORD PTR [ecx] # AVX512BW
|
||||
vpsraw zmm6{k7}, zmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsraw zmm6{k7}, zmm5, XMMWORD PTR [edx+2032] # AVX512BW Disp8
|
||||
vpsraw zmm6{k7}, zmm5, XMMWORD PTR [edx+2048] # AVX512BW
|
||||
vpsraw zmm6{k7}, zmm5, XMMWORD PTR [edx-2048] # AVX512BW Disp8
|
||||
vpsraw zmm6{k7}, zmm5, XMMWORD PTR [edx-2064] # AVX512BW
|
||||
vpsrlw zmm6{k7}, zmm5, xmm4 # AVX512BW
|
||||
vpsrlw zmm6{k7}{z}, zmm5, xmm4 # AVX512BW
|
||||
vpsrlw zmm6{k7}, zmm5, XMMWORD PTR [ecx] # AVX512BW
|
||||
vpsrlw zmm6{k7}, zmm5, XMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsrlw zmm6{k7}, zmm5, XMMWORD PTR [edx+2032] # AVX512BW Disp8
|
||||
vpsrlw zmm6{k7}, zmm5, XMMWORD PTR [edx+2048] # AVX512BW
|
||||
vpsrlw zmm6{k7}, zmm5, XMMWORD PTR [edx-2048] # AVX512BW Disp8
|
||||
vpsrlw zmm6{k7}, zmm5, XMMWORD PTR [edx-2064] # AVX512BW
|
||||
vpsrldq zmm6, zmm5, 0xab # AVX512BW
|
||||
vpsrldq zmm6, zmm5, 123 # AVX512BW
|
||||
vpsrldq zmm6, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpsrldq zmm6, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpsrldq zmm6, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpsrldq zmm6, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpsrldq zmm6, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpsrldq zmm6, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
vpsrlw zmm6, zmm5, 0xab # AVX512BW
|
||||
vpsrlw zmm6{k7}, zmm5, 0xab # AVX512BW
|
||||
vpsrlw zmm6{k7}{z}, zmm5, 0xab # AVX512BW
|
||||
vpsrlw zmm6, zmm5, 123 # AVX512BW
|
||||
vpsrlw zmm6, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpsrlw zmm6, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpsrlw zmm6, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpsrlw zmm6, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpsrlw zmm6, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpsrlw zmm6, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
vpsraw zmm6, zmm5, 0xab # AVX512BW
|
||||
vpsraw zmm6{k7}, zmm5, 0xab # AVX512BW
|
||||
vpsraw zmm6{k7}{z}, zmm5, 0xab # AVX512BW
|
||||
vpsraw zmm6, zmm5, 123 # AVX512BW
|
||||
vpsraw zmm6, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpsraw zmm6, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpsraw zmm6, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpsraw zmm6, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpsraw zmm6, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpsraw zmm6, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
vpsubb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpsubb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpsubb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpsubb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpsubb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsubb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpsubb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpsubb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpsubb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpsubsb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpsubsb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpsubsb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpsubsb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpsubsb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsubsb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpsubsb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpsubsb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpsubsb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpsubsw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpsubsw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpsubsw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpsubsw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpsubsw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsubsw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpsubsw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpsubsw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpsubsw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpsubusb zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpsubusb zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpsubusb zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpsubusb zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpsubusb zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsubusb zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpsubusb zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpsubusb zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpsubusb zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpsubusw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpsubusw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpsubusw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpsubusw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpsubusw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsubusw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpsubusw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpsubusw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpsubusw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpsubw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpsubw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpsubw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpsubw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpsubw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpsubw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpsubw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpsubw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpsubw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpunpckhbw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpunpckhbw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpunpckhbw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpunpckhbw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpunpckhbw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpunpckhbw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpunpckhbw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpunpckhbw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpunpckhbw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpunpckhwd zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpunpckhwd zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpunpckhwd zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpunpckhwd zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpunpckhwd zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpunpckhwd zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpunpckhwd zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpunpckhwd zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpunpckhwd zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpunpcklbw zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpunpcklbw zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpunpcklbw zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpunpcklbw zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpunpcklbw zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpunpcklbw zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpunpcklbw zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpunpcklbw zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpunpcklbw zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpunpcklwd zmm6, zmm5, zmm4 # AVX512BW
|
||||
vpunpcklwd zmm6{k7}, zmm5, zmm4 # AVX512BW
|
||||
vpunpcklwd zmm6{k7}{z}, zmm5, zmm4 # AVX512BW
|
||||
vpunpcklwd zmm6, zmm5, ZMMWORD PTR [ecx] # AVX512BW
|
||||
vpunpcklwd zmm6, zmm5, ZMMWORD PTR [esp+esi*8-123456] # AVX512BW
|
||||
vpunpcklwd zmm6, zmm5, ZMMWORD PTR [edx+8128] # AVX512BW Disp8
|
||||
vpunpcklwd zmm6, zmm5, ZMMWORD PTR [edx+8192] # AVX512BW
|
||||
vpunpcklwd zmm6, zmm5, ZMMWORD PTR [edx-8192] # AVX512BW Disp8
|
||||
vpunpcklwd zmm6, zmm5, ZMMWORD PTR [edx-8256] # AVX512BW
|
||||
vpslldq zmm6, zmm5, 0xab # AVX512BW
|
||||
vpslldq zmm6, zmm5, 123 # AVX512BW
|
||||
vpslldq zmm6, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpslldq zmm6, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpslldq zmm6, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpslldq zmm6, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpslldq zmm6, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpslldq zmm6, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
vpsllw zmm6, zmm5, 0xab # AVX512BW
|
||||
vpsllw zmm6{k7}, zmm5, 0xab # AVX512BW
|
||||
vpsllw zmm6{k7}{z}, zmm5, 0xab # AVX512BW
|
||||
vpsllw zmm6, zmm5, 123 # AVX512BW
|
||||
vpsllw zmm6, ZMMWORD PTR [ecx], 123 # AVX512BW
|
||||
vpsllw zmm6, ZMMWORD PTR [esp+esi*8-123456], 123 # AVX512BW
|
||||
vpsllw zmm6, ZMMWORD PTR [edx+8128], 123 # AVX512BW Disp8
|
||||
vpsllw zmm6, ZMMWORD PTR [edx+8192], 123 # AVX512BW
|
||||
vpsllw zmm6, ZMMWORD PTR [edx-8192], 123 # AVX512BW Disp8
|
||||
vpsllw zmm6, ZMMWORD PTR [edx-8256], 123 # AVX512BW
|
||||
988
gas/testsuite/gas/i386/avx512bw-wig1-intel.d
Normal file
988
gas/testsuite/gas/i386/avx512bw-wig1-intel.d
Normal file
|
|
@ -0,0 +1,988 @@
|
|||
#as: -mevexwig=1
|
||||
#objdump: -dw -Mintel
|
||||
#name: i386 AVX512BW wig insns (Intel disassembly)
|
||||
#source: avx512bw-wig.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c f5[ ]*vpabsb zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1c f5[ ]*vpabsb zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1c f5[ ]*vpabsb zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 31[ ]*vpabsb zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b4 f4 c0 1d fe ff[ ]*vpabsb zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 7f[ ]*vpabsb zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 00 20 00 00[ ]*vpabsb zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 80[ ]*vpabsb zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 c0 df ff ff[ ]*vpabsb zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d f5[ ]*vpabsw zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1d f5[ ]*vpabsw zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1d f5[ ]*vpabsw zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 31[ ]*vpabsw zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b4 f4 c0 1d fe ff[ ]*vpabsw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 7f[ ]*vpabsw zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 00 20 00 00[ ]*vpabsw zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 80[ ]*vpabsw zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 c0 df ff ff[ ]*vpabsw zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 f4[ ]*vpacksswb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 63 f4[ ]*vpacksswb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 63 f4[ ]*vpacksswb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 31[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b4 f4 c0 1d fe ff[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 7f[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 00 20 00 00[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 80[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 c0 df ff ff[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 f4[ ]*vpackuswb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 67 f4[ ]*vpackuswb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 67 f4[ ]*vpackuswb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 31[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b4 f4 c0 1d fe ff[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 7f[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 00 20 00 00[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 80[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 c0 df ff ff[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc f4[ ]*vpaddb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fc f4[ ]*vpaddb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fc f4[ ]*vpaddb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 31[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b4 f4 c0 1d fe ff[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 7f[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 00 20 00 00[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 80[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 c0 df ff ff[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec f4[ ]*vpaddsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ec f4[ ]*vpaddsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ec f4[ ]*vpaddsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 31[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b4 f4 c0 1d fe ff[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 7f[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 00 20 00 00[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 80[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 c0 df ff ff[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed f4[ ]*vpaddsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ed f4[ ]*vpaddsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ed f4[ ]*vpaddsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 31[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b4 f4 c0 1d fe ff[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 7f[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 00 20 00 00[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 80[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 c0 df ff ff[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc f4[ ]*vpaddusb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dc f4[ ]*vpaddusb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dc f4[ ]*vpaddusb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 31[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b4 f4 c0 1d fe ff[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 7f[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 00 20 00 00[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 80[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 c0 df ff ff[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd f4[ ]*vpaddusw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dd f4[ ]*vpaddusw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dd f4[ ]*vpaddusw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 31[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b4 f4 c0 1d fe ff[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 7f[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 00 20 00 00[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 80[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 c0 df ff ff[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd f4[ ]*vpaddw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fd f4[ ]*vpaddw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fd f4[ ]*vpaddw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 31[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b4 f4 c0 1d fe ff[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 7f[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 00 20 00 00[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 80[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 c0 df ff ff[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 ab[ ]*vpalignr zmm6,zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f 0f f4 ab[ ]*vpalignr zmm6\{k7\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf 0f f4 ab[ ]*vpalignr zmm6\{k7\}\{z\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 7b[ ]*vpalignr zmm6,zmm5,zmm4,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 31 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b4 f4 c0 1d fe ff 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 7f 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 00 20 00 00 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 80 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 c0 df ff ff 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 f4[ ]*vpavgb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e0 f4[ ]*vpavgb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e0 f4[ ]*vpavgb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 31[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b4 f4 c0 1d fe ff[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 7f[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 00 20 00 00[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 80[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 c0 df ff ff[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 f4[ ]*vpavgw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e3 f4[ ]*vpavgw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e3 f4[ ]*vpavgw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 31[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b4 f4 c0 1d fe ff[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 7f[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 00 20 00 00[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 80[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 c0 df ff ff[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ed[ ]*vpcmpeqb k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 74 ed[ ]*vpcmpeqb k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 29[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ac f4 c0 1d fe ff[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 7f[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa 00 20 00 00[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 80[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa c0 df ff ff[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ed[ ]*vpcmpeqw k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 75 ed[ ]*vpcmpeqw k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 29[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ac f4 c0 1d fe ff[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 7f[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa 00 20 00 00[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 80[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa c0 df ff ff[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ed[ ]*vpcmpgtb k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 64 ed[ ]*vpcmpgtb k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 29[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ac f4 c0 1d fe ff[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 7f[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa 00 20 00 00[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 80[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa c0 df ff ff[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ed[ ]*vpcmpgtw k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 65 ed[ ]*vpcmpgtw k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 29[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ac f4 c0 1d fe ff[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 7f[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa 00 20 00 00[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 80[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa c0 df ff ff[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 f4[ ]*vpmaddubsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 04 f4[ ]*vpmaddubsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 04 f4[ ]*vpmaddubsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 31[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b4 f4 c0 1d fe ff[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 7f[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 00 20 00 00[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 80[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 c0 df ff ff[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 f4[ ]*vpmaddwd zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f5 f4[ ]*vpmaddwd zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f5 f4[ ]*vpmaddwd zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 31[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b4 f4 c0 1d fe ff[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 7f[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 00 20 00 00[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 80[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 c0 df ff ff[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c f4[ ]*vpmaxsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3c f4[ ]*vpmaxsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3c f4[ ]*vpmaxsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 31[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b4 f4 c0 1d fe ff[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 7f[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 00 20 00 00[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 80[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 c0 df ff ff[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee f4[ ]*vpmaxsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ee f4[ ]*vpmaxsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ee f4[ ]*vpmaxsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 31[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b4 f4 c0 1d fe ff[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 7f[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 00 20 00 00[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 80[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 c0 df ff ff[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de f4[ ]*vpmaxub zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f de f4[ ]*vpmaxub zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf de f4[ ]*vpmaxub zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 31[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b4 f4 c0 1d fe ff[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 7f[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 00 20 00 00[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 80[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 c0 df ff ff[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e f4[ ]*vpmaxuw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3e f4[ ]*vpmaxuw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3e f4[ ]*vpmaxuw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 31[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b4 f4 c0 1d fe ff[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 7f[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 00 20 00 00[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 80[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 c0 df ff ff[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 f4[ ]*vpminsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 38 f4[ ]*vpminsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 38 f4[ ]*vpminsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 31[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b4 f4 c0 1d fe ff[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 7f[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 00 20 00 00[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 80[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 c0 df ff ff[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea f4[ ]*vpminsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ea f4[ ]*vpminsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ea f4[ ]*vpminsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 31[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b4 f4 c0 1d fe ff[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 7f[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 00 20 00 00[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 80[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 c0 df ff ff[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da f4[ ]*vpminub zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f da f4[ ]*vpminub zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf da f4[ ]*vpminub zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 31[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b4 f4 c0 1d fe ff[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 7f[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 00 20 00 00[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 80[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 c0 df ff ff[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a f4[ ]*vpminuw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3a f4[ ]*vpminuw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3a f4[ ]*vpminuw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 31[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b4 f4 c0 1d fe ff[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 7f[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 00 20 00 00[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 80[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 c0 df ff ff[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 f5[ ]*vpmovsxbw zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 20 f5[ ]*vpmovsxbw zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 31[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b4 f4 c0 1d fe ff[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 7f[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 00 10 00 00[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 80[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 e0 ef ff ff[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 f5[ ]*vpmovzxbw zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 30 f5[ ]*vpmovzxbw zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 31[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b4 f4 c0 1d fe ff[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 7f[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 00 10 00 00[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 80[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 e0 ef ff ff[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b f4[ ]*vpmulhrsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 0b f4[ ]*vpmulhrsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 0b f4[ ]*vpmulhrsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 31[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b4 f4 c0 1d fe ff[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 7f[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 00 20 00 00[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 80[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 c0 df ff ff[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 f4[ ]*vpmulhuw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e4 f4[ ]*vpmulhuw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e4 f4[ ]*vpmulhuw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 31[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b4 f4 c0 1d fe ff[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 7f[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 00 20 00 00[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 80[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 c0 df ff ff[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 f4[ ]*vpmulhw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e5 f4[ ]*vpmulhw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e5 f4[ ]*vpmulhw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 31[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b4 f4 c0 1d fe ff[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 7f[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 00 20 00 00[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 80[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 c0 df ff ff[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 f4[ ]*vpmullw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d5 f4[ ]*vpmullw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d5 f4[ ]*vpmullw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 31[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b4 f4 c0 1d fe ff[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 7f[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 00 20 00 00[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 80[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 c0 df ff ff[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 f4[ ]*vpsadbw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 31[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b4 f4 c0 1d fe ff[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 7f[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 00 20 00 00[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 80[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 c0 df ff ff[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 f4[ ]*vpshufb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 00 f4[ ]*vpshufb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 00 f4[ ]*vpshufb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 31[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b4 f4 c0 1d fe ff[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 7f[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 00 20 00 00[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 80[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 c0 df ff ff[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 ab[ ]*vpshufhw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 4f 70 f5 ab[ ]*vpshufhw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe cf 70 f5 ab[ ]*vpshufhw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 7b[ ]*vpshufhw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 31 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 7f 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 00 20 00 00 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 80 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 c0 df ff ff 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 ab[ ]*vpshuflw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 70 f5 ab[ ]*vpshuflw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 70 f5 ab[ ]*vpshuflw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 7b[ ]*vpshuflw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 31 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 7f 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 00 20 00 00 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 80 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 c0 df ff ff 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 f4[ ]*vpsllw zmm6\{k7\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f1 f4[ ]*vpsllw zmm6\{k7\}\{z\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 31[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b4 f4 c0 1d fe ff[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 7f[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 00 08 00 00[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 80[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 f0 f7 ff ff[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 f4[ ]*vpsraw zmm6\{k7\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e1 f4[ ]*vpsraw zmm6\{k7\}\{z\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 31[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b4 f4 c0 1d fe ff[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 7f[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 00 08 00 00[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 80[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 f0 f7 ff ff[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 f4[ ]*vpsrlw zmm6\{k7\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d1 f4[ ]*vpsrlw zmm6\{k7\}\{z\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 31[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b4 f4 c0 1d fe ff[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 7f[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 00 08 00 00[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 80[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 f0 f7 ff ff[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd ab[ ]*vpsrldq zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd 7b[ ]*vpsrldq zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 19 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9c f4 c0 1d fe ff 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 7f 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a 00 20 00 00 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 80 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a c0 df ff ff 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 ab[ ]*vpsrlw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 d5 ab[ ]*vpsrlw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 d5 ab[ ]*vpsrlw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 7b[ ]*vpsrlw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 11 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 94 f4 c0 1d fe ff 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 7f 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 00 20 00 00 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 80 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 c0 df ff ff 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 ab[ ]*vpsraw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 e5 ab[ ]*vpsraw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 e5 ab[ ]*vpsraw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 7b[ ]*vpsraw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 21 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a4 f4 c0 1d fe ff 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 7f 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 00 20 00 00 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 80 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 c0 df ff ff 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 f4[ ]*vpsubb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f8 f4[ ]*vpsubb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f8 f4[ ]*vpsubb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 31[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b4 f4 c0 1d fe ff[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 7f[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 00 20 00 00[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 80[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 c0 df ff ff[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 f4[ ]*vpsubsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e8 f4[ ]*vpsubsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e8 f4[ ]*vpsubsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 31[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b4 f4 c0 1d fe ff[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 7f[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 00 20 00 00[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 80[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 c0 df ff ff[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 f4[ ]*vpsubsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e9 f4[ ]*vpsubsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e9 f4[ ]*vpsubsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 31[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b4 f4 c0 1d fe ff[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 7f[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 00 20 00 00[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 80[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 c0 df ff ff[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 f4[ ]*vpsubusb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d8 f4[ ]*vpsubusb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d8 f4[ ]*vpsubusb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 31[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b4 f4 c0 1d fe ff[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 7f[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 00 20 00 00[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 80[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 c0 df ff ff[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 f4[ ]*vpsubusw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d9 f4[ ]*vpsubusw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d9 f4[ ]*vpsubusw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 31[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b4 f4 c0 1d fe ff[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 7f[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 00 20 00 00[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 80[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 c0 df ff ff[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 f4[ ]*vpsubw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f9 f4[ ]*vpsubw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f9 f4[ ]*vpsubw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 31[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b4 f4 c0 1d fe ff[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 7f[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 00 20 00 00[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 80[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 c0 df ff ff[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 f4[ ]*vpunpckhbw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 68 f4[ ]*vpunpckhbw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 68 f4[ ]*vpunpckhbw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 31[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b4 f4 c0 1d fe ff[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 7f[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 00 20 00 00[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 80[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 c0 df ff ff[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 f4[ ]*vpunpckhwd zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 69 f4[ ]*vpunpckhwd zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 69 f4[ ]*vpunpckhwd zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 31[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b4 f4 c0 1d fe ff[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 7f[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 00 20 00 00[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 80[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 c0 df ff ff[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 f4[ ]*vpunpcklbw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 60 f4[ ]*vpunpcklbw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 60 f4[ ]*vpunpcklbw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 31[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b4 f4 c0 1d fe ff[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 7f[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 00 20 00 00[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 80[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 c0 df ff ff[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 f4[ ]*vpunpcklwd zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 61 f4[ ]*vpunpcklwd zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 61 f4[ ]*vpunpcklwd zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 31[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b4 f4 c0 1d fe ff[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 7f[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 00 20 00 00[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 80[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 c0 df ff ff[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd ab[ ]*vpslldq zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd 7b[ ]*vpslldq zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 39 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 bc f4 c0 1d fe ff 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 7f 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba 00 20 00 00 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 80 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba c0 df ff ff 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 ab[ ]*vpsllw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 f5 ab[ ]*vpsllw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 f5 ab[ ]*vpsllw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 7b[ ]*vpsllw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 31 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b4 f4 c0 1d fe ff 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 7f 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 00 20 00 00 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 80 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 c0 df ff ff 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c f5[ ]*vpabsb zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1c f5[ ]*vpabsb zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1c f5[ ]*vpabsb zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 31[ ]*vpabsb zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b4 f4 c0 1d fe ff[ ]*vpabsb zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 7f[ ]*vpabsb zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 00 20 00 00[ ]*vpabsb zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 80[ ]*vpabsb zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 c0 df ff ff[ ]*vpabsb zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d f5[ ]*vpabsw zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1d f5[ ]*vpabsw zmm6\{k7\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1d f5[ ]*vpabsw zmm6\{k7\}\{z\},zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 31[ ]*vpabsw zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b4 f4 c0 1d fe ff[ ]*vpabsw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 7f[ ]*vpabsw zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 00 20 00 00[ ]*vpabsw zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 80[ ]*vpabsw zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 c0 df ff ff[ ]*vpabsw zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 f4[ ]*vpacksswb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 63 f4[ ]*vpacksswb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 63 f4[ ]*vpacksswb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 31[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b4 f4 c0 1d fe ff[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 7f[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 00 20 00 00[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 80[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 c0 df ff ff[ ]*vpacksswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 f4[ ]*vpackuswb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 67 f4[ ]*vpackuswb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 67 f4[ ]*vpackuswb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 31[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b4 f4 c0 1d fe ff[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 7f[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 00 20 00 00[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 80[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 c0 df ff ff[ ]*vpackuswb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc f4[ ]*vpaddb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fc f4[ ]*vpaddb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fc f4[ ]*vpaddb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 31[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b4 f4 c0 1d fe ff[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 7f[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 00 20 00 00[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 80[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 c0 df ff ff[ ]*vpaddb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec f4[ ]*vpaddsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ec f4[ ]*vpaddsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ec f4[ ]*vpaddsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 31[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b4 f4 c0 1d fe ff[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 7f[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 00 20 00 00[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 80[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 c0 df ff ff[ ]*vpaddsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed f4[ ]*vpaddsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ed f4[ ]*vpaddsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ed f4[ ]*vpaddsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 31[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b4 f4 c0 1d fe ff[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 7f[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 00 20 00 00[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 80[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 c0 df ff ff[ ]*vpaddsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc f4[ ]*vpaddusb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dc f4[ ]*vpaddusb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dc f4[ ]*vpaddusb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 31[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b4 f4 c0 1d fe ff[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 7f[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 00 20 00 00[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 80[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 c0 df ff ff[ ]*vpaddusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd f4[ ]*vpaddusw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dd f4[ ]*vpaddusw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dd f4[ ]*vpaddusw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 31[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b4 f4 c0 1d fe ff[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 7f[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 00 20 00 00[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 80[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 c0 df ff ff[ ]*vpaddusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd f4[ ]*vpaddw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fd f4[ ]*vpaddw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fd f4[ ]*vpaddw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 31[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b4 f4 c0 1d fe ff[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 7f[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 00 20 00 00[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 80[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 c0 df ff ff[ ]*vpaddw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 ab[ ]*vpalignr zmm6,zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f 0f f4 ab[ ]*vpalignr zmm6\{k7\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf 0f f4 ab[ ]*vpalignr zmm6\{k7\}\{z\},zmm5,zmm4,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 7b[ ]*vpalignr zmm6,zmm5,zmm4,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 31 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b4 f4 c0 1d fe ff 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 7f 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 00 20 00 00 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 80 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 c0 df ff ff 7b[ ]*vpalignr zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 f4[ ]*vpavgb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e0 f4[ ]*vpavgb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e0 f4[ ]*vpavgb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 31[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b4 f4 c0 1d fe ff[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 7f[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 00 20 00 00[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 80[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 c0 df ff ff[ ]*vpavgb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 f4[ ]*vpavgw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e3 f4[ ]*vpavgw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e3 f4[ ]*vpavgw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 31[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b4 f4 c0 1d fe ff[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 7f[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 00 20 00 00[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 80[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 c0 df ff ff[ ]*vpavgw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ed[ ]*vpcmpeqb k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 74 ed[ ]*vpcmpeqb k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 29[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ac f4 c0 1d fe ff[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 7f[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa 00 20 00 00[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 80[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa c0 df ff ff[ ]*vpcmpeqb k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ed[ ]*vpcmpeqw k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 75 ed[ ]*vpcmpeqw k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 29[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ac f4 c0 1d fe ff[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 7f[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa 00 20 00 00[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 80[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa c0 df ff ff[ ]*vpcmpeqw k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ed[ ]*vpcmpgtb k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 64 ed[ ]*vpcmpgtb k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 29[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ac f4 c0 1d fe ff[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 7f[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa 00 20 00 00[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 80[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa c0 df ff ff[ ]*vpcmpgtb k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ed[ ]*vpcmpgtw k5,zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 65 ed[ ]*vpcmpgtw k5\{k7\},zmm6,zmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 29[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ac f4 c0 1d fe ff[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 7f[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa 00 20 00 00[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 80[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa c0 df ff ff[ ]*vpcmpgtw k5,zmm6,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 f4[ ]*vpmaddubsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 04 f4[ ]*vpmaddubsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 04 f4[ ]*vpmaddubsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 31[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b4 f4 c0 1d fe ff[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 7f[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 00 20 00 00[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 80[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 c0 df ff ff[ ]*vpmaddubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 f4[ ]*vpmaddwd zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f5 f4[ ]*vpmaddwd zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f5 f4[ ]*vpmaddwd zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 31[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b4 f4 c0 1d fe ff[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 7f[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 00 20 00 00[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 80[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 c0 df ff ff[ ]*vpmaddwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c f4[ ]*vpmaxsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3c f4[ ]*vpmaxsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3c f4[ ]*vpmaxsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 31[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b4 f4 c0 1d fe ff[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 7f[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 00 20 00 00[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 80[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 c0 df ff ff[ ]*vpmaxsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee f4[ ]*vpmaxsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ee f4[ ]*vpmaxsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ee f4[ ]*vpmaxsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 31[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b4 f4 c0 1d fe ff[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 7f[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 00 20 00 00[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 80[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 c0 df ff ff[ ]*vpmaxsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de f4[ ]*vpmaxub zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f de f4[ ]*vpmaxub zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf de f4[ ]*vpmaxub zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 31[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b4 f4 c0 1d fe ff[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 7f[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 00 20 00 00[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 80[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 c0 df ff ff[ ]*vpmaxub zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e f4[ ]*vpmaxuw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3e f4[ ]*vpmaxuw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3e f4[ ]*vpmaxuw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 31[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b4 f4 c0 1d fe ff[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 7f[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 00 20 00 00[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 80[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 c0 df ff ff[ ]*vpmaxuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 f4[ ]*vpminsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 38 f4[ ]*vpminsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 38 f4[ ]*vpminsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 31[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b4 f4 c0 1d fe ff[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 7f[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 00 20 00 00[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 80[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 c0 df ff ff[ ]*vpminsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea f4[ ]*vpminsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ea f4[ ]*vpminsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ea f4[ ]*vpminsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 31[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b4 f4 c0 1d fe ff[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 7f[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 00 20 00 00[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 80[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 c0 df ff ff[ ]*vpminsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da f4[ ]*vpminub zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f da f4[ ]*vpminub zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf da f4[ ]*vpminub zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 31[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b4 f4 c0 1d fe ff[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 7f[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 00 20 00 00[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 80[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 c0 df ff ff[ ]*vpminub zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a f4[ ]*vpminuw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3a f4[ ]*vpminuw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3a f4[ ]*vpminuw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 31[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b4 f4 c0 1d fe ff[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 7f[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 00 20 00 00[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 80[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 c0 df ff ff[ ]*vpminuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 f5[ ]*vpmovsxbw zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 20 f5[ ]*vpmovsxbw zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 31[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b4 f4 c0 1d fe ff[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 7f[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 00 10 00 00[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 80[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 e0 ef ff ff[ ]*vpmovsxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 f5[ ]*vpmovzxbw zmm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 30 f5[ ]*vpmovzxbw zmm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 31[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b4 f4 c0 1d fe ff[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 7f[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx\+0xfe0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 00 10 00 00[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx\+0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 80[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 e0 ef ff ff[ ]*vpmovzxbw zmm6\{k7\},YMMWORD PTR \[edx-0x1020\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b f4[ ]*vpmulhrsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 0b f4[ ]*vpmulhrsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 0b f4[ ]*vpmulhrsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 31[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b4 f4 c0 1d fe ff[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 7f[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 00 20 00 00[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 80[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 c0 df ff ff[ ]*vpmulhrsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 f4[ ]*vpmulhuw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e4 f4[ ]*vpmulhuw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e4 f4[ ]*vpmulhuw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 31[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b4 f4 c0 1d fe ff[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 7f[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 00 20 00 00[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 80[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 c0 df ff ff[ ]*vpmulhuw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 f4[ ]*vpmulhw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e5 f4[ ]*vpmulhw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e5 f4[ ]*vpmulhw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 31[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b4 f4 c0 1d fe ff[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 7f[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 00 20 00 00[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 80[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 c0 df ff ff[ ]*vpmulhw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 f4[ ]*vpmullw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d5 f4[ ]*vpmullw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d5 f4[ ]*vpmullw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 31[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b4 f4 c0 1d fe ff[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 7f[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 00 20 00 00[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 80[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 c0 df ff ff[ ]*vpmullw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 f4[ ]*vpsadbw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 31[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b4 f4 c0 1d fe ff[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 7f[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 00 20 00 00[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 80[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 c0 df ff ff[ ]*vpsadbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 f4[ ]*vpshufb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 00 f4[ ]*vpshufb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 00 f4[ ]*vpshufb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 31[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b4 f4 c0 1d fe ff[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 7f[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 00 20 00 00[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 80[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 c0 df ff ff[ ]*vpshufb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 ab[ ]*vpshufhw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 4f 70 f5 ab[ ]*vpshufhw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe cf 70 f5 ab[ ]*vpshufhw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 7b[ ]*vpshufhw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 31 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 7f 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 00 20 00 00 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 80 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 c0 df ff ff 7b[ ]*vpshufhw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 ab[ ]*vpshuflw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 70 f5 ab[ ]*vpshuflw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 70 f5 ab[ ]*vpshuflw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 7b[ ]*vpshuflw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 31 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 7f 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 00 20 00 00 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 80 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 c0 df ff ff 7b[ ]*vpshuflw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 f4[ ]*vpsllw zmm6\{k7\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f1 f4[ ]*vpsllw zmm6\{k7\}\{z\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 31[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b4 f4 c0 1d fe ff[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 7f[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 00 08 00 00[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 80[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 f0 f7 ff ff[ ]*vpsllw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 f4[ ]*vpsraw zmm6\{k7\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e1 f4[ ]*vpsraw zmm6\{k7\}\{z\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 31[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b4 f4 c0 1d fe ff[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 7f[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 00 08 00 00[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 80[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 f0 f7 ff ff[ ]*vpsraw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 f4[ ]*vpsrlw zmm6\{k7\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d1 f4[ ]*vpsrlw zmm6\{k7\}\{z\},zmm5,xmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 31[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b4 f4 c0 1d fe ff[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 7f[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x7f0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 00 08 00 00[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx\+0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 80[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x800\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 f0 f7 ff ff[ ]*vpsrlw zmm6\{k7\},zmm5,XMMWORD PTR \[edx-0x810\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd ab[ ]*vpsrldq zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd 7b[ ]*vpsrldq zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 19 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9c f4 c0 1d fe ff 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 7f 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a 00 20 00 00 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 80 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a c0 df ff ff 7b[ ]*vpsrldq zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 ab[ ]*vpsrlw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 d5 ab[ ]*vpsrlw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 d5 ab[ ]*vpsrlw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 7b[ ]*vpsrlw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 11 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 94 f4 c0 1d fe ff 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 7f 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 00 20 00 00 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 80 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 c0 df ff ff 7b[ ]*vpsrlw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 ab[ ]*vpsraw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 e5 ab[ ]*vpsraw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 e5 ab[ ]*vpsraw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 7b[ ]*vpsraw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 21 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a4 f4 c0 1d fe ff 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 7f 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 00 20 00 00 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 80 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 c0 df ff ff 7b[ ]*vpsraw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 f4[ ]*vpsubb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f8 f4[ ]*vpsubb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f8 f4[ ]*vpsubb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 31[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b4 f4 c0 1d fe ff[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 7f[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 00 20 00 00[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 80[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 c0 df ff ff[ ]*vpsubb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 f4[ ]*vpsubsb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e8 f4[ ]*vpsubsb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e8 f4[ ]*vpsubsb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 31[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b4 f4 c0 1d fe ff[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 7f[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 00 20 00 00[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 80[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 c0 df ff ff[ ]*vpsubsb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 f4[ ]*vpsubsw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e9 f4[ ]*vpsubsw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e9 f4[ ]*vpsubsw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 31[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b4 f4 c0 1d fe ff[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 7f[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 00 20 00 00[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 80[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 c0 df ff ff[ ]*vpsubsw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 f4[ ]*vpsubusb zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d8 f4[ ]*vpsubusb zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d8 f4[ ]*vpsubusb zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 31[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b4 f4 c0 1d fe ff[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 7f[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 00 20 00 00[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 80[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 c0 df ff ff[ ]*vpsubusb zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 f4[ ]*vpsubusw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d9 f4[ ]*vpsubusw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d9 f4[ ]*vpsubusw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 31[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b4 f4 c0 1d fe ff[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 7f[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 00 20 00 00[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 80[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 c0 df ff ff[ ]*vpsubusw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 f4[ ]*vpsubw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f9 f4[ ]*vpsubw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f9 f4[ ]*vpsubw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 31[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b4 f4 c0 1d fe ff[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 7f[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 00 20 00 00[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 80[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 c0 df ff ff[ ]*vpsubw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 f4[ ]*vpunpckhbw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 68 f4[ ]*vpunpckhbw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 68 f4[ ]*vpunpckhbw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 31[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b4 f4 c0 1d fe ff[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 7f[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 00 20 00 00[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 80[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 c0 df ff ff[ ]*vpunpckhbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 f4[ ]*vpunpckhwd zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 69 f4[ ]*vpunpckhwd zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 69 f4[ ]*vpunpckhwd zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 31[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b4 f4 c0 1d fe ff[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 7f[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 00 20 00 00[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 80[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 c0 df ff ff[ ]*vpunpckhwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 f4[ ]*vpunpcklbw zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 60 f4[ ]*vpunpcklbw zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 60 f4[ ]*vpunpcklbw zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 31[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b4 f4 c0 1d fe ff[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 7f[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 00 20 00 00[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 80[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 c0 df ff ff[ ]*vpunpcklbw zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 f4[ ]*vpunpcklwd zmm6,zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 61 f4[ ]*vpunpcklwd zmm6\{k7\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 61 f4[ ]*vpunpcklwd zmm6\{k7\}\{z\},zmm5,zmm4
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 31[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[ecx\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b4 f4 c0 1d fe ff[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[esp\+esi\*8-0x1e240\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 7f[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x1fc0\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 00 20 00 00[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx\+0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 80[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2000\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 c0 df ff ff[ ]*vpunpcklwd zmm6,zmm5,ZMMWORD PTR \[edx-0x2040\]
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd ab[ ]*vpslldq zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd 7b[ ]*vpslldq zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 39 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 bc f4 c0 1d fe ff 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 7f 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba 00 20 00 00 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 80 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba c0 df ff ff 7b[ ]*vpslldq zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 ab[ ]*vpsllw zmm6,zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 f5 ab[ ]*vpsllw zmm6\{k7\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 f5 ab[ ]*vpsllw zmm6\{k7\}\{z\},zmm5,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 7b[ ]*vpsllw zmm6,zmm5,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 31 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[ecx\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b4 f4 c0 1d fe ff 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[esp\+esi\*8-0x1e240\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 7f 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx\+0x1fc0\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 00 20 00 00 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx\+0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 80 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx-0x2000\],0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 c0 df ff ff 7b[ ]*vpsllw zmm6,ZMMWORD PTR \[edx-0x2040\],0x7b
|
||||
#pass
|
||||
988
gas/testsuite/gas/i386/avx512bw-wig1.d
Normal file
988
gas/testsuite/gas/i386/avx512bw-wig1.d
Normal file
|
|
@ -0,0 +1,988 @@
|
|||
#as: -mevexwig=1
|
||||
#objdump: -dw
|
||||
#name: i386 AVX512BW wig insns
|
||||
#source: avx512bw-wig.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c f5[ ]*vpabsb %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1c f5[ ]*vpabsb %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1c f5[ ]*vpabsb %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 31[ ]*vpabsb \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b4 f4 c0 1d fe ff[ ]*vpabsb -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 7f[ ]*vpabsb 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 00 20 00 00[ ]*vpabsb 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 80[ ]*vpabsb -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 c0 df ff ff[ ]*vpabsb -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d f5[ ]*vpabsw %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1d f5[ ]*vpabsw %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1d f5[ ]*vpabsw %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 31[ ]*vpabsw \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b4 f4 c0 1d fe ff[ ]*vpabsw -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 7f[ ]*vpabsw 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 00 20 00 00[ ]*vpabsw 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 80[ ]*vpabsw -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 c0 df ff ff[ ]*vpabsw -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 f4[ ]*vpacksswb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 63 f4[ ]*vpacksswb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 63 f4[ ]*vpacksswb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 31[ ]*vpacksswb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b4 f4 c0 1d fe ff[ ]*vpacksswb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 7f[ ]*vpacksswb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 00 20 00 00[ ]*vpacksswb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 80[ ]*vpacksswb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 c0 df ff ff[ ]*vpacksswb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 f4[ ]*vpackuswb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 67 f4[ ]*vpackuswb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 67 f4[ ]*vpackuswb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 31[ ]*vpackuswb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b4 f4 c0 1d fe ff[ ]*vpackuswb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 7f[ ]*vpackuswb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 00 20 00 00[ ]*vpackuswb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 80[ ]*vpackuswb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 c0 df ff ff[ ]*vpackuswb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc f4[ ]*vpaddb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fc f4[ ]*vpaddb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fc f4[ ]*vpaddb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 31[ ]*vpaddb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b4 f4 c0 1d fe ff[ ]*vpaddb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 7f[ ]*vpaddb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 00 20 00 00[ ]*vpaddb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 80[ ]*vpaddb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 c0 df ff ff[ ]*vpaddb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec f4[ ]*vpaddsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ec f4[ ]*vpaddsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ec f4[ ]*vpaddsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 31[ ]*vpaddsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b4 f4 c0 1d fe ff[ ]*vpaddsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 7f[ ]*vpaddsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 00 20 00 00[ ]*vpaddsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 80[ ]*vpaddsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 c0 df ff ff[ ]*vpaddsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed f4[ ]*vpaddsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ed f4[ ]*vpaddsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ed f4[ ]*vpaddsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 31[ ]*vpaddsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b4 f4 c0 1d fe ff[ ]*vpaddsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 7f[ ]*vpaddsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 00 20 00 00[ ]*vpaddsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 80[ ]*vpaddsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 c0 df ff ff[ ]*vpaddsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc f4[ ]*vpaddusb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dc f4[ ]*vpaddusb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dc f4[ ]*vpaddusb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 31[ ]*vpaddusb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b4 f4 c0 1d fe ff[ ]*vpaddusb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 7f[ ]*vpaddusb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 00 20 00 00[ ]*vpaddusb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 80[ ]*vpaddusb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 c0 df ff ff[ ]*vpaddusb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd f4[ ]*vpaddusw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dd f4[ ]*vpaddusw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dd f4[ ]*vpaddusw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 31[ ]*vpaddusw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b4 f4 c0 1d fe ff[ ]*vpaddusw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 7f[ ]*vpaddusw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 00 20 00 00[ ]*vpaddusw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 80[ ]*vpaddusw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 c0 df ff ff[ ]*vpaddusw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd f4[ ]*vpaddw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fd f4[ ]*vpaddw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fd f4[ ]*vpaddw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 31[ ]*vpaddw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b4 f4 c0 1d fe ff[ ]*vpaddw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 7f[ ]*vpaddw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 00 20 00 00[ ]*vpaddw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 80[ ]*vpaddw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 c0 df ff ff[ ]*vpaddw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 ab[ ]*vpalignr \$0xab,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f 0f f4 ab[ ]*vpalignr \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf 0f f4 ab[ ]*vpalignr \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 7b[ ]*vpalignr \$0x7b,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 31 7b[ ]*vpalignr \$0x7b,\(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b4 f4 c0 1d fe ff 7b[ ]*vpalignr \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 7f 7b[ ]*vpalignr \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 00 20 00 00 7b[ ]*vpalignr \$0x7b,0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 80 7b[ ]*vpalignr \$0x7b,-0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 c0 df ff ff 7b[ ]*vpalignr \$0x7b,-0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 f4[ ]*vpavgb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e0 f4[ ]*vpavgb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e0 f4[ ]*vpavgb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 31[ ]*vpavgb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b4 f4 c0 1d fe ff[ ]*vpavgb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 7f[ ]*vpavgb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 00 20 00 00[ ]*vpavgb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 80[ ]*vpavgb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 c0 df ff ff[ ]*vpavgb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 f4[ ]*vpavgw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e3 f4[ ]*vpavgw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e3 f4[ ]*vpavgw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 31[ ]*vpavgw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b4 f4 c0 1d fe ff[ ]*vpavgw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 7f[ ]*vpavgw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 00 20 00 00[ ]*vpavgw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 80[ ]*vpavgw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 c0 df ff ff[ ]*vpavgw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ed[ ]*vpcmpeqb %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 74 ed[ ]*vpcmpeqb %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 29[ ]*vpcmpeqb \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ac f4 c0 1d fe ff[ ]*vpcmpeqb -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 7f[ ]*vpcmpeqb 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa 00 20 00 00[ ]*vpcmpeqb 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 80[ ]*vpcmpeqb -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa c0 df ff ff[ ]*vpcmpeqb -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ed[ ]*vpcmpeqw %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 75 ed[ ]*vpcmpeqw %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 29[ ]*vpcmpeqw \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ac f4 c0 1d fe ff[ ]*vpcmpeqw -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 7f[ ]*vpcmpeqw 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa 00 20 00 00[ ]*vpcmpeqw 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 80[ ]*vpcmpeqw -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa c0 df ff ff[ ]*vpcmpeqw -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ed[ ]*vpcmpgtb %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 64 ed[ ]*vpcmpgtb %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 29[ ]*vpcmpgtb \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ac f4 c0 1d fe ff[ ]*vpcmpgtb -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 7f[ ]*vpcmpgtb 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa 00 20 00 00[ ]*vpcmpgtb 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 80[ ]*vpcmpgtb -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa c0 df ff ff[ ]*vpcmpgtb -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ed[ ]*vpcmpgtw %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 65 ed[ ]*vpcmpgtw %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 29[ ]*vpcmpgtw \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ac f4 c0 1d fe ff[ ]*vpcmpgtw -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 7f[ ]*vpcmpgtw 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa 00 20 00 00[ ]*vpcmpgtw 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 80[ ]*vpcmpgtw -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa c0 df ff ff[ ]*vpcmpgtw -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 f4[ ]*vpmaddubsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 04 f4[ ]*vpmaddubsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 04 f4[ ]*vpmaddubsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 31[ ]*vpmaddubsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b4 f4 c0 1d fe ff[ ]*vpmaddubsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 7f[ ]*vpmaddubsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 00 20 00 00[ ]*vpmaddubsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 80[ ]*vpmaddubsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 c0 df ff ff[ ]*vpmaddubsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 f4[ ]*vpmaddwd %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f5 f4[ ]*vpmaddwd %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f5 f4[ ]*vpmaddwd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 31[ ]*vpmaddwd \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b4 f4 c0 1d fe ff[ ]*vpmaddwd -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 7f[ ]*vpmaddwd 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 00 20 00 00[ ]*vpmaddwd 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 80[ ]*vpmaddwd -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 c0 df ff ff[ ]*vpmaddwd -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c f4[ ]*vpmaxsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3c f4[ ]*vpmaxsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3c f4[ ]*vpmaxsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 31[ ]*vpmaxsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b4 f4 c0 1d fe ff[ ]*vpmaxsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 7f[ ]*vpmaxsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 00 20 00 00[ ]*vpmaxsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 80[ ]*vpmaxsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 c0 df ff ff[ ]*vpmaxsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee f4[ ]*vpmaxsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ee f4[ ]*vpmaxsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ee f4[ ]*vpmaxsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 31[ ]*vpmaxsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b4 f4 c0 1d fe ff[ ]*vpmaxsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 7f[ ]*vpmaxsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 00 20 00 00[ ]*vpmaxsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 80[ ]*vpmaxsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 c0 df ff ff[ ]*vpmaxsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de f4[ ]*vpmaxub %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f de f4[ ]*vpmaxub %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf de f4[ ]*vpmaxub %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 31[ ]*vpmaxub \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b4 f4 c0 1d fe ff[ ]*vpmaxub -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 7f[ ]*vpmaxub 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 00 20 00 00[ ]*vpmaxub 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 80[ ]*vpmaxub -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 c0 df ff ff[ ]*vpmaxub -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e f4[ ]*vpmaxuw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3e f4[ ]*vpmaxuw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3e f4[ ]*vpmaxuw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 31[ ]*vpmaxuw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b4 f4 c0 1d fe ff[ ]*vpmaxuw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 7f[ ]*vpmaxuw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 00 20 00 00[ ]*vpmaxuw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 80[ ]*vpmaxuw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 c0 df ff ff[ ]*vpmaxuw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 f4[ ]*vpminsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 38 f4[ ]*vpminsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 38 f4[ ]*vpminsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 31[ ]*vpminsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b4 f4 c0 1d fe ff[ ]*vpminsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 7f[ ]*vpminsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 00 20 00 00[ ]*vpminsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 80[ ]*vpminsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 c0 df ff ff[ ]*vpminsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea f4[ ]*vpminsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ea f4[ ]*vpminsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ea f4[ ]*vpminsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 31[ ]*vpminsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b4 f4 c0 1d fe ff[ ]*vpminsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 7f[ ]*vpminsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 00 20 00 00[ ]*vpminsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 80[ ]*vpminsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 c0 df ff ff[ ]*vpminsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da f4[ ]*vpminub %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f da f4[ ]*vpminub %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf da f4[ ]*vpminub %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 31[ ]*vpminub \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b4 f4 c0 1d fe ff[ ]*vpminub -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 7f[ ]*vpminub 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 00 20 00 00[ ]*vpminub 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 80[ ]*vpminub -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 c0 df ff ff[ ]*vpminub -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a f4[ ]*vpminuw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3a f4[ ]*vpminuw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3a f4[ ]*vpminuw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 31[ ]*vpminuw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b4 f4 c0 1d fe ff[ ]*vpminuw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 7f[ ]*vpminuw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 00 20 00 00[ ]*vpminuw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 80[ ]*vpminuw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 c0 df ff ff[ ]*vpminuw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 f5[ ]*vpmovsxbw %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 20 f5[ ]*vpmovsxbw %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 31[ ]*vpmovsxbw \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b4 f4 c0 1d fe ff[ ]*vpmovsxbw -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 7f[ ]*vpmovsxbw 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 00 10 00 00[ ]*vpmovsxbw 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 80[ ]*vpmovsxbw -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 e0 ef ff ff[ ]*vpmovsxbw -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 f5[ ]*vpmovzxbw %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 30 f5[ ]*vpmovzxbw %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 31[ ]*vpmovzxbw \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b4 f4 c0 1d fe ff[ ]*vpmovzxbw -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 7f[ ]*vpmovzxbw 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 00 10 00 00[ ]*vpmovzxbw 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 80[ ]*vpmovzxbw -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 e0 ef ff ff[ ]*vpmovzxbw -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b f4[ ]*vpmulhrsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 0b f4[ ]*vpmulhrsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 0b f4[ ]*vpmulhrsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 31[ ]*vpmulhrsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b4 f4 c0 1d fe ff[ ]*vpmulhrsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 7f[ ]*vpmulhrsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 00 20 00 00[ ]*vpmulhrsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 80[ ]*vpmulhrsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 c0 df ff ff[ ]*vpmulhrsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 f4[ ]*vpmulhuw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e4 f4[ ]*vpmulhuw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e4 f4[ ]*vpmulhuw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 31[ ]*vpmulhuw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b4 f4 c0 1d fe ff[ ]*vpmulhuw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 7f[ ]*vpmulhuw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 00 20 00 00[ ]*vpmulhuw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 80[ ]*vpmulhuw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 c0 df ff ff[ ]*vpmulhuw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 f4[ ]*vpmulhw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e5 f4[ ]*vpmulhw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e5 f4[ ]*vpmulhw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 31[ ]*vpmulhw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b4 f4 c0 1d fe ff[ ]*vpmulhw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 7f[ ]*vpmulhw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 00 20 00 00[ ]*vpmulhw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 80[ ]*vpmulhw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 c0 df ff ff[ ]*vpmulhw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 f4[ ]*vpmullw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d5 f4[ ]*vpmullw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d5 f4[ ]*vpmullw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 31[ ]*vpmullw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b4 f4 c0 1d fe ff[ ]*vpmullw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 7f[ ]*vpmullw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 00 20 00 00[ ]*vpmullw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 80[ ]*vpmullw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 c0 df ff ff[ ]*vpmullw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 f4[ ]*vpsadbw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 31[ ]*vpsadbw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b4 f4 c0 1d fe ff[ ]*vpsadbw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 7f[ ]*vpsadbw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 00 20 00 00[ ]*vpsadbw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 80[ ]*vpsadbw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 c0 df ff ff[ ]*vpsadbw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 f4[ ]*vpshufb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 00 f4[ ]*vpshufb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 00 f4[ ]*vpshufb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 31[ ]*vpshufb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b4 f4 c0 1d fe ff[ ]*vpshufb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 7f[ ]*vpshufb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 00 20 00 00[ ]*vpshufb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 80[ ]*vpshufb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 c0 df ff ff[ ]*vpshufb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 ab[ ]*vpshufhw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 4f 70 f5 ab[ ]*vpshufhw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe cf 70 f5 ab[ ]*vpshufhw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 7b[ ]*vpshufhw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 31 7b[ ]*vpshufhw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshufhw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 7f 7b[ ]*vpshufhw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 00 20 00 00 7b[ ]*vpshufhw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 80 7b[ ]*vpshufhw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 c0 df ff ff 7b[ ]*vpshufhw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 ab[ ]*vpshuflw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 70 f5 ab[ ]*vpshuflw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 70 f5 ab[ ]*vpshuflw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 7b[ ]*vpshuflw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 31 7b[ ]*vpshuflw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshuflw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 7f 7b[ ]*vpshuflw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 00 20 00 00 7b[ ]*vpshuflw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 80 7b[ ]*vpshuflw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 c0 df ff ff 7b[ ]*vpshuflw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 f4[ ]*vpsllw %xmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f1 f4[ ]*vpsllw %xmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 31[ ]*vpsllw \(%ecx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b4 f4 c0 1d fe ff[ ]*vpsllw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 7f[ ]*vpsllw 0x7f0\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 00 08 00 00[ ]*vpsllw 0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 80[ ]*vpsllw -0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 f0 f7 ff ff[ ]*vpsllw -0x810\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 f4[ ]*vpsraw %xmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e1 f4[ ]*vpsraw %xmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 31[ ]*vpsraw \(%ecx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b4 f4 c0 1d fe ff[ ]*vpsraw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 7f[ ]*vpsraw 0x7f0\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 00 08 00 00[ ]*vpsraw 0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 80[ ]*vpsraw -0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 f0 f7 ff ff[ ]*vpsraw -0x810\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 f4[ ]*vpsrlw %xmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d1 f4[ ]*vpsrlw %xmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 31[ ]*vpsrlw \(%ecx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b4 f4 c0 1d fe ff[ ]*vpsrlw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 7f[ ]*vpsrlw 0x7f0\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 00 08 00 00[ ]*vpsrlw 0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 80[ ]*vpsrlw -0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 f0 f7 ff ff[ ]*vpsrlw -0x810\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd ab[ ]*vpsrldq \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd 7b[ ]*vpsrldq \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 19 7b[ ]*vpsrldq \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9c f4 c0 1d fe ff 7b[ ]*vpsrldq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 7f 7b[ ]*vpsrldq \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a 00 20 00 00 7b[ ]*vpsrldq \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 80 7b[ ]*vpsrldq \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a c0 df ff ff 7b[ ]*vpsrldq \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 ab[ ]*vpsrlw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 d5 ab[ ]*vpsrlw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 d5 ab[ ]*vpsrlw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 7b[ ]*vpsrlw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 11 7b[ ]*vpsrlw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 94 f4 c0 1d fe ff 7b[ ]*vpsrlw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 7f 7b[ ]*vpsrlw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 00 20 00 00 7b[ ]*vpsrlw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 80 7b[ ]*vpsrlw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 c0 df ff ff 7b[ ]*vpsrlw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 ab[ ]*vpsraw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 e5 ab[ ]*vpsraw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 e5 ab[ ]*vpsraw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 7b[ ]*vpsraw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 21 7b[ ]*vpsraw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a4 f4 c0 1d fe ff 7b[ ]*vpsraw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 7f 7b[ ]*vpsraw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 00 20 00 00 7b[ ]*vpsraw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 80 7b[ ]*vpsraw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 c0 df ff ff 7b[ ]*vpsraw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 f4[ ]*vpsubb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f8 f4[ ]*vpsubb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f8 f4[ ]*vpsubb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 31[ ]*vpsubb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b4 f4 c0 1d fe ff[ ]*vpsubb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 7f[ ]*vpsubb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 00 20 00 00[ ]*vpsubb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 80[ ]*vpsubb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 c0 df ff ff[ ]*vpsubb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 f4[ ]*vpsubsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e8 f4[ ]*vpsubsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e8 f4[ ]*vpsubsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 31[ ]*vpsubsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b4 f4 c0 1d fe ff[ ]*vpsubsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 7f[ ]*vpsubsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 00 20 00 00[ ]*vpsubsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 80[ ]*vpsubsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 c0 df ff ff[ ]*vpsubsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 f4[ ]*vpsubsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e9 f4[ ]*vpsubsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e9 f4[ ]*vpsubsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 31[ ]*vpsubsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b4 f4 c0 1d fe ff[ ]*vpsubsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 7f[ ]*vpsubsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 00 20 00 00[ ]*vpsubsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 80[ ]*vpsubsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 c0 df ff ff[ ]*vpsubsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 f4[ ]*vpsubusb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d8 f4[ ]*vpsubusb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d8 f4[ ]*vpsubusb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 31[ ]*vpsubusb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b4 f4 c0 1d fe ff[ ]*vpsubusb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 7f[ ]*vpsubusb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 00 20 00 00[ ]*vpsubusb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 80[ ]*vpsubusb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 c0 df ff ff[ ]*vpsubusb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 f4[ ]*vpsubusw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d9 f4[ ]*vpsubusw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d9 f4[ ]*vpsubusw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 31[ ]*vpsubusw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b4 f4 c0 1d fe ff[ ]*vpsubusw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 7f[ ]*vpsubusw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 00 20 00 00[ ]*vpsubusw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 80[ ]*vpsubusw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 c0 df ff ff[ ]*vpsubusw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 f4[ ]*vpsubw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f9 f4[ ]*vpsubw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f9 f4[ ]*vpsubw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 31[ ]*vpsubw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b4 f4 c0 1d fe ff[ ]*vpsubw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 7f[ ]*vpsubw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 00 20 00 00[ ]*vpsubw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 80[ ]*vpsubw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 c0 df ff ff[ ]*vpsubw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 f4[ ]*vpunpckhbw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 68 f4[ ]*vpunpckhbw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 68 f4[ ]*vpunpckhbw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 31[ ]*vpunpckhbw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b4 f4 c0 1d fe ff[ ]*vpunpckhbw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 7f[ ]*vpunpckhbw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 00 20 00 00[ ]*vpunpckhbw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 80[ ]*vpunpckhbw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 c0 df ff ff[ ]*vpunpckhbw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 f4[ ]*vpunpckhwd %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 69 f4[ ]*vpunpckhwd %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 69 f4[ ]*vpunpckhwd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 31[ ]*vpunpckhwd \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b4 f4 c0 1d fe ff[ ]*vpunpckhwd -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 7f[ ]*vpunpckhwd 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 00 20 00 00[ ]*vpunpckhwd 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 80[ ]*vpunpckhwd -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 c0 df ff ff[ ]*vpunpckhwd -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 f4[ ]*vpunpcklbw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 60 f4[ ]*vpunpcklbw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 60 f4[ ]*vpunpcklbw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 31[ ]*vpunpcklbw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b4 f4 c0 1d fe ff[ ]*vpunpcklbw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 7f[ ]*vpunpcklbw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 00 20 00 00[ ]*vpunpcklbw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 80[ ]*vpunpcklbw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 c0 df ff ff[ ]*vpunpcklbw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 f4[ ]*vpunpcklwd %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 61 f4[ ]*vpunpcklwd %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 61 f4[ ]*vpunpcklwd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 31[ ]*vpunpcklwd \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b4 f4 c0 1d fe ff[ ]*vpunpcklwd -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 7f[ ]*vpunpcklwd 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 00 20 00 00[ ]*vpunpcklwd 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 80[ ]*vpunpcklwd -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 c0 df ff ff[ ]*vpunpcklwd -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd ab[ ]*vpslldq \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd 7b[ ]*vpslldq \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 39 7b[ ]*vpslldq \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 bc f4 c0 1d fe ff 7b[ ]*vpslldq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 7f 7b[ ]*vpslldq \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba 00 20 00 00 7b[ ]*vpslldq \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 80 7b[ ]*vpslldq \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba c0 df ff ff 7b[ ]*vpslldq \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 ab[ ]*vpsllw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 f5 ab[ ]*vpsllw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 f5 ab[ ]*vpsllw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 7b[ ]*vpsllw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 31 7b[ ]*vpsllw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b4 f4 c0 1d fe ff 7b[ ]*vpsllw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 7f 7b[ ]*vpsllw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 00 20 00 00 7b[ ]*vpsllw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 80 7b[ ]*vpsllw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 c0 df ff ff 7b[ ]*vpsllw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c f5[ ]*vpabsb %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1c f5[ ]*vpabsb %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1c f5[ ]*vpabsb %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 31[ ]*vpabsb \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b4 f4 c0 1d fe ff[ ]*vpabsb -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 7f[ ]*vpabsb 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 00 20 00 00[ ]*vpabsb 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c 72 80[ ]*vpabsb -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1c b2 c0 df ff ff[ ]*vpabsb -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d f5[ ]*vpabsw %zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 1d f5[ ]*vpabsw %zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 1d f5[ ]*vpabsw %zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 31[ ]*vpabsw \(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b4 f4 c0 1d fe ff[ ]*vpabsw -0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 7f[ ]*vpabsw 0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 00 20 00 00[ ]*vpabsw 0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d 72 80[ ]*vpabsw -0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 48 1d b2 c0 df ff ff[ ]*vpabsw -0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 f4[ ]*vpacksswb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 63 f4[ ]*vpacksswb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 63 f4[ ]*vpacksswb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 31[ ]*vpacksswb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b4 f4 c0 1d fe ff[ ]*vpacksswb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 7f[ ]*vpacksswb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 00 20 00 00[ ]*vpacksswb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 72 80[ ]*vpacksswb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 63 b2 c0 df ff ff[ ]*vpacksswb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 f4[ ]*vpackuswb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 67 f4[ ]*vpackuswb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 67 f4[ ]*vpackuswb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 31[ ]*vpackuswb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b4 f4 c0 1d fe ff[ ]*vpackuswb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 7f[ ]*vpackuswb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 00 20 00 00[ ]*vpackuswb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 72 80[ ]*vpackuswb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 67 b2 c0 df ff ff[ ]*vpackuswb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc f4[ ]*vpaddb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fc f4[ ]*vpaddb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fc f4[ ]*vpaddb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 31[ ]*vpaddb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b4 f4 c0 1d fe ff[ ]*vpaddb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 7f[ ]*vpaddb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 00 20 00 00[ ]*vpaddb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc 72 80[ ]*vpaddb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fc b2 c0 df ff ff[ ]*vpaddb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec f4[ ]*vpaddsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ec f4[ ]*vpaddsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ec f4[ ]*vpaddsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 31[ ]*vpaddsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b4 f4 c0 1d fe ff[ ]*vpaddsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 7f[ ]*vpaddsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 00 20 00 00[ ]*vpaddsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec 72 80[ ]*vpaddsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ec b2 c0 df ff ff[ ]*vpaddsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed f4[ ]*vpaddsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ed f4[ ]*vpaddsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ed f4[ ]*vpaddsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 31[ ]*vpaddsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b4 f4 c0 1d fe ff[ ]*vpaddsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 7f[ ]*vpaddsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 00 20 00 00[ ]*vpaddsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed 72 80[ ]*vpaddsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ed b2 c0 df ff ff[ ]*vpaddsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc f4[ ]*vpaddusb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dc f4[ ]*vpaddusb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dc f4[ ]*vpaddusb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 31[ ]*vpaddusb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b4 f4 c0 1d fe ff[ ]*vpaddusb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 7f[ ]*vpaddusb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 00 20 00 00[ ]*vpaddusb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc 72 80[ ]*vpaddusb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dc b2 c0 df ff ff[ ]*vpaddusb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd f4[ ]*vpaddusw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f dd f4[ ]*vpaddusw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf dd f4[ ]*vpaddusw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 31[ ]*vpaddusw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b4 f4 c0 1d fe ff[ ]*vpaddusw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 7f[ ]*vpaddusw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 00 20 00 00[ ]*vpaddusw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd 72 80[ ]*vpaddusw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 dd b2 c0 df ff ff[ ]*vpaddusw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd f4[ ]*vpaddw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f fd f4[ ]*vpaddw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf fd f4[ ]*vpaddw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 31[ ]*vpaddw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b4 f4 c0 1d fe ff[ ]*vpaddw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 7f[ ]*vpaddw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 00 20 00 00[ ]*vpaddw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd 72 80[ ]*vpaddw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 fd b2 c0 df ff ff[ ]*vpaddw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 ab[ ]*vpalignr \$0xab,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 4f 0f f4 ab[ ]*vpalignr \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 cf 0f f4 ab[ ]*vpalignr \$0xab,%zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f f4 7b[ ]*vpalignr \$0x7b,%zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 31 7b[ ]*vpalignr \$0x7b,\(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b4 f4 c0 1d fe ff 7b[ ]*vpalignr \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 7f 7b[ ]*vpalignr \$0x7b,0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 00 20 00 00 7b[ ]*vpalignr \$0x7b,0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f 72 80 7b[ ]*vpalignr \$0x7b,-0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f3 d5 48 0f b2 c0 df ff ff 7b[ ]*vpalignr \$0x7b,-0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 f4[ ]*vpavgb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e0 f4[ ]*vpavgb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e0 f4[ ]*vpavgb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 31[ ]*vpavgb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b4 f4 c0 1d fe ff[ ]*vpavgb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 7f[ ]*vpavgb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 00 20 00 00[ ]*vpavgb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 72 80[ ]*vpavgb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e0 b2 c0 df ff ff[ ]*vpavgb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 f4[ ]*vpavgw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e3 f4[ ]*vpavgw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e3 f4[ ]*vpavgw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 31[ ]*vpavgw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b4 f4 c0 1d fe ff[ ]*vpavgw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 7f[ ]*vpavgw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 00 20 00 00[ ]*vpavgw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 72 80[ ]*vpavgw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e3 b2 c0 df ff ff[ ]*vpavgw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ed[ ]*vpcmpeqb %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 74 ed[ ]*vpcmpeqb %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 29[ ]*vpcmpeqb \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 ac f4 c0 1d fe ff[ ]*vpcmpeqb -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 7f[ ]*vpcmpeqb 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa 00 20 00 00[ ]*vpcmpeqb 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 6a 80[ ]*vpcmpeqb -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 74 aa c0 df ff ff[ ]*vpcmpeqb -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ed[ ]*vpcmpeqw %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 75 ed[ ]*vpcmpeqw %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 29[ ]*vpcmpeqw \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 ac f4 c0 1d fe ff[ ]*vpcmpeqw -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 7f[ ]*vpcmpeqw 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa 00 20 00 00[ ]*vpcmpeqw 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 6a 80[ ]*vpcmpeqw -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 75 aa c0 df ff ff[ ]*vpcmpeqw -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ed[ ]*vpcmpgtb %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 64 ed[ ]*vpcmpgtb %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 29[ ]*vpcmpgtb \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 ac f4 c0 1d fe ff[ ]*vpcmpgtb -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 7f[ ]*vpcmpgtb 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa 00 20 00 00[ ]*vpcmpgtb 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 6a 80[ ]*vpcmpgtb -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 64 aa c0 df ff ff[ ]*vpcmpgtb -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ed[ ]*vpcmpgtw %zmm5,%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 65 ed[ ]*vpcmpgtw %zmm5,%zmm6,%k5\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 29[ ]*vpcmpgtw \(%ecx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 ac f4 c0 1d fe ff[ ]*vpcmpgtw -0x1e240\(%esp,%esi,8\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 7f[ ]*vpcmpgtw 0x1fc0\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa 00 20 00 00[ ]*vpcmpgtw 0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 6a 80[ ]*vpcmpgtw -0x2000\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 65 aa c0 df ff ff[ ]*vpcmpgtw -0x2040\(%edx\),%zmm6,%k5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 f4[ ]*vpmaddubsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 04 f4[ ]*vpmaddubsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 04 f4[ ]*vpmaddubsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 31[ ]*vpmaddubsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b4 f4 c0 1d fe ff[ ]*vpmaddubsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 7f[ ]*vpmaddubsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 00 20 00 00[ ]*vpmaddubsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 72 80[ ]*vpmaddubsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 04 b2 c0 df ff ff[ ]*vpmaddubsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 f4[ ]*vpmaddwd %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f5 f4[ ]*vpmaddwd %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f5 f4[ ]*vpmaddwd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 31[ ]*vpmaddwd \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b4 f4 c0 1d fe ff[ ]*vpmaddwd -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 7f[ ]*vpmaddwd 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 00 20 00 00[ ]*vpmaddwd 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 72 80[ ]*vpmaddwd -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f5 b2 c0 df ff ff[ ]*vpmaddwd -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c f4[ ]*vpmaxsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3c f4[ ]*vpmaxsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3c f4[ ]*vpmaxsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 31[ ]*vpmaxsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b4 f4 c0 1d fe ff[ ]*vpmaxsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 7f[ ]*vpmaxsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 00 20 00 00[ ]*vpmaxsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c 72 80[ ]*vpmaxsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3c b2 c0 df ff ff[ ]*vpmaxsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee f4[ ]*vpmaxsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ee f4[ ]*vpmaxsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ee f4[ ]*vpmaxsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 31[ ]*vpmaxsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b4 f4 c0 1d fe ff[ ]*vpmaxsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 7f[ ]*vpmaxsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 00 20 00 00[ ]*vpmaxsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee 72 80[ ]*vpmaxsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ee b2 c0 df ff ff[ ]*vpmaxsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de f4[ ]*vpmaxub %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f de f4[ ]*vpmaxub %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf de f4[ ]*vpmaxub %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 31[ ]*vpmaxub \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b4 f4 c0 1d fe ff[ ]*vpmaxub -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 7f[ ]*vpmaxub 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 00 20 00 00[ ]*vpmaxub 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de 72 80[ ]*vpmaxub -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 de b2 c0 df ff ff[ ]*vpmaxub -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e f4[ ]*vpmaxuw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3e f4[ ]*vpmaxuw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3e f4[ ]*vpmaxuw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 31[ ]*vpmaxuw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b4 f4 c0 1d fe ff[ ]*vpmaxuw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 7f[ ]*vpmaxuw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 00 20 00 00[ ]*vpmaxuw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e 72 80[ ]*vpmaxuw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3e b2 c0 df ff ff[ ]*vpmaxuw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 f4[ ]*vpminsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 38 f4[ ]*vpminsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 38 f4[ ]*vpminsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 31[ ]*vpminsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b4 f4 c0 1d fe ff[ ]*vpminsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 7f[ ]*vpminsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 00 20 00 00[ ]*vpminsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 72 80[ ]*vpminsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 38 b2 c0 df ff ff[ ]*vpminsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea f4[ ]*vpminsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f ea f4[ ]*vpminsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf ea f4[ ]*vpminsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 31[ ]*vpminsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b4 f4 c0 1d fe ff[ ]*vpminsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 7f[ ]*vpminsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 00 20 00 00[ ]*vpminsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea 72 80[ ]*vpminsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 ea b2 c0 df ff ff[ ]*vpminsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da f4[ ]*vpminub %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f da f4[ ]*vpminub %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf da f4[ ]*vpminub %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 31[ ]*vpminub \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b4 f4 c0 1d fe ff[ ]*vpminub -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 7f[ ]*vpminub 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 00 20 00 00[ ]*vpminub 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da 72 80[ ]*vpminub -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 da b2 c0 df ff ff[ ]*vpminub -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a f4[ ]*vpminuw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 3a f4[ ]*vpminuw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 3a f4[ ]*vpminuw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 31[ ]*vpminuw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b4 f4 c0 1d fe ff[ ]*vpminuw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 7f[ ]*vpminuw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 00 20 00 00[ ]*vpminuw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a 72 80[ ]*vpminuw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 3a b2 c0 df ff ff[ ]*vpminuw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 f5[ ]*vpmovsxbw %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 20 f5[ ]*vpmovsxbw %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 31[ ]*vpmovsxbw \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b4 f4 c0 1d fe ff[ ]*vpmovsxbw -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 7f[ ]*vpmovsxbw 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 00 10 00 00[ ]*vpmovsxbw 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 72 80[ ]*vpmovsxbw -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 20 b2 e0 ef ff ff[ ]*vpmovsxbw -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 f5[ ]*vpmovzxbw %ymm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd cf 30 f5[ ]*vpmovzxbw %ymm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 31[ ]*vpmovzxbw \(%ecx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b4 f4 c0 1d fe ff[ ]*vpmovzxbw -0x1e240\(%esp,%esi,8\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 7f[ ]*vpmovzxbw 0xfe0\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 00 10 00 00[ ]*vpmovzxbw 0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 72 80[ ]*vpmovzxbw -0x1000\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 fd 4f 30 b2 e0 ef ff ff[ ]*vpmovzxbw -0x1020\(%edx\),%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b f4[ ]*vpmulhrsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 0b f4[ ]*vpmulhrsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 0b f4[ ]*vpmulhrsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 31[ ]*vpmulhrsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b4 f4 c0 1d fe ff[ ]*vpmulhrsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 7f[ ]*vpmulhrsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 00 20 00 00[ ]*vpmulhrsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b 72 80[ ]*vpmulhrsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 0b b2 c0 df ff ff[ ]*vpmulhrsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 f4[ ]*vpmulhuw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e4 f4[ ]*vpmulhuw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e4 f4[ ]*vpmulhuw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 31[ ]*vpmulhuw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b4 f4 c0 1d fe ff[ ]*vpmulhuw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 7f[ ]*vpmulhuw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 00 20 00 00[ ]*vpmulhuw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 72 80[ ]*vpmulhuw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e4 b2 c0 df ff ff[ ]*vpmulhuw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 f4[ ]*vpmulhw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e5 f4[ ]*vpmulhw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e5 f4[ ]*vpmulhw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 31[ ]*vpmulhw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b4 f4 c0 1d fe ff[ ]*vpmulhw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 7f[ ]*vpmulhw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 00 20 00 00[ ]*vpmulhw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 72 80[ ]*vpmulhw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e5 b2 c0 df ff ff[ ]*vpmulhw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 f4[ ]*vpmullw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d5 f4[ ]*vpmullw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d5 f4[ ]*vpmullw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 31[ ]*vpmullw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b4 f4 c0 1d fe ff[ ]*vpmullw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 7f[ ]*vpmullw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 00 20 00 00[ ]*vpmullw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 72 80[ ]*vpmullw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d5 b2 c0 df ff ff[ ]*vpmullw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 f4[ ]*vpsadbw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 31[ ]*vpsadbw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b4 f4 c0 1d fe ff[ ]*vpsadbw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 7f[ ]*vpsadbw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 00 20 00 00[ ]*vpsadbw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 72 80[ ]*vpsadbw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f6 b2 c0 df ff ff[ ]*vpsadbw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 f4[ ]*vpshufb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 4f 00 f4[ ]*vpshufb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 cf 00 f4[ ]*vpshufb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 31[ ]*vpshufb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b4 f4 c0 1d fe ff[ ]*vpshufb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 7f[ ]*vpshufb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 00 20 00 00[ ]*vpshufb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 72 80[ ]*vpshufb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f2 d5 48 00 b2 c0 df ff ff[ ]*vpshufb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 ab[ ]*vpshufhw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 4f 70 f5 ab[ ]*vpshufhw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe cf 70 f5 ab[ ]*vpshufhw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 f5 7b[ ]*vpshufhw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 31 7b[ ]*vpshufhw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshufhw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 7f 7b[ ]*vpshufhw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 00 20 00 00 7b[ ]*vpshufhw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 72 80 7b[ ]*vpshufhw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 fe 48 70 b2 c0 df ff ff 7b[ ]*vpshufhw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 ab[ ]*vpshuflw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 4f 70 f5 ab[ ]*vpshuflw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff cf 70 f5 ab[ ]*vpshuflw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 f5 7b[ ]*vpshuflw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 31 7b[ ]*vpshuflw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b4 f4 c0 1d fe ff 7b[ ]*vpshuflw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 7f 7b[ ]*vpshuflw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 00 20 00 00 7b[ ]*vpshuflw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 72 80 7b[ ]*vpshuflw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 48 70 b2 c0 df ff ff 7b[ ]*vpshuflw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 f4[ ]*vpsllw %xmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f1 f4[ ]*vpsllw %xmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 31[ ]*vpsllw \(%ecx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b4 f4 c0 1d fe ff[ ]*vpsllw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 7f[ ]*vpsllw 0x7f0\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 00 08 00 00[ ]*vpsllw 0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 72 80[ ]*vpsllw -0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f1 b2 f0 f7 ff ff[ ]*vpsllw -0x810\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 f4[ ]*vpsraw %xmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e1 f4[ ]*vpsraw %xmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 31[ ]*vpsraw \(%ecx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b4 f4 c0 1d fe ff[ ]*vpsraw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 7f[ ]*vpsraw 0x7f0\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 00 08 00 00[ ]*vpsraw 0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 72 80[ ]*vpsraw -0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e1 b2 f0 f7 ff ff[ ]*vpsraw -0x810\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 f4[ ]*vpsrlw %xmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d1 f4[ ]*vpsrlw %xmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 31[ ]*vpsrlw \(%ecx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b4 f4 c0 1d fe ff[ ]*vpsrlw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 7f[ ]*vpsrlw 0x7f0\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 00 08 00 00[ ]*vpsrlw 0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 72 80[ ]*vpsrlw -0x800\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d1 b2 f0 f7 ff ff[ ]*vpsrlw -0x810\(%edx\),%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd ab[ ]*vpsrldq \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 dd 7b[ ]*vpsrldq \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 19 7b[ ]*vpsrldq \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9c f4 c0 1d fe ff 7b[ ]*vpsrldq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 7f 7b[ ]*vpsrldq \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a 00 20 00 00 7b[ ]*vpsrldq \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 5a 80 7b[ ]*vpsrldq \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 9a c0 df ff ff 7b[ ]*vpsrldq \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 ab[ ]*vpsrlw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 d5 ab[ ]*vpsrlw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 d5 ab[ ]*vpsrlw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 d5 7b[ ]*vpsrlw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 11 7b[ ]*vpsrlw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 94 f4 c0 1d fe ff 7b[ ]*vpsrlw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 7f 7b[ ]*vpsrlw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 00 20 00 00 7b[ ]*vpsrlw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 52 80 7b[ ]*vpsrlw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 92 c0 df ff ff 7b[ ]*vpsrlw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 ab[ ]*vpsraw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 e5 ab[ ]*vpsraw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 e5 ab[ ]*vpsraw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 e5 7b[ ]*vpsraw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 21 7b[ ]*vpsraw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a4 f4 c0 1d fe ff 7b[ ]*vpsraw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 7f 7b[ ]*vpsraw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 00 20 00 00 7b[ ]*vpsraw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 62 80 7b[ ]*vpsraw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 a2 c0 df ff ff 7b[ ]*vpsraw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 f4[ ]*vpsubb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f8 f4[ ]*vpsubb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f8 f4[ ]*vpsubb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 31[ ]*vpsubb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b4 f4 c0 1d fe ff[ ]*vpsubb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 7f[ ]*vpsubb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 00 20 00 00[ ]*vpsubb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 72 80[ ]*vpsubb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f8 b2 c0 df ff ff[ ]*vpsubb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 f4[ ]*vpsubsb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e8 f4[ ]*vpsubsb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e8 f4[ ]*vpsubsb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 31[ ]*vpsubsb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b4 f4 c0 1d fe ff[ ]*vpsubsb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 7f[ ]*vpsubsb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 00 20 00 00[ ]*vpsubsb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 72 80[ ]*vpsubsb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e8 b2 c0 df ff ff[ ]*vpsubsb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 f4[ ]*vpsubsw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f e9 f4[ ]*vpsubsw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf e9 f4[ ]*vpsubsw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 31[ ]*vpsubsw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b4 f4 c0 1d fe ff[ ]*vpsubsw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 7f[ ]*vpsubsw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 00 20 00 00[ ]*vpsubsw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 72 80[ ]*vpsubsw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 e9 b2 c0 df ff ff[ ]*vpsubsw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 f4[ ]*vpsubusb %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d8 f4[ ]*vpsubusb %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d8 f4[ ]*vpsubusb %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 31[ ]*vpsubusb \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b4 f4 c0 1d fe ff[ ]*vpsubusb -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 7f[ ]*vpsubusb 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 00 20 00 00[ ]*vpsubusb 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 72 80[ ]*vpsubusb -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d8 b2 c0 df ff ff[ ]*vpsubusb -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 f4[ ]*vpsubusw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f d9 f4[ ]*vpsubusw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf d9 f4[ ]*vpsubusw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 31[ ]*vpsubusw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b4 f4 c0 1d fe ff[ ]*vpsubusw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 7f[ ]*vpsubusw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 00 20 00 00[ ]*vpsubusw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 72 80[ ]*vpsubusw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 d9 b2 c0 df ff ff[ ]*vpsubusw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 f4[ ]*vpsubw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f f9 f4[ ]*vpsubw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf f9 f4[ ]*vpsubw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 31[ ]*vpsubw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b4 f4 c0 1d fe ff[ ]*vpsubw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 7f[ ]*vpsubw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 00 20 00 00[ ]*vpsubw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 72 80[ ]*vpsubw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 f9 b2 c0 df ff ff[ ]*vpsubw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 f4[ ]*vpunpckhbw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 68 f4[ ]*vpunpckhbw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 68 f4[ ]*vpunpckhbw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 31[ ]*vpunpckhbw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b4 f4 c0 1d fe ff[ ]*vpunpckhbw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 7f[ ]*vpunpckhbw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 00 20 00 00[ ]*vpunpckhbw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 72 80[ ]*vpunpckhbw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 68 b2 c0 df ff ff[ ]*vpunpckhbw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 f4[ ]*vpunpckhwd %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 69 f4[ ]*vpunpckhwd %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 69 f4[ ]*vpunpckhwd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 31[ ]*vpunpckhwd \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b4 f4 c0 1d fe ff[ ]*vpunpckhwd -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 7f[ ]*vpunpckhwd 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 00 20 00 00[ ]*vpunpckhwd 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 72 80[ ]*vpunpckhwd -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 69 b2 c0 df ff ff[ ]*vpunpckhwd -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 f4[ ]*vpunpcklbw %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 60 f4[ ]*vpunpcklbw %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 60 f4[ ]*vpunpcklbw %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 31[ ]*vpunpcklbw \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b4 f4 c0 1d fe ff[ ]*vpunpcklbw -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 7f[ ]*vpunpcklbw 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 00 20 00 00[ ]*vpunpcklbw 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 72 80[ ]*vpunpcklbw -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 60 b2 c0 df ff ff[ ]*vpunpcklbw -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 f4[ ]*vpunpcklwd %zmm4,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 4f 61 f4[ ]*vpunpcklwd %zmm4,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 cf 61 f4[ ]*vpunpcklwd %zmm4,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 31[ ]*vpunpcklwd \(%ecx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b4 f4 c0 1d fe ff[ ]*vpunpcklwd -0x1e240\(%esp,%esi,8\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 7f[ ]*vpunpcklwd 0x1fc0\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 00 20 00 00[ ]*vpunpcklwd 0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 72 80[ ]*vpunpcklwd -0x2000\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 d5 48 61 b2 c0 df ff ff[ ]*vpunpcklwd -0x2040\(%edx\),%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd ab[ ]*vpslldq \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 fd 7b[ ]*vpslldq \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 39 7b[ ]*vpslldq \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 bc f4 c0 1d fe ff 7b[ ]*vpslldq \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 7f 7b[ ]*vpslldq \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba 00 20 00 00 7b[ ]*vpslldq \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 7a 80 7b[ ]*vpslldq \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 73 ba c0 df ff ff 7b[ ]*vpslldq \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 ab[ ]*vpsllw \$0xab,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 4f 71 f5 ab[ ]*vpsllw \$0xab,%zmm5,%zmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd cf 71 f5 ab[ ]*vpsllw \$0xab,%zmm5,%zmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 f5 7b[ ]*vpsllw \$0x7b,%zmm5,%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 31 7b[ ]*vpsllw \$0x7b,\(%ecx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b4 f4 c0 1d fe ff 7b[ ]*vpsllw \$0x7b,-0x1e240\(%esp,%esi,8\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 7f 7b[ ]*vpsllw \$0x7b,0x1fc0\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 00 20 00 00 7b[ ]*vpsllw \$0x7b,0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 72 80 7b[ ]*vpsllw \$0x7b,-0x2000\(%edx\),%zmm6
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 cd 48 71 b2 c0 df ff ff 7b[ ]*vpsllw \$0x7b,-0x2040\(%edx\),%zmm6
|
||||
#pass
|
||||
1602
gas/testsuite/gas/i386/avx512bw.d
Normal file
1602
gas/testsuite/gas/i386/avx512bw.d
Normal file
File diff suppressed because it is too large
Load diff
1597
gas/testsuite/gas/i386/avx512bw.s
Normal file
1597
gas/testsuite/gas/i386/avx512bw.s
Normal file
File diff suppressed because it is too large
Load diff
2632
gas/testsuite/gas/i386/avx512bw_vl-intel.d
Normal file
2632
gas/testsuite/gas/i386/avx512bw_vl-intel.d
Normal file
File diff suppressed because it is too large
Load diff
76
gas/testsuite/gas/i386/avx512bw_vl-opts-intel.d
Normal file
76
gas/testsuite/gas/i386/avx512bw_vl-opts-intel.d
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel -Msuffix
|
||||
#name: i386 AVX512BW/VL opts insns (Intel disassembly)
|
||||
#source: avx512bw_vl-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s xmm6\{k7\}\{z\},xmm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s ymm6\{k7\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 ymm6\{k7\}\{z\},ymm5
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s ymm6\{k7\}\{z\},ymm5
|
||||
#pass
|
||||
76
gas/testsuite/gas/i386/avx512bw_vl-opts.d
Normal file
76
gas/testsuite/gas/i386/avx512bw_vl-opts.d
Normal file
|
|
@ -0,0 +1,76 @@
|
|||
#as:
|
||||
#objdump: -dw -Msuffix
|
||||
#name: i386 AVX512BW/VL opts insns
|
||||
#source: avx512bw_vl-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 6f f5[ ]*vmovdqu8 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 6f f5[ ]*vmovdqu8 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 7f af 7f ee[ ]*vmovdqu8\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 6f f5[ ]*vmovdqu16 %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm5,%xmm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 6f f5[ ]*vmovdqu16 %ymm5,%ymm6\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 f1 ff af 7f ee[ ]*vmovdqu16\.s %ymm5,%ymm6\{%k7\}\{z\}
|
||||
#pass
|
||||
71
gas/testsuite/gas/i386/avx512bw_vl-opts.s
Normal file
71
gas/testsuite/gas/i386/avx512bw_vl-opts.s
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
# Check 32bit AVX512{BW,VL} swap instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vmovdqu8 %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm5, %xmm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm5, %xmm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm5, %ymm6{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm5, %ymm6{%k7}{z} # AVX512{BW,VL}
|
||||
|
||||
.intel_syntax noprefix
|
||||
vmovdqu8 xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm6{k7}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm6{k7}{z}, xmm5 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm6{k7}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm6{k7}{z}, ymm5 # AVX512{BW,VL}
|
||||
1679
gas/testsuite/gas/i386/avx512bw_vl-wig.s
Normal file
1679
gas/testsuite/gas/i386/avx512bw_vl-wig.s
Normal file
File diff suppressed because it is too large
Load diff
1684
gas/testsuite/gas/i386/avx512bw_vl-wig1-intel.d
Normal file
1684
gas/testsuite/gas/i386/avx512bw_vl-wig1-intel.d
Normal file
File diff suppressed because it is too large
Load diff
1684
gas/testsuite/gas/i386/avx512bw_vl-wig1.d
Normal file
1684
gas/testsuite/gas/i386/avx512bw_vl-wig1.d
Normal file
File diff suppressed because it is too large
Load diff
2632
gas/testsuite/gas/i386/avx512bw_vl.d
Normal file
2632
gas/testsuite/gas/i386/avx512bw_vl.d
Normal file
File diff suppressed because it is too large
Load diff
2627
gas/testsuite/gas/i386/avx512bw_vl.s
Normal file
2627
gas/testsuite/gas/i386/avx512bw_vl.s
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -285,6 +285,18 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
|
|||
run_dump_test "avx512f_vl"
|
||||
run_dump_test "avx512cd_vl-intel"
|
||||
run_dump_test "avx512cd_vl"
|
||||
run_dump_test "avx512bw-intel"
|
||||
run_dump_test "avx512bw-opts-intel"
|
||||
run_dump_test "avx512bw-opts"
|
||||
run_dump_test "avx512bw-wig1-intel"
|
||||
run_dump_test "avx512bw-wig1"
|
||||
run_dump_test "avx512bw"
|
||||
run_dump_test "avx512bw_vl-intel"
|
||||
run_dump_test "avx512bw_vl-opts-intel"
|
||||
run_dump_test "avx512bw_vl-opts"
|
||||
run_dump_test "avx512bw_vl-wig1-intel"
|
||||
run_dump_test "avx512bw_vl-wig1"
|
||||
run_dump_test "avx512bw_vl"
|
||||
run_dump_test "disassem"
|
||||
|
||||
# These tests require support for 8 and 16 bit relocs,
|
||||
|
|
@ -593,6 +605,18 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
|
|||
run_dump_test "x86-64-avx512f_vl"
|
||||
run_dump_test "x86-64-avx512cd_vl-intel"
|
||||
run_dump_test "x86-64-avx512cd_vl"
|
||||
run_dump_test "x86-64-avx512bw-intel"
|
||||
run_dump_test "x86-64-avx512bw-opts-intel"
|
||||
run_dump_test "x86-64-avx512bw-opts"
|
||||
run_dump_test "x86-64-avx512bw-wig1-intel"
|
||||
run_dump_test "x86-64-avx512bw-wig1"
|
||||
run_dump_test "x86-64-avx512bw"
|
||||
run_dump_test "x86-64-avx512bw_vl-intel"
|
||||
run_dump_test "x86-64-avx512bw_vl-opts-intel"
|
||||
run_dump_test "x86-64-avx512bw_vl-opts"
|
||||
run_dump_test "x86-64-avx512bw_vl-wig1-intel"
|
||||
run_dump_test "x86-64-avx512bw_vl-wig1"
|
||||
run_dump_test "x86-64-avx512bw_vl"
|
||||
|
||||
if { ![istarget "*-*-aix*"]
|
||||
&& ![istarget "*-*-beos*"]
|
||||
|
|
|
|||
1706
gas/testsuite/gas/i386/x86-64-avx512bw-intel.d
Normal file
1706
gas/testsuite/gas/i386/x86-64-avx512bw-intel.d
Normal file
File diff suppressed because it is too large
Load diff
84
gas/testsuite/gas/i386/x86-64-avx512bw-opts-intel.d
Normal file
84
gas/testsuite/gas/i386/x86-64-avx512bw-opts-intel.d
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel -Msuffix
|
||||
#name: x86_64 AVX512BW opts insns (Intel disassembly)
|
||||
#source: x86-64-avx512bw-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s rax,xmm29,0xab
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s rax,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s r8,xmm29,0x7b
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s zmm30,zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s zmm30\{k7\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 zmm30\{k7\}\{z\},zmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s zmm30\{k7\}\{z\},zmm29
|
||||
#pass
|
||||
84
gas/testsuite/gas/i386/x86-64-avx512bw-opts.d
Normal file
84
gas/testsuite/gas/i386/x86-64-avx512bw-opts.d
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
#as:
|
||||
#objdump: -dw -Msuffix
|
||||
#name: x86_64 AVX512BW opts insns
|
||||
#source: x86-64-avx512bw-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 ab[ ]*vpextrw \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 ab[ ]*vpextrw\.s \$0xab,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 91 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 63 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%rax
|
||||
[ ]*[a-f0-9]+:[ ]*62 11 fd 08 c5 c5 7b[ ]*vpextrw \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 43 fd 08 15 e8 7b[ ]*vpextrw\.s \$0x7b,%xmm29,%r8
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 6f f5[ ]*vmovdqu8 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 48 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 4f 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 6f f5[ ]*vmovdqu8 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f cf 7f ee[ ]*vmovdqu8\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 6f f5[ ]*vmovdqu16 %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 48 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 4f 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 6f f5[ ]*vmovdqu16 %zmm29,%zmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff cf 7f ee[ ]*vmovdqu16\.s %zmm29,%zmm30\{%k7\}\{z\}
|
||||
#pass
|
||||
79
gas/testsuite/gas/i386/x86-64-avx512bw-opts.s
Normal file
79
gas/testsuite/gas/i386/x86-64-avx512bw-opts.s
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
# Check 64bit AVX512BW swap instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vpextrw $0xab, %xmm29, %rax # AVX512BW
|
||||
vpextrw.s $0xab, %xmm29, %rax # AVX512BW
|
||||
vpextrw $123, %xmm29, %rax # AVX512BW
|
||||
vpextrw.s $123, %xmm29, %rax # AVX512BW
|
||||
vpextrw $123, %xmm29, %r8 # AVX512BW
|
||||
vpextrw.s $123, %xmm29, %r8 # AVX512BW
|
||||
vpextrw $0xab, %xmm29, %rax # AVX512BW
|
||||
vpextrw.s $0xab, %xmm29, %rax # AVX512BW
|
||||
vpextrw $123, %xmm29, %rax # AVX512BW
|
||||
vpextrw.s $123, %xmm29, %rax # AVX512BW
|
||||
vpextrw $123, %xmm29, %r8 # AVX512BW
|
||||
vpextrw.s $123, %xmm29, %r8 # AVX512BW
|
||||
vmovdqu8 %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu8.s %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu8 %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu8.s %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu8 %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
vmovdqu8.s %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
vmovdqu8 %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu8.s %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu8 %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu8.s %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu8 %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
vmovdqu8.s %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
vmovdqu16 %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu16.s %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu16 %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu16.s %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu16 %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
vmovdqu16.s %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
vmovdqu16 %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu16.s %zmm29, %zmm30 # AVX512BW
|
||||
vmovdqu16 %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu16.s %zmm29, %zmm30{%k7} # AVX512BW
|
||||
vmovdqu16 %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
vmovdqu16.s %zmm29, %zmm30{%k7}{z} # AVX512BW
|
||||
|
||||
.intel_syntax noprefix
|
||||
vpextrw rax, xmm29, 0xab # AVX512BW
|
||||
vpextrw.s rax, xmm29, 0xab # AVX512BW
|
||||
vpextrw rax, xmm29, 123 # AVX512BW
|
||||
vpextrw.s rax, xmm29, 123 # AVX512BW
|
||||
vpextrw r8, xmm29, 123 # AVX512BW
|
||||
vpextrw.s r8, xmm29, 123 # AVX512BW
|
||||
vpextrw rax, xmm29, 0xab # AVX512BW
|
||||
vpextrw.s rax, xmm29, 0xab # AVX512BW
|
||||
vpextrw rax, xmm29, 123 # AVX512BW
|
||||
vpextrw.s rax, xmm29, 123 # AVX512BW
|
||||
vpextrw r8, xmm29, 123 # AVX512BW
|
||||
vpextrw.s r8, xmm29, 123 # AVX512BW
|
||||
vmovdqu8 zmm30, zmm29 # AVX512BW
|
||||
vmovdqu8.s zmm30, zmm29 # AVX512BW
|
||||
vmovdqu8 zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu8.s zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu8 zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
vmovdqu8.s zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
vmovdqu8 zmm30, zmm29 # AVX512BW
|
||||
vmovdqu8.s zmm30, zmm29 # AVX512BW
|
||||
vmovdqu8 zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu8.s zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu8 zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
vmovdqu8.s zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
vmovdqu16 zmm30, zmm29 # AVX512BW
|
||||
vmovdqu16.s zmm30, zmm29 # AVX512BW
|
||||
vmovdqu16 zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu16.s zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu16 zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
vmovdqu16.s zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
vmovdqu16 zmm30, zmm29 # AVX512BW
|
||||
vmovdqu16.s zmm30, zmm29 # AVX512BW
|
||||
vmovdqu16 zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu16.s zmm30{k7}, zmm29 # AVX512BW
|
||||
vmovdqu16 zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
vmovdqu16.s zmm30{k7}{z}, zmm29 # AVX512BW
|
||||
1069
gas/testsuite/gas/i386/x86-64-avx512bw-wig.s
Normal file
1069
gas/testsuite/gas/i386/x86-64-avx512bw-wig.s
Normal file
File diff suppressed because it is too large
Load diff
1074
gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
Normal file
1074
gas/testsuite/gas/i386/x86-64-avx512bw-wig1-intel.d
Normal file
File diff suppressed because it is too large
Load diff
1074
gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
Normal file
1074
gas/testsuite/gas/i386/x86-64-avx512bw-wig1.d
Normal file
File diff suppressed because it is too large
Load diff
1706
gas/testsuite/gas/i386/x86-64-avx512bw.d
Normal file
1706
gas/testsuite/gas/i386/x86-64-avx512bw.d
Normal file
File diff suppressed because it is too large
Load diff
1701
gas/testsuite/gas/i386/x86-64-avx512bw.s
Normal file
1701
gas/testsuite/gas/i386/x86-64-avx512bw.s
Normal file
File diff suppressed because it is too large
Load diff
3056
gas/testsuite/gas/i386/x86-64-avx512bw_vl-intel.d
Normal file
3056
gas/testsuite/gas/i386/x86-64-avx512bw_vl-intel.d
Normal file
File diff suppressed because it is too large
Load diff
108
gas/testsuite/gas/i386/x86-64-avx512bw_vl-opts-intel.d
Normal file
108
gas/testsuite/gas/i386/x86-64-avx512bw_vl-opts-intel.d
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
#as:
|
||||
#objdump: -dw -Mintel -Msuffix
|
||||
#name: x86_64 AVX512BW/VL opts insns (Intel disassembly)
|
||||
#source: x86-64-avx512bw_vl-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s xmm30,xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s xmm30\{k7\}\{z\},xmm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s ymm30,ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s ymm30\{k7\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 ymm30\{k7\}\{z\},ymm29
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s ymm30\{k7\}\{z\},ymm29
|
||||
#pass
|
||||
108
gas/testsuite/gas/i386/x86-64-avx512bw_vl-opts.d
Normal file
108
gas/testsuite/gas/i386/x86-64-avx512bw_vl-opts.d
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
#as:
|
||||
#objdump: -dw -Msuffix
|
||||
#name: x86_64 AVX512BW/VL opts insns
|
||||
#source: x86-64-avx512bw_vl-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 6f f5[ ]*vmovdqu8 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 08 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 0f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 6f f5[ ]*vmovdqu8 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 8f 7f ee[ ]*vmovdqu8\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 6f f5[ ]*vmovdqu8 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 28 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f 2f 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 6f f5[ ]*vmovdqu8 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 7f af 7f ee[ ]*vmovdqu8\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 6f f5[ ]*vmovdqu16 %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 08 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 0f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 6f f5[ ]*vmovdqu16 %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 8f 7f ee[ ]*vmovdqu16\.s %xmm29,%xmm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 6f f5[ ]*vmovdqu16 %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 28 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff 2f 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 6f f5[ ]*vmovdqu16 %ymm29,%ymm30\{%k7\}\{z\}
|
||||
[ ]*[a-f0-9]+:[ ]*62 01 ff af 7f ee[ ]*vmovdqu16\.s %ymm29,%ymm30\{%k7\}\{z\}
|
||||
#pass
|
||||
103
gas/testsuite/gas/i386/x86-64-avx512bw_vl-opts.s
Normal file
103
gas/testsuite/gas/i386/x86-64-avx512bw_vl-opts.s
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
# Check 64bit AVX512{BW,VL} swap instructions
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
vmovdqu8 %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu8 %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu8.s %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm29, %xmm30 # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm29, %xmm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %xmm29, %xmm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm29, %ymm30 # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm29, %ymm30{%k7} # AVX512{BW,VL}
|
||||
vmovdqu16 %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
vmovdqu16.s %ymm29, %ymm30{%k7}{z} # AVX512{BW,VL}
|
||||
|
||||
.intel_syntax noprefix
|
||||
vmovdqu8 xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8 xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8 ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu8.s ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm30, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm30{k7}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16 xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s xmm30{k7}{z}, xmm29 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm30, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm30{k7}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16 ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
vmovdqu16.s ymm30{k7}{z}, ymm29 # AVX512{BW,VL}
|
||||
1979
gas/testsuite/gas/i386/x86-64-avx512bw_vl-wig.s
Normal file
1979
gas/testsuite/gas/i386/x86-64-avx512bw_vl-wig.s
Normal file
File diff suppressed because it is too large
Load diff
1984
gas/testsuite/gas/i386/x86-64-avx512bw_vl-wig1-intel.d
Normal file
1984
gas/testsuite/gas/i386/x86-64-avx512bw_vl-wig1-intel.d
Normal file
File diff suppressed because it is too large
Load diff
1984
gas/testsuite/gas/i386/x86-64-avx512bw_vl-wig1.d
Normal file
1984
gas/testsuite/gas/i386/x86-64-avx512bw_vl-wig1.d
Normal file
File diff suppressed because it is too large
Load diff
3056
gas/testsuite/gas/i386/x86-64-avx512bw_vl.d
Normal file
3056
gas/testsuite/gas/i386/x86-64-avx512bw_vl.d
Normal file
File diff suppressed because it is too large
Load diff
3051
gas/testsuite/gas/i386/x86-64-avx512bw_vl.s
Normal file
3051
gas/testsuite/gas/i386/x86-64-avx512bw_vl.s
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -1,3 +1,77 @@
|
|||
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
|
||||
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
||||
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
||||
Sergey Lega <sergey.s.lega@intel.com>
|
||||
Anna Tikhonova <anna.tikhonova@intel.com>
|
||||
Ilya Tocar <ilya.tocar@intel.com>
|
||||
Andrey Turetskiy <andrey.turetskiy@intel.com>
|
||||
Ilya Verbin <ilya.verbin@intel.com>
|
||||
Kirill Yukhin <kirill.yukhin@intel.com>
|
||||
Michael Zolotukhin <michael.v.zolotukhin@intel.com>
|
||||
|
||||
* i386-dis-evex.h: Add new instructions (prefixes bellow).
|
||||
* i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
|
||||
(enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
|
||||
(PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
|
||||
PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
|
||||
PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
|
||||
PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
|
||||
PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
|
||||
PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
|
||||
PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
|
||||
PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
|
||||
PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
|
||||
PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
|
||||
PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
|
||||
PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
|
||||
PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
|
||||
PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
|
||||
PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
|
||||
PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
|
||||
PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
|
||||
PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
|
||||
PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
|
||||
PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
|
||||
(VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
|
||||
VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
|
||||
VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
|
||||
VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
|
||||
VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
|
||||
VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
|
||||
VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
|
||||
VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
|
||||
VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
|
||||
VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
|
||||
VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
|
||||
(VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
|
||||
EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
|
||||
EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
|
||||
EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
|
||||
EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
|
||||
EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
|
||||
EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
|
||||
(prefix_table): Add entries for new instructions.
|
||||
(vex_table) : Ditto.
|
||||
(vex_len_table): Ditto.
|
||||
(vex_w_table): Ditto.
|
||||
(intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
|
||||
mask_bd_mode handling.
|
||||
(OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
|
||||
handling.
|
||||
(OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
|
||||
handling.
|
||||
(OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
|
||||
(OP_EX): Add dqw_swap_mode handling.
|
||||
(OP_VEX): Add mask_bd_mode handling.
|
||||
(OP_Mask): Add mask_bd_mode handling.
|
||||
* i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
|
||||
(cpu_flags): Add CpuAVX512BW.
|
||||
* i386-init.h: Regenerated.
|
||||
* i386-opc.h (CpuAVX512BW): New.
|
||||
(i386_cpu_flags): Add cpuavx512bw.
|
||||
* i386-opc.tbl: Add AVX512BW instructions.
|
||||
* i386-tbl.h: Regenerate.
|
||||
|
||||
2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
|
||||
Alexander Ivchenko <alexander.ivchenko@intel.com>
|
||||
Maxim Kuznetsov <maxim.kuznetsov@intel.com>
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -231,6 +231,8 @@ static initializer cpu_flag_init[] =
|
|||
"CpuPREFETCHWT1" },
|
||||
{ "CPU_SE1_FLAGS",
|
||||
"CpuSE1" },
|
||||
{ "CPU_AVX512BW_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512BW" },
|
||||
{ "CPU_AVX512VL_FLAGS",
|
||||
"CpuMMX|CpuSSE|CpuSSE2|CpuSSE3|CpuSSSE3|CpuSSE4_1|CpuSSE4_2|CpuAVX|CpuAVX2|CpuAVX512F|CpuAVX512VL" },
|
||||
};
|
||||
|
|
@ -382,6 +384,7 @@ static bitfield cpu_flags[] =
|
|||
BITFIELD (CpuAVX512ER),
|
||||
BITFIELD (CpuAVX512PF),
|
||||
BITFIELD (CpuAVX512VL),
|
||||
BITFIELD (CpuAVX512BW),
|
||||
BITFIELD (CpuL1OM),
|
||||
BITFIELD (CpuK1OM),
|
||||
BITFIELD (CpuSSE4a),
|
||||
|
|
|
|||
|
|
@ -20,579 +20,585 @@
|
|||
|
||||
#define CPU_UNKNOWN_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_GENERIC32_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_GENERIC64_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NONE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I186_FLAGS \
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I286_FLAGS \
|
||||
{ { 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I386_FLAGS \
|
||||
{ { 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I486_FLAGS \
|
||||
{ { 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I586_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_I686_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PENTIUMPRO_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 1, 1, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_P4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOCONA_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CORE2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_COREI7_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K6_2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ATHLON_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_K8_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AMDFAM10_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 1, 1, 0, 1, 1, 1, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER3_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BDVER4_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER1_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BTVER2_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 1, \
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
1, 1, 1, 0, 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_8087_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_287_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_387_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY87_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSH_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_NOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SYSCALL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSSE3_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4_2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_SSE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVEOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PCLMUL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FMA4_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XOP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LWP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BMI_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_TBM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MOVBE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CX16_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDTSCP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_EPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_FSGSBASE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDRND_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_F16C_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_BMI2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_LZCNT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_HLE_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RTM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_INVPCID_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_VMFUNC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_3DNOWA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PADLOCK_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SVME_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SSE4A_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ABM_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX2_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512F_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512CD_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512ER_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512PF_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_ANY_AVX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_L1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_K1OM_FLAGS \
|
||||
{ { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1 } }
|
||||
|
||||
#define CPU_ADX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_RDSEED_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PRFCHW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SMAP_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_MPX_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SHA_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_CLFLUSHOPT_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVES_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_XSAVEC_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_PREFETCHWT1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_SE1_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512BW_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
#define CPU_AVX512VL_FLAGS \
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 1, \
|
||||
0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
|
||||
|
||||
|
||||
#define OPERAND_TYPE_NONE \
|
||||
|
|
|
|||
|
|
@ -104,6 +104,8 @@ enum
|
|||
CpuAVX512PF,
|
||||
/* Intel AVX-512 VL Instructions support required. */
|
||||
CpuAVX512VL,
|
||||
/* Intel AVX-512 BW Instructions support required. */
|
||||
CpuAVX512BW,
|
||||
/* Intel L1OM support required */
|
||||
CpuL1OM,
|
||||
/* Intel K1OM support required */
|
||||
|
|
@ -239,6 +241,7 @@ typedef union i386_cpu_flags
|
|||
unsigned int cpuavx512er:1;
|
||||
unsigned int cpuavx512pf:1;
|
||||
unsigned int cpuavx512vl:1;
|
||||
unsigned int cpuavx512bw:1;
|
||||
unsigned int cpul1om:1;
|
||||
unsigned int cpuk1om:1;
|
||||
unsigned int cpuxsave:1;
|
||||
|
|
|
|||
|
|
@ -5285,3 +5285,388 @@ vplzcntq, 2, 0x6644, None, 1, CpuAVX512CD|CpuAVX512VL, Modrm|EVex=2|Masking=3|Ve
|
|||
vplzcntq, 2, 0x6644, None, 1, CpuAVX512CD|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=2|VecESize=1|Broadcast=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Qword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
|
||||
// AVX512VL and AVX512CD instructions end.
|
||||
|
||||
// AVX512BW instructions end.
|
||||
|
||||
kaddd, 3, 0x664A, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kandd, 3, 0x6641, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kandnd, 3, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kmovd, 2, 0x6690, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMask }
|
||||
kmovd, 2, 0x6691, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
knotd, 2, 0x6644, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
|
||||
kord, 3, 0x6645, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kortestd, 2, 0x6698, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
|
||||
ktestd, 2, 0x6699, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
|
||||
kxnord, 3, 0x6646, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kxord, 3, 0x6647, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
|
||||
kaddq, 3, 0x4A, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kandnq, 3, 0x42, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kandq, 3, 0x41, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kmovq, 2, 0x90, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegMask }
|
||||
kmovq, 2, 0x91, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
knotq, 2, 0x44, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
|
||||
korq, 3, 0x45, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kortestq, 2, 0x98, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
|
||||
ktestq, 2, 0x99, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
|
||||
kunpckdq, 3, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kunpckwd, 3, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kxnorq, 3, 0x46, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
kxorq, 3, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
|
||||
|
||||
kmovd, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
|
||||
kmovd, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
|
||||
kmovq, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, RegMask }
|
||||
kmovq, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg64 }
|
||||
|
||||
kshiftld, 3, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
|
||||
kshiftlq, 3, 0x6633, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
|
||||
kshiftrd, 3, 0x6631, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
|
||||
kshiftrq, 3, 0x6631, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=2|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask }
|
||||
|
||||
vdbpsadbw, 4, 0x6642, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vdbpsadbw, 4, 0x6642, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vdbpsadbw, 4, 0x6642, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|S|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegZMM }
|
||||
vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
|
||||
vmovdqu16, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
|
||||
vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegZMM|RegMem }
|
||||
vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
|
||||
vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
|
||||
|
||||
vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vmovdqu16, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
|
||||
vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
|
||||
vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW, Modrm|S|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegZMM }
|
||||
vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|S|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
|
||||
vmovdqu8, 2, 0xF26F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|S|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM }
|
||||
vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegZMM|RegMem }
|
||||
vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
|
||||
vmovdqu8, 2, 0xF27F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegYMM|RegMem }
|
||||
|
||||
vpabsb, 2, 0x661C, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpabsb, 2, 0x661C, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpabsb, 2, 0x661C, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpmaxsb, 3, 0x663C, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmaxsb, 3, 0x663C, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmaxsb, 3, 0x663C, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpminsb, 3, 0x6638, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpminsb, 3, 0x6638, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpminsb, 3, 0x6638, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpshufb, 3, 0x6600, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpshufb, 3, 0x6600, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpshufb, 3, 0x6600, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpabsw, 2, 0x661D, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpabsw, 2, 0x661D, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpabsw, 2, 0x661D, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmaddubsw, 3, 0x6604, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmaxuw, 3, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmaxuw, 3, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmaxuw, 3, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpminuw, 3, 0x663A, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpminuw, 3, 0x663A, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpminuw, 3, 0x663A, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmulhrsw, 3, 0x660B, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmulhrsw, 3, 0x660B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmulhrsw, 3, 0x660B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpackssdw, 3, 0x666B, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpackssdw, 3, 0x666B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpackssdw, 3, 0x666B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpacksswb, 3, 0x6663, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpacksswb, 3, 0x6663, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpacksswb, 3, 0x6663, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpackuswb, 3, 0x6667, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpackuswb, 3, 0x6667, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpackuswb, 3, 0x6667, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpackusdw, 3, 0x662B, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|Dword|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpackusdw, 3, 0x662B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpackusdw, 3, 0x662B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Broadcast=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpaddb, 3, 0x66FC, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpaddb, 3, 0x66FC, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpaddb, 3, 0x66FC, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpaddsb, 3, 0x66EC, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpaddsb, 3, 0x66EC, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpaddsb, 3, 0x66EC, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpaddusb, 3, 0x66DC, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpaddusb, 3, 0x66DC, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpaddusb, 3, 0x66DC, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpavgb, 3, 0x66E0, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpavgb, 3, 0x66E0, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpavgb, 3, 0x66E0, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmaxub, 3, 0x66DE, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmaxub, 3, 0x66DE, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmaxub, 3, 0x66DE, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpminub, 3, 0x66DA, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpminub, 3, 0x66DA, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpminub, 3, 0x66DA, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsubb, 3, 0x66F8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsubsb, 3, 0x66E8, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsubsb, 3, 0x66E8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsubsb, 3, 0x66E8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsubusb, 3, 0x66D8, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsubusb, 3, 0x66D8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsubusb, 3, 0x66D8, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpunpckhbw, 3, 0x6668, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpunpckhbw, 3, 0x6668, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpunpckhbw, 3, 0x6668, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpunpcklbw, 3, 0x6660, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpunpcklbw, 3, 0x6660, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpunpcklbw, 3, 0x6660, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpaddsw, 3, 0x66ED, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpaddsw, 3, 0x66ED, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpaddsw, 3, 0x66ED, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpaddusw, 3, 0x66DD, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpaddusw, 3, 0x66DD, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpaddusw, 3, 0x66DD, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpaddw, 3, 0x66FD, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpaddw, 3, 0x66FD, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpaddw, 3, 0x66FD, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpavgw, 3, 0x66E3, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpavgw, 3, 0x66E3, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpavgw, 3, 0x66E3, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmaxsw, 3, 0x66EE, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmaxsw, 3, 0x66EE, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmaxsw, 3, 0x66EE, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpminsw, 3, 0x66EA, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpminsw, 3, 0x66EA, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpminsw, 3, 0x66EA, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmulhuw, 3, 0x66E4, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmulhuw, 3, 0x66E4, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmulhuw, 3, 0x66E4, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmulhw, 3, 0x66E5, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmulhw, 3, 0x66E5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmulhw, 3, 0x66E5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpmullw, 3, 0x66D5, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmullw, 3, 0x66D5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmullw, 3, 0x66D5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsllw, 3, 0x6671, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegZMM }
|
||||
vpsllw, 3, 0x6671, 6, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpsllw, 3, 0x6671, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
|
||||
vpsllw, 3, 0x6671, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpsllw, 3, 0x6671, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
|
||||
vpsllw, 3, 0x6671, 6, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpsllw, 3, 0x66F1, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsllw, 3, 0x66F1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsllw, 3, 0x66F1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsraw, 3, 0x6671, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegZMM }
|
||||
vpsraw, 3, 0x6671, 4, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpsraw, 3, 0x6671, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
|
||||
vpsraw, 3, 0x6671, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpsraw, 3, 0x6671, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
|
||||
vpsraw, 3, 0x6671, 4, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpsraw, 3, 0x66E1, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsraw, 3, 0x66E1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsraw, 3, 0x66E1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsrlw, 3, 0x6671, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegZMM }
|
||||
vpsrlw, 3, 0x6671, 2, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpsrlw, 3, 0x6671, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
|
||||
vpsrlw, 3, 0x6671, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpsrlw, 3, 0x6671, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
|
||||
vpsrlw, 3, 0x6671, 2, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpsrlw, 3, 0x66D1, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsrlw, 3, 0x66D1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsrlw, 3, 0x66D1, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsubsw, 3, 0x66E9, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsubsw, 3, 0x66E9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsubsw, 3, 0x66E9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsubusw, 3, 0x66D9, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsubusw, 3, 0x66D9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsubusw, 3, 0x66D9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsubw, 3, 0x66F9, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpunpckhwd, 3, 0x6669, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpunpckhwd, 3, 0x6669, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpunpckhwd, 3, 0x6669, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpunpcklwd, 3, 0x6661, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpunpcklwd, 3, 0x6661, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpunpcklwd, 3, 0x6661, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpalignr, 4, 0x660F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpalignr, 4, 0x660F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpalignr, 4, 0x660F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=2|VexVVVV=1|VecESize=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpblendmb, 3, 0x6666, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpblendmb, 3, 0x6666, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpblendmb, 3, 0x6666, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpbroadcastb, 2, 0x6678, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegZMM }
|
||||
vpbroadcastb, 2, 0x6678, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
|
||||
vpbroadcastb, 2, 0x6678, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegYMM }
|
||||
vpbroadcastb, 2, 0x667A, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegZMM }
|
||||
vpbroadcastb, 2, 0x667A, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegXMM }
|
||||
vpbroadcastb, 2, 0x667A, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegYMM }
|
||||
|
||||
vpblendmw, 3, 0x6666, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpblendmw, 3, 0x6666, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpblendmw, 3, 0x6666, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpermi2w, 3, 0x6675, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpermi2w, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpermi2w, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpermt2w, 3, 0x667D, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpermt2w, 3, 0x667D, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpermt2w, 3, 0x667D, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpermw, 3, 0x668D, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpermw, 3, 0x668D, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpermw, 3, 0x668D, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsllvw, 3, 0x6612, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsllvw, 3, 0x6612, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsllvw, 3, 0x6612, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsravw, 3, 0x6611, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsravw, 3, 0x6611, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsravw, 3, 0x6611, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
vpsrlvw, 3, 0x6610, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsrlvw, 3, 0x6610, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsrlvw, 3, 0x6610, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpbroadcastw, 2, 0x6679, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpbroadcastw, 2, 0x6679, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpbroadcastw, 2, 0x6679, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpbroadcastw, 2, 0x667B, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegZMM }
|
||||
vpbroadcastw, 2, 0x667B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegXMM }
|
||||
vpbroadcastw, 2, 0x667B, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Reg32, RegYMM }
|
||||
|
||||
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpb, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpub, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
|
||||
vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpeqb, 3, 0x6674, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpgtb, 3, 0x6664, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegZMM }
|
||||
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=3|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
|
||||
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexVVVV=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
|
||||
vpslldq, 3, 0x6673, 7, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegZMM }
|
||||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=3|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM }
|
||||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexVVVV=3|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegYMM }
|
||||
vpsrldq, 3, 0x6673, 3, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=3|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
|
||||
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpeqw, 3, 0x6675, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpgtw, 3, 0x6665, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
vpextrw, 3, 0x66C5, None, 1, CpuAVX512BW, Modrm|S|EVex=4|VexOpcode=0|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64 }
|
||||
vpinsrw, 4, 0x66C4, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=0|VexVVVV=1|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
|
||||
vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpuw, 4, 0x663E, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vpcmpw, 4, 0x663F, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=2|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
|
||||
vpextrb, 3, 0x6614, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
vpinsrb, 4, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|VexVVVV=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64|Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM, RegXMM }
|
||||
|
||||
vpextrw, 3, 0x6615, None, 1, CpuAVX512BW, Modrm|EVex=4|VexOpcode=2|Disp8MemShift=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Reg64|Word|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
|
||||
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpmaddwd, 3, 0x66F5, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpmovb2m, 2, 0xF329, None, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegMask }
|
||||
vpmovb2m, 2, 0xF329, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegMask }
|
||||
vpmovb2m, 2, 0xF329, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegMask }
|
||||
|
||||
vpmovm2b, 2, 0xF328, None, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegZMM }
|
||||
vpmovm2b, 2, 0xF328, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM }
|
||||
vpmovm2b, 2, 0xF328, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegYMM }
|
||||
|
||||
vpmovm2w, 2, 0xF328, None, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegZMM }
|
||||
vpmovm2w, 2, 0xF328, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM }
|
||||
vpmovm2w, 2, 0xF328, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegYMM }
|
||||
|
||||
vpmovswb, 2, 0xF320, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|RegMem }
|
||||
vpmovswb, 2, 0xF320, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
|
||||
vpmovswb, 2, 0xF320, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
|
||||
vpmovuswb, 2, 0xF310, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|RegMem }
|
||||
vpmovuswb, 2, 0xF310, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
|
||||
vpmovuswb, 2, 0xF310, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
|
||||
vpmovwb, 2, 0xF330, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|RegMem }
|
||||
vpmovwb, 2, 0xF330, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|RegMem }
|
||||
vpmovwb, 2, 0xF330, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|RegMem }
|
||||
|
||||
vpmovswb, 2, 0xF320, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovswb, 2, 0xF320, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovswb, 2, 0xF320, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovuswb, 2, 0xF310, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovuswb, 2, 0xF310, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovuswb, 2, 0xF310, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovwb, 2, 0xF330, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovwb, 2, 0xF330, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
vpmovwb, 2, 0xF330, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8 }
|
||||
|
||||
vpmovsxbw, 2, 0x6620, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpmovsxbw, 2, 0x6620, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpmovsxbw, 2, 0x6620, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
vpmovzxbw, 2, 0x6630, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpmovzxbw, 2, 0x6630, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=1|Disp8MemShift=3|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpmovzxbw, 2, 0x6630, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
|
||||
vpmovw2m, 2, 0xF329, None, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegMask }
|
||||
vpmovw2m, 2, 0xF329, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegMask }
|
||||
vpmovw2m, 2, 0xF329, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegMask }
|
||||
|
||||
vpsadbw, 3, 0x66F6, None, 1, CpuAVX512BW, Modrm|EVex=1|VexOpcode=0|VexVVVV=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegZMM }
|
||||
vpsadbw, 3, 0x66F6, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|VexOpcode=0|VexVVVV=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegXMM }
|
||||
vpsadbw, 3, 0x66F6, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|VexOpcode=0|VexVVVV=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegYMM }
|
||||
|
||||
vpshufhw, 3, 0xF370, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpshufhw, 3, 0xF370, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpshufhw, 3, 0xF370, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
|
||||
vpshuflw, 3, 0xF270, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=3|VexOpcode=0|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM }
|
||||
vpshuflw, 3, 0xF270, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexOpcode=0|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM }
|
||||
vpshuflw, 3, 0xF270, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexOpcode=0|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM }
|
||||
|
||||
vptestmb, 3, 0x6626, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vptestmb, 3, 0x6626, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vptestmb, 3, 0x6626, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
|
||||
vptestmw, 3, 0x6626, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vptestmw, 3, 0x6626, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vptestmw, 3, 0x6626, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
|
||||
vptestnmb, 3, 0xF326, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vptestnmb, 3, 0xF326, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vptestnmb, 3, 0xF326, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=1|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
|
||||
vptestnmw, 3, 0xF326, None, 1, CpuAVX512BW, Modrm|EVex=1|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=6|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM|ZMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegZMM, RegMask }
|
||||
vptestnmw, 3, 0xF326, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=4|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|XMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegXMM, RegMask }
|
||||
vptestnmw, 3, 0xF326, None, 1, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=2|VexOpcode=1|VexVVVV=1|VexW=2|Disp8MemShift=5|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|YMMword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|Vec_Disp8, RegYMM, RegMask }
|
||||
|
||||
// AVX512BW instructions end.
|
||||
|
|
|
|||
16000
opcodes/i386-tbl.h
16000
opcodes/i386-tbl.h
File diff suppressed because it is too large
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Reference in a new issue