x86: replace adhoc ambiguous operand checking for CRC32
There's no need (anymore?) to heavily special case this - just make generic logic consider only its first operand, and deal with the case of an 'l' suffix not being allowed in a pattern.
This commit is contained in:
Jan Beulich
parent
c006a730e9
commit
1a0351246a
13 changed files with 60 additions and 50 deletions
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@ -1,3 +1,17 @@
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2020-01-21 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (process_suffix): Merge CRC32 handling into
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generic code path. Deal with No_lSuf being set in a template.
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* testsuite/gas/i386/inval-crc32.l,
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testsuite/gas/i386/x86-64-inval-crc32.l: Expect warning(s)
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instead of error(s) when operand size is ambiguous.
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* testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s,
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testsuite/gas/i386/noreg64.s: Add CRC32 tests.
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* testsuite/gas/i386/noreg16.d, testsuite/gas/i386/noreg16.l,
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testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg32.l,
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testsuite/gas/i386/noreg64.d, testsuite/gas/i386/noreg64.l:
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Adjust expectations.
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2020-01-21 Jan Beulich <jbeulich@suse.com>
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2020-01-21 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (process_suffix): Drop SYSRET special case
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* config/tc-i386.c (process_suffix): Drop SYSRET special case
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@ -6301,50 +6301,26 @@ process_suffix (void)
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Destination register type is more significant than source
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Destination register type is more significant than source
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register type. crc32 in SSE4.2 prefers source register
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register type. crc32 in SSE4.2 prefers source register
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type. */
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type. */
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if (i.tm.base_opcode == 0xf20f38f0
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unsigned int op = i.tm.base_opcode != 0xf20f38f0 ? i.operands : 1;
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&& i.types[0].bitfield.class == Reg)
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{
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if (i.types[0].bitfield.byte)
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i.suffix = BYTE_MNEM_SUFFIX;
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else if (i.types[0].bitfield.word)
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i.suffix = WORD_MNEM_SUFFIX;
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else if (i.types[0].bitfield.dword)
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i.suffix = LONG_MNEM_SUFFIX;
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else if (i.types[0].bitfield.qword)
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i.suffix = QWORD_MNEM_SUFFIX;
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}
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if (!i.suffix)
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while (op--)
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{
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if (i.tm.operand_types[op].bitfield.instance == InstanceNone
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int op;
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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{
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if (i.tm.base_opcode == 0xf20f38f0)
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if (i.types[op].bitfield.class != Reg)
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{
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continue;
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/* We have to know the operand size for crc32. */
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if (i.types[op].bitfield.byte)
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as_bad (_("ambiguous memory operand size for `%s`"),
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i.suffix = BYTE_MNEM_SUFFIX;
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i.tm.name);
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else if (i.types[op].bitfield.word)
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return 0;
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i.suffix = WORD_MNEM_SUFFIX;
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}
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else if (i.types[op].bitfield.dword)
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i.suffix = LONG_MNEM_SUFFIX;
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for (op = i.operands; --op >= 0;)
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else if (i.types[op].bitfield.qword)
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if (i.tm.operand_types[op].bitfield.instance == InstanceNone
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i.suffix = QWORD_MNEM_SUFFIX;
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|| i.tm.operand_types[op].bitfield.instance == Accum)
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else
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{
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continue;
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if (i.types[op].bitfield.class != Reg)
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break;
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continue;
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}
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if (i.types[op].bitfield.byte)
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i.suffix = BYTE_MNEM_SUFFIX;
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else if (i.types[op].bitfield.word)
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i.suffix = WORD_MNEM_SUFFIX;
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else if (i.types[op].bitfield.dword)
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i.suffix = LONG_MNEM_SUFFIX;
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else if (i.types[op].bitfield.qword)
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i.suffix = QWORD_MNEM_SUFFIX;
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else
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continue;
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break;
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}
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}
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}
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}
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else if (i.suffix == BYTE_MNEM_SUFFIX)
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else if (i.suffix == BYTE_MNEM_SUFFIX)
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{
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{
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@ -6484,8 +6460,10 @@ process_suffix (void)
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i.suffix = SHORT_MNEM_SUFFIX;
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i.suffix = SHORT_MNEM_SUFFIX;
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else if (flag_code == CODE_16BIT)
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else if (flag_code == CODE_16BIT)
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i.suffix = WORD_MNEM_SUFFIX;
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i.suffix = WORD_MNEM_SUFFIX;
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else
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else if (!i.tm.opcode_modifier.no_lsuf)
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i.suffix = LONG_MNEM_SUFFIX;
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i.suffix = LONG_MNEM_SUFFIX;
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else
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i.suffix = QWORD_MNEM_SUFFIX;
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}
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}
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}
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}
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@ -3,7 +3,7 @@
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.*:7: Error: .*
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.*:7: Error: .*
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.*:8: Error: .*
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.*:8: Error: .*
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.*:9: Error: .*
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.*:9: Error: .*
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.*:10: Error: .*
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.*:10: Warning: .*
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.*:11: Error: .*
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.*:11: Error: .*
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.*:12: Error: .*
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.*:12: Error: .*
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.*:13: Error: .*
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.*:13: Error: .*
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@ -27,7 +27,9 @@ GAS LISTING .*
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[ ]*7[ ]+crc32w \(%esi\), %ax
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[ ]*7[ ]+crc32w \(%esi\), %ax
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[ ]*8[ ]+crc32 \(%esi\), %al
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[ ]*8[ ]+crc32 \(%esi\), %al
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[ ]*9[ ]+crc32 \(%esi\), %ax
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[ ]*9[ ]+crc32 \(%esi\), %ax
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[ ]*10[ ]+crc32 \(%esi\), %eax
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[ ]*10[ ]+\?\?\?\? F20F38F1[ ]+crc32 \(%esi\), %eax
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\*\*\*\* Warning: .* `crc32'
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[ ]*10[ ]+06
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[ ]*11[ ]+crc32 %al, %al
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[ ]*11[ ]+crc32 %al, %al
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[ ]*12[ ]+crc32b %al, %al
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[ ]*12[ ]+crc32b %al, %al
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[ ]*13[ ]+crc32 %ax, %ax
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[ ]*13[ ]+crc32 %ax, %ax
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@ -26,6 +26,7 @@ Disassembly of section .text:
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*[a-f0-9]+: 81 3f 34 12 cmpw \$0x1234,\(%bx\)
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*[a-f0-9]+: 81 3f 34 12 cmpw \$0x1234,\(%bx\)
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*[a-f0-9]+: a7 cmpsw %es:\(%di\),%ds:\(%si\)
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*[a-f0-9]+: a7 cmpsw %es:\(%di\),%ds:\(%si\)
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*[a-f0-9]+: 67 a7 cmpsw %es:\(%edi\),%ds:\(%esi\)
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*[a-f0-9]+: 67 a7 cmpsw %es:\(%edi\),%ds:\(%esi\)
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*[a-f0-9]+: f2 0f 38 f1 07 crc32w \(%bx\),%eax
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*[a-f0-9]+: f2 0f 2a 07 cvtsi2sdl \(%bx\),%xmm0
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*[a-f0-9]+: f2 0f 2a 07 cvtsi2sdl \(%bx\),%xmm0
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*[a-f0-9]+: f3 0f 2a 07 cvtsi2ssl \(%bx\),%xmm0
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*[a-f0-9]+: f3 0f 2a 07 cvtsi2ssl \(%bx\),%xmm0
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*[a-f0-9]+: ff 0f decw \(%bx\)
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*[a-f0-9]+: ff 0f decw \(%bx\)
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@ -17,6 +17,7 @@
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.*:[1-9][0-9]*: Warning: .* `cmp'
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.*:[1-9][0-9]*: Warning: .* `cmp'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `crc32'
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.*:[1-9][0-9]*: Warning: .* `dec'
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.*:[1-9][0-9]*: Warning: .* `dec'
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.*:[1-9][0-9]*: Warning: .* `div'
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.*:[1-9][0-9]*: Warning: .* `div'
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.*:[1-9][0-9]*: Warning: .* `fadd'
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.*:[1-9][0-9]*: Warning: .* `fadd'
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@ -20,6 +20,7 @@ noreg:
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cmp $0x1234, (%bx)
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cmp $0x1234, (%bx)
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cmps
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cmps
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cmps %es:(%edi), (%esi)
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cmps %es:(%edi), (%esi)
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crc32 (%bx), %eax
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cvtsi2sd (%bx), %xmm0
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cvtsi2sd (%bx), %xmm0
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cvtsi2ss (%bx), %xmm0
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cvtsi2ss (%bx), %xmm0
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dec (%bx)
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dec (%bx)
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@ -30,6 +30,7 @@ Disassembly of section .text:
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*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%eax\)
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*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%eax\)
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*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
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*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
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*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
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*[a-f0-9]+: a7 cmpsl %es:\(%edi\),%ds:\(%esi\)
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*[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%eax\),%eax
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*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%eax\),%xmm0
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*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%eax\),%xmm0
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*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%eax\),%xmm0
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*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%eax\),%xmm0
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*[a-f0-9]+: ff 08 decl \(%eax\)
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*[a-f0-9]+: ff 08 decl \(%eax\)
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@ -21,6 +21,7 @@
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.*:[1-9][0-9]*: Warning: .* `cmp'
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.*:[1-9][0-9]*: Warning: .* `cmp'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `crc32'
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.*:[1-9][0-9]*: Warning: .* `dec'
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.*:[1-9][0-9]*: Warning: .* `dec'
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.*:[1-9][0-9]*: Warning: .* `div'
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.*:[1-9][0-9]*: Warning: .* `div'
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.*:[1-9][0-9]*: Warning: .* `fadd'
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.*:[1-9][0-9]*: Warning: .* `fadd'
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@ -23,6 +23,7 @@ noreg:
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cmp $0x12345678, (%eax)
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cmp $0x12345678, (%eax)
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cmps
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cmps
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cmps %es:(%edi), (%esi)
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cmps %es:(%edi), (%esi)
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crc32 (%eax), %eax
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cvtsi2sd (%eax), %xmm0
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cvtsi2sd (%eax), %xmm0
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cvtsi2ss (%eax), %xmm0
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cvtsi2ss (%eax), %xmm0
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dec (%eax)
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dec (%eax)
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@ -30,6 +30,8 @@ Disassembly of section .text:
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*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%rax\)
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*[a-f0-9]+: 81 38 78 56 34 12 cmpl \$0x12345678,\(%rax\)
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*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
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*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
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*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
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*[a-f0-9]+: a7 cmpsl %es:\(%rdi\),%ds:\(%rsi\)
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*[a-f0-9]+: f2 0f 38 f1 00 crc32l \(%rax\),%eax
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*[a-f0-9]+: f2 48 0f 38 f1 00 crc32q \(%rax\),%rax
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*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
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*[a-f0-9]+: f2 0f 2a 00 cvtsi2sdl \(%rax\),%xmm0
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*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
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*[a-f0-9]+: f3 0f 2a 00 cvtsi2ssl \(%rax\),%xmm0
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*[a-f0-9]+: ff 08 decl \(%rax\)
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*[a-f0-9]+: ff 08 decl \(%rax\)
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@ -21,6 +21,8 @@
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.*:[1-9][0-9]*: Warning: .* `cmp'
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.*:[1-9][0-9]*: Warning: .* `cmp'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `cmps'
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.*:[1-9][0-9]*: Warning: .* `crc32'
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.*:[1-9][0-9]*: Warning: .* `crc32'
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.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
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.*:[1-9][0-9]*: Warning: .* `cvtsi2sd'
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.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
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.*:[1-9][0-9]*: Warning: .* `cvtsi2ss'
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.*:[1-9][0-9]*: Warning: .* `dec'
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.*:[1-9][0-9]*: Warning: .* `dec'
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@ -23,6 +23,8 @@ noreg:
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cmp $0x12345678, (%rax)
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cmp $0x12345678, (%rax)
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cmps
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cmps
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cmps %es:(%rdi), (%rsi)
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cmps %es:(%rdi), (%rsi)
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crc32 (%rax), %eax
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crc32 (%rax), %rax
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cvtsi2sd (%rax), %xmm0
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cvtsi2sd (%rax), %xmm0
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cvtsi2ss (%rax), %xmm0
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cvtsi2ss (%rax), %xmm0
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dec (%rax)
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dec (%rax)
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@ -3,8 +3,8 @@
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.*:7: Error: .*
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.*:7: Error: .*
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.*:8: Error: .*
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.*:8: Error: .*
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.*:9: Error: .*
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.*:9: Error: .*
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.*:10: Error: .*
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.*:10: Warning: .*
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.*:11: Error: .*
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.*:11: Warning: .*
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.*:12: Error: .*
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.*:12: Error: .*
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.*:13: Error: .*
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.*:13: Error: .*
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.*:14: Error: .*
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.*:14: Error: .*
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@ -38,8 +38,12 @@ GAS LISTING .*
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[ ]*7[ ]+crc32w \(%rsi\), %ax
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[ ]*7[ ]+crc32w \(%rsi\), %ax
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[ ]*8[ ]+crc32 \(%rsi\), %al
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[ ]*8[ ]+crc32 \(%rsi\), %al
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[ ]*9[ ]+crc32 \(%rsi\), %ax
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[ ]*9[ ]+crc32 \(%rsi\), %ax
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[ ]*10[ ]+crc32 \(%rsi\), %eax
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[ ]*10[ ]+\?\?\?\? F20F38F1[ ]+crc32 \(%rsi\), %eax
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[ ]*11[ ]+crc32 \(%rsi\), %rax
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\*\*\*\* Warning: .* `crc32'
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[ ]*10[ ]+06
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[ ]*11[ ]+\?\?\?\? F2480F38[ ]+crc32 \(%rsi\), %rax
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\*\*\*\* Warning: .* `crc32'
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[ ]*11[ ]+F106
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[ ]*12[ ]+crc32 %al, %al
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[ ]*12[ ]+crc32 %al, %al
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[ ]*13[ ]+crc32b %al, %al
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[ ]*13[ ]+crc32b %al, %al
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[ ]*14[ ]+crc32 %ax, %ax
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[ ]*14[ ]+crc32 %ax, %ax
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