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RISC-V: Indent and GNU coding standards tidy, also aligned the code.

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bfd/
    * elfnn-riscv.c: Indent, labels and GNU coding standards tidy,
    also aligned the code.
gas/
    * config/tc-riscv.c: Indent and GNU coding standards tidy,
    also aligned the code.
    * config/tc-riscv.h: Likewise.
include/
    * opcode/riscv.h: Indent and GNU coding standards tidy,
    also aligned the code.
opcodes/
    * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
    (riscv_fpr_names_abi): Likewise.
    (riscv_opcodes): Likewise.
    (riscv_insn_types): Likewise.
This commit is contained in:
Nelson Chu 2021-01-15 09:36:51 +08:00
parent b800637e76
commit 1942a04836
9 changed files with 923 additions and 901 deletions
Download patch file Download diff file Expand all files Collapse all files

5
bfd/ChangeLog
View file

@ -1,3 +1,8 @@
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* elfnn-riscv.c: Indent, labels and GNU coding standards tidy,
also aligned the code.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* elfnn-riscv.c (riscv_merge_attributes): Fix typos of messages.

17
bfd/elfnn-riscv.c
View file

@ -1771,7 +1771,6 @@ riscv_pcrel_reloc_eq (const void *entry1, const void *entry2)
static bfd_boolean
riscv_init_pcrel_relocs (riscv_pcrel_relocs *p)
{
p->lo_relocs = NULL;
p->hi_relocs = htab_create (1024, riscv_pcrel_reloc_hash,
riscv_pcrel_reloc_eq, free);
@ -2656,14 +2655,14 @@ riscv_elf_relocate_section (bfd *output_bfd,
BFD_ASSERT (! unresolved_reloc);
bfd_put_NN (output_bfd,
dtpoff (info, relocation),
(htab->elf.sgot->contents + off +
RISCV_ELF_WORD_BYTES));
(htab->elf.sgot->contents
+ off + RISCV_ELF_WORD_BYTES));
}
else
{
bfd_put_NN (output_bfd, 0,
(htab->elf.sgot->contents + off +
RISCV_ELF_WORD_BYTES));
(htab->elf.sgot->contents
+ off + RISCV_ELF_WORD_BYTES));
outrel.r_info = ELFNN_R_INFO (indx, R_RISCV_TLS_DTPRELNN);
outrel.r_offset += RISCV_ELF_WORD_BYTES;
riscv_elf_append_rela (output_bfd, htab->elf.srelgot, &outrel);
@ -2680,8 +2679,8 @@ riscv_elf_relocate_section (bfd *output_bfd,
htab->elf.sgot->contents + off);
bfd_put_NN (output_bfd,
dtpoff (info, relocation),
(htab->elf.sgot->contents + off +
RISCV_ELF_WORD_BYTES));
(htab->elf.sgot->contents
+ off + RISCV_ELF_WORD_BYTES));
}
}
@ -3499,11 +3498,11 @@ riscv_merge_multi_letter_ext (bfd *ibfd,
}
}
if (in || out) {
if (in || out)
{
/* If we're here, either `in' or `out' is running longer than
the other. So, we need to append the corresponding tail. */
tail = in ? in : out;
while (tail)
{
riscv_add_subset (&merged_subsets, tail->name, tail->major_version,

6
gas/ChangeLog
View file

@ -1,3 +1,9 @@
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c: Indent and GNU coding standards tidy,
also aligned the code.
* config/tc-riscv.h: Likewise.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* config/tc-riscv.c: Error and warning messages tidy.

28
gas/config/tc-riscv.c
View file

@ -85,7 +85,8 @@ static enum riscv_priv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE;
static unsigned xlen = 0; /* The width of an x-register. */
static unsigned abi_xlen = 0; /* The width of a pointer in the ABI. */
static bfd_boolean rve_abi = FALSE;
enum float_abi {
enum float_abi
{
FLOAT_ABI_DEFAULT = -1,
FLOAT_ABI_SOFT,
FLOAT_ABI_SINGLE,
@ -1254,10 +1255,6 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
INSERT_OPERAND (RS2, insn, va_arg (args, int));
continue;
case '>':
INSERT_OPERAND (SHAMT, insn, va_arg (args, int));
continue;
case 'j':
case 'u':
case 'q':
@ -2184,11 +2181,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
"field, value must be 0...64"));
break;
}
INSERT_OPERAND (CFUNCT6, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
case '4':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
@ -2199,11 +2196,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
"field, value must be 0...15"));
break;
}
INSERT_OPERAND (CFUNCT4, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
case '3':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
@ -2218,6 +2215,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
s = expr_end;
continue;
case '2':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
@ -2232,6 +2230,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
imm_expr->X_op = O_absent;
s = expr_end;
continue;
default:
as_bad (_("internal: unknown compressed funct "
"field specifier `CF%c'"), *args);
@ -2392,7 +2391,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
}
continue;
}
break;
case 'I':
@ -2462,7 +2460,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
|| imm_expr->X_add_number < -(signed)RISCV_IMM_REACH/2)
break;
}
s = expr_end;
continue;
@ -2508,6 +2505,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
else
*imm_reloc = BFD_RELOC_RISCV_CALL;
continue;
case 'O':
switch (*++args)
{
@ -2523,11 +2521,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
"lower 2 bits must be 0x3"));
break;
}
INSERT_OPERAND (OP, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
case '2':
if (my_getOpcodeExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
@ -2538,11 +2536,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
"value must be 0...2"));
break;
}
INSERT_OPERAND (OP2, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
default:
as_bad (_("internal: unknown opcode field "
"specifier `O%c'"), *args);
@ -2562,11 +2560,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
"value must be 0...127"));
break;
}
INSERT_OPERAND (FUNCT7, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
case '3':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
@ -2577,11 +2575,11 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
"value must be 0...7"));
break;
}
INSERT_OPERAND (FUNCT3, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
continue;
case '2':
if (my_getSmallExpression (imm_expr, imm_reloc, s, p)
|| imm_expr->X_op != O_constant
@ -2592,7 +2590,6 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
"value must be 0...3"));
break;
}
INSERT_OPERAND (FUNCT2, *ip, imm_expr->X_add_number);
imm_expr->X_op = O_absent;
s = expr_end;
@ -3728,11 +3725,10 @@ riscv_convert_symbolic_attribute (const char *name)
#undef T
};
unsigned int i;
if (name == NULL)
return -1;
unsigned int i;
for (i = 0; i < ARRAY_SIZE (attribute_table); i++)
if (strcmp (name, attribute_table[i].name) == 0)
return attribute_table[i].tag;

5
include/ChangeLog
View file

@ -1,3 +1,8 @@
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* opcode/riscv.h: Indent and GNU coding standards tidy,
also aligned the code.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* elf/riscv.h: Comments tidy and improvement.

7
include/opcode/riscv.h
View file

@ -322,26 +322,33 @@ struct riscv_opcode
{
/* The name of the instruction. */
const char *name;
/* The requirement of xlen for the instruction, 0 if no requirement. */
unsigned xlen_requirement;
/* Class to which this instruction belongs. Used to decide whether or
not this instruction is legal in the current -march context. */
enum riscv_insn_class insn_class;
/* A string describing the arguments for this instruction. */
const char *args;
/* The basic opcode for the instruction. When assembling, this
opcode is modified by the arguments to produce the actual opcode
that is used. If pinfo is INSN_MACRO, then this is 0. */
insn_t match;
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
relevant portions of the opcode when disassembling. If the
actual opcode anded with the match field equals the opcode field,
then we have found the correct instruction. If pinfo is
INSN_MACRO, then this field is the macro identifier. */
insn_t mask;
/* A function to determine if a word corresponds to this instruction.
Usually, this computes ((word & mask) == match). */
int (*match_func) (const struct riscv_opcode *op, insn_t word);
/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
of bits describing the instruction, notably any relevant hazard
information. */

7
opcodes/ChangeLog
View file

@ -1,3 +1,10 @@
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
(riscv_fpr_names_abi): Likewise.
(riscv_opcodes): Likewise.
(riscv_insn_types): Likewise.
2021-01-15 Nelson Chu <nelson.chu@sifive.com>
* riscv-dis.c (parse_riscv_dis_option): Fix typos of message.

11
opcodes/riscv-opc.c
View file

@ -34,7 +34,8 @@ const char * const riscv_gpr_names_numeric[NGPR] =
"x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31"
};
const char * const riscv_gpr_names_abi[NGPR] = {
const char * const riscv_gpr_names_abi[NGPR] =
{
"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
@ -49,7 +50,8 @@ const char * const riscv_fpr_names_numeric[NFPR] =
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
};
const char * const riscv_fpr_names_abi[NFPR] = {
const char * const riscv_fpr_names_abi[NFPR] =
{
"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
@ -571,13 +573,10 @@ const struct riscv_opcode riscv_opcodes[] =
{"fsw", 32, INSN_CLASS_F_AND_C, "CD,Ck(Cs)", MATCH_C_FSW, MASK_C_FSW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
{"fsw", 0, INSN_CLASS_F, "T,q(s)", MATCH_FSW, MASK_FSW, match_opcode, INSN_DREF|INSN_4_BYTE },
{"fsw", 0, INSN_CLASS_F, "T,A,s", 0, (int) M_FSW, match_never, INSN_MACRO },
{"fmv.x.w", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
{"fmv.w.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.x.s", 0, INSN_CLASS_F, "d,S", MATCH_FMV_X_S, MASK_FMV_X_S, match_opcode, 0 },
{"fmv.s.x", 0, INSN_CLASS_F, "D,s", MATCH_FMV_S_X, MASK_FMV_S_X, match_opcode, 0 },
{"fmv.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJ_S, MASK_FSGNJ_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fneg.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJN_S, MASK_FSGNJN_S, match_rs1_eq_rs2, INSN_ALIAS },
{"fabs.s", 0, INSN_CLASS_F, "D,U", MATCH_FSGNJX_S, MASK_FSGNJX_S, match_rs1_eq_rs2, INSN_ALIAS },
@ -845,7 +844,6 @@ const struct riscv_opcode riscv_insn_types[] =
{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,s,T", 0, 0, match_opcode, 0 },
{"r", 0, INSN_CLASS_F, "O4,F3,F7,d,S,T", 0, 0, match_opcode, 0 },
{"r", 0, INSN_CLASS_F, "O4,F3,F7,D,S,T", 0, 0, match_opcode, 0 },
{"r", 0, INSN_CLASS_I, "O4,F3,F2,d,s,t,r", 0, 0, match_opcode, 0 },
{"r", 0, INSN_CLASS_F, "O4,F3,F2,D,s,t,r", 0, 0, match_opcode, 0 },
{"r", 0, INSN_CLASS_F, "O4,F3,F2,d,S,t,r", 0, 0, match_opcode, 0 },
@ -884,7 +882,6 @@ const struct riscv_opcode riscv_insn_types[] =
{"i", 0, INSN_CLASS_F, "O4,F3,D,s,j", 0, 0, match_opcode, 0 },
{"i", 0, INSN_CLASS_F, "O4,F3,d,S,j", 0, 0, match_opcode, 0 },
{"i", 0, INSN_CLASS_F, "O4,F3,D,S,j", 0, 0, match_opcode, 0 },
{"i", 0, INSN_CLASS_I, "O4,F3,d,o(s)", 0, 0, match_opcode, 0 },
{"i", 0, INSN_CLASS_F, "O4,F3,D,o(s)", 0, 0, match_opcode, 0 },