Add support for ARMv8-M security extensions instructions
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com> gas/ * config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN. (arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not shared with a non M profile architecture. (do_rn): New function. (known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather than arm_ext_v8m. (v7m_psrs): Add ARMv8-M security extensions new special registers. (insns): Add ARMv8-M Security Extensions instructions. (aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of arm_ext_v8m_m to decide the profile and the Thumb ISA. * testsuite/gas/arm/archv8m-cmse.s: New file. * testsuite/gas/arm/archv8m-cmse-main.s: Likewise.. * testsuite/gas/arm/archv8m-cmse-msr.s: Likewise. * testsuite/gas/arm/any-cmse.d: Likewise. * testsuite/gas/arm/any-cmse-main.d: Likewise. * testsuite/gas/arm/archv8m-cmse-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise. * testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise. * testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise. include/ * opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit. (ARM_AEXT2_V8M_MAIN): New architecture extension feature set. (ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M for the high core bits. opcodes/ * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M Mainline Security Extensions instructions. (thumb_opcodes): Add entries for narrow ARMv8-M Security Extensions instructions. (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions instructions. (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions special registers.
This commit is contained in:
Thomas Preud'homme
parent
29f4fdc42d
commit
16a1fa25be
16 changed files with 270 additions and 10 deletions
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@ -1,3 +1,27 @@
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2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* config/tc-arm.c (arm_ext_m): Add feature bit ARM_EXT2_V8M_MAIN.
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(arm_ext_v8m_main): New feature set for bit ARM_EXT2_V8M_MAIN.
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(arm_ext_v8m_m_only): New feature set for instructions in ARMv8-M not
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shared with a non M profile architecture.
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(do_rn): New function.
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(known_t32_only_insn): Check opcode against arm_ext_v8m_m_only rather
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than arm_ext_v8m.
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(v7m_psrs): Add ARMv8-M security extensions new special registers.
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(insns): Add ARMv8-M Security Extensions instructions.
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(aeabi_set_public_attributes): Use arm_ext_v8m_m_only instead of
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arm_ext_v8m_m to decide the profile and the Thumb ISA.
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* testsuite/gas/arm/archv8m-cmse.s: New file.
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* testsuite/gas/arm/archv8m-cmse-main.s: Likewise..
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* testsuite/gas/arm/archv8m-cmse-msr.s: Likewise.
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* testsuite/gas/arm/any-cmse.d: Likewise.
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* testsuite/gas/arm/any-cmse-main.d: Likewise.
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* testsuite/gas/arm/archv8m-cmse-base.d: Likewise.
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* testsuite/gas/arm/archv8m-cmse-msr-base.d: Likewise.
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* testsuite/gas/arm/archv8m-cmse-main-1.d: Likewise.
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* testsuite/gas/arm/archv8m-cmse-main-2.d: Likewise.
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* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
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2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
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* testsuite/gas/sparc/sparc5vis4.s: Fix mnemonic of faligndatai.
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@ -201,7 +201,8 @@ static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
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static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
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static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
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static const arm_feature_set arm_ext_m =
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ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M, ARM_EXT2_V8M);
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ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M,
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ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
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static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
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static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
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static const arm_feature_set arm_ext_os = ARM_FEATURE_CORE_LOW (ARM_EXT_OS);
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@ -209,6 +210,11 @@ static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV);
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static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT);
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static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN);
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static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M);
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static const arm_feature_set arm_ext_v8m_main =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN);
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/* Instructions in ARMv8-M only found in M profile architectures. */
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static const arm_feature_set arm_ext_v8m_m_only =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
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static const arm_feature_set arm_ext_v6t2_v8m =
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ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M);
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/* Instructions shared between ARMv8-A and ARMv8-M. */
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@ -8177,6 +8183,12 @@ do_rd (void)
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inst.instruction |= inst.operands[0].reg << 12;
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}
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static void
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do_rn (void)
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{
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inst.instruction |= inst.operands[0].reg << 16;
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}
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static void
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do_rd_rm (void)
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{
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@ -18189,8 +18201,8 @@ known_t32_only_insn (const struct asm_opcode *opcode)
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|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier))
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return TRUE;
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/* Wide-only instruction added to ARMv8-M. */
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if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m)
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/* Wide-only instruction added to ARMv8-M Baseline. */
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if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m_m_only)
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|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics)
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|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m)
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|| ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div))
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@ -18766,14 +18778,16 @@ static const struct asm_psr v7m_psrs[] =
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{"ipsr", 5 }, {"IPSR", 5 },
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{"epsr", 6 }, {"EPSR", 6 },
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{"iepsr", 7 }, {"IEPSR", 7 },
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{"msp", 8 }, {"MSP", 8 },
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{"psp", 9 }, {"PSP", 9 },
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{"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 },
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{"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 },
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{"primask", 16}, {"PRIMASK", 16},
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{"basepri", 17}, {"BASEPRI", 17},
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{"basepri_max", 18}, {"BASEPRI_MAX", 18},
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{"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
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{"faultmask", 19}, {"FAULTMASK", 19},
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{"control", 20}, {"CONTROL", 20}
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{"control", 20}, {"CONTROL", 20},
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{"msp_ns", 0x88}, {"MSP_NS", 0x88},
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{"psp_ns", 0x89}, {"PSP_NS", 0x89}
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};
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/* Table of all shift-in-operand names. */
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@ -20948,12 +20962,25 @@ static const struct asm_opcode insns[] =
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cCE("cfmadda32", e200600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
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cCE("cfmsuba32", e300600, 4, (RMAX, RMAX, RMFX, RMFX), mav_quad),
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/* ARMv8-M instructions. */
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#undef ARM_VARIANT
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#define ARM_VARIANT NULL
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8m
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TUE("sg", 0, e97fe97f, 0, (), 0, noargs),
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TUE("blxns", 0, 4784, 1, (RRnpc), 0, t_blx),
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TUE("bxns", 0, 4704, 1, (RRnpc), 0, t_bx),
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TUE("tt", 0, e840f000, 2, (RRnpc, RRnpc), 0, tt),
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TUE("ttt", 0, e840f040, 2, (RRnpc, RRnpc), 0, tt),
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TUE("tta", 0, e840f080, 2, (RRnpc, RRnpc), 0, tt),
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TUE("ttat", 0, e840f0c0, 2, (RRnpc, RRnpc), 0, tt),
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/* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
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instructions behave as nop if no VFP is present. */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT & arm_ext_v8m_main
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TUEc("vlldm", 0, ec300a00, 1, (RRnpc), rn),
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TUEc("vlstm", 0, ec200a00, 1, (RRnpc), rn),
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};
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#undef ARM_VARIANT
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#undef THUMB_VARIANT
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@ -26171,7 +26198,7 @@ aeabi_set_public_attributes (void)
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if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
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|| ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
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|| (ARM_CPU_HAS_FEATURE (flags, arm_ext_atomics)
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&& !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)))
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&& !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)))
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profile = 'A';
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else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
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profile = 'R';
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@ -26195,7 +26222,7 @@ aeabi_set_public_attributes (void)
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int thumb_isa_use;
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if (!ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
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&& ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
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&& ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only))
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thumb_isa_use = 3;
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else if (ARM_CPU_HAS_FEATURE (flags, arm_arch_t2))
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thumb_isa_use = 2;
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11
gas/testsuite/gas/arm/any-cmse-main.d
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11
gas/testsuite/gas/arm/any-cmse-main.d
Normal file
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@ -0,0 +1,11 @@
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#name: attributes for 'any' CPU with ARMv8-M Mainline Security Extensions instructions
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#source: archv8m-cmse-main.s
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#as:
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#readelf: -A
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# target: *-*-*eabi* *-*-nacl*
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Attribute Section: aeabi
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File Attributes
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Tag_CPU_arch: v8-M.mainline
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Tag_CPU_arch_profile: Microcontroller
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Tag_THUMB_ISA_use: Yes
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11
gas/testsuite/gas/arm/any-cmse.d
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11
gas/testsuite/gas/arm/any-cmse.d
Normal file
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@ -0,0 +1,11 @@
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#name: attributes for 'any' CPU with ARMv8-M Security Extensions instructions
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#source: archv8m-cmse.s
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#as:
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#readelf: -A
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# target: *-*-*eabi* *-*-nacl*
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Attribute Section: aeabi
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File Attributes
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Tag_CPU_arch: v8-M.baseline
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Tag_CPU_arch_profile: Microcontroller
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Tag_THUMB_ISA_use: Yes
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17
gas/testsuite/gas/arm/archv8m-cmse-base.d
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17
gas/testsuite/gas/arm/archv8m-cmse-base.d
Normal file
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@ -0,0 +1,17 @@
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#name: ARMv8-M Baseline Security Extensions instructions
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#source: archv8m-cmse.s
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#as: -march=armv8-m.base
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+.* <[^>]*> e97f e97f sg
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0+.* <[^>]*> 47a4 blxns r4
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0+.* <[^>]*> 47cc blxns r9
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0+.* <[^>]*> 4724 bxns r4
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0+.* <[^>]*> 474c bxns r9
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0+.* <[^>]*> e841 f080 tta r0, r1
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0+.* <[^>]*> e849 f880 tta r8, r9
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0+.* <[^>]*> e841 f0c0 ttat r0, r1
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0+.* <[^>]*> e849 f8c0 ttat r8, r9
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17
gas/testsuite/gas/arm/archv8m-cmse-main-1.d
Normal file
17
gas/testsuite/gas/arm/archv8m-cmse-main-1.d
Normal file
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@ -0,0 +1,17 @@
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#name: ARMv8-M Mainline Security Extensions instructions (1)
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#source: archv8m-cmse.s
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#as: -march=armv8-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+.* <[^>]*> e97f e97f sg
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0+.* <[^>]*> 47a4 blxns r4
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0+.* <[^>]*> 47cc blxns r9
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0+.* <[^>]*> 4724 bxns r4
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0+.* <[^>]*> 474c bxns r9
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0+.* <[^>]*> e841 f080 tta r0, r1
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0+.* <[^>]*> e849 f880 tta r8, r9
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0+.* <[^>]*> e841 f0c0 ttat r0, r1
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0+.* <[^>]*> e849 f8c0 ttat r8, r9
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10
gas/testsuite/gas/arm/archv8m-cmse-main-2.d
Normal file
10
gas/testsuite/gas/arm/archv8m-cmse-main-2.d
Normal file
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@ -0,0 +1,10 @@
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#name: ARMv8-M Mainline Security Extensions instructions (2)
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#source: archv8m-cmse-main.s
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#as: -march=armv8-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+.* <[^>]*> ec31 0a00 vlldm r1
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0+.* <[^>]*> ec22 0a00 vlstm r2
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5
gas/testsuite/gas/arm/archv8m-cmse-main.s
Normal file
5
gas/testsuite/gas/arm/archv8m-cmse-main.s
Normal file
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@ -0,0 +1,5 @@
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.thumb
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.syntax unified
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vlldm r1
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vlstm r2
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32
gas/testsuite/gas/arm/archv8m-cmse-msr-base.d
Normal file
32
gas/testsuite/gas/arm/archv8m-cmse-msr-base.d
Normal file
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@ -0,0 +1,32 @@
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#name: ARMv8-M Baseline Security Extensions MSR/MRS instructions
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#source: archv8m-cmse-msr.s
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#as: -march=armv8-m.base
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8888 msr MSP_NS, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8889 msr PSP_NS, r0
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8888 msr MSP_NS, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8889 msr PSP_NS, r0
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
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0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
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0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
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32
gas/testsuite/gas/arm/archv8m-cmse-msr-main.d
Normal file
32
gas/testsuite/gas/arm/archv8m-cmse-msr-main.d
Normal file
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#name: ARMv8-M Mainline Security Extensions MSR/MRS instructions
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#source: archv8m-cmse-msr.s
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#as: -march=armv8-m.main
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#objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8888 msr MSP_NS, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8889 msr PSP_NS, r0
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8808 msr MSP, r0
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0+.* <[^>]*> f380 8888 msr MSP_NS, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8809 msr PSP, r0
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0+.* <[^>]*> f380 8889 msr PSP_NS, r0
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
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0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8008 mrs r0, MSP
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0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
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0+.* <[^>]*> f3ef 8009 mrs r0, PSP
|
||||
0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
|
||||
24
gas/testsuite/gas/arm/archv8m-cmse-msr.s
Normal file
24
gas/testsuite/gas/arm/archv8m-cmse-msr.s
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
msr MSP, r0
|
||||
msr MSP_S, r0
|
||||
msr MSP_NS, r0
|
||||
msr PSP, r0
|
||||
msr PSP_S, r0
|
||||
msr PSP_NS, r0
|
||||
msr msp, r0
|
||||
msr msp_s, r0
|
||||
msr msp_ns, r0
|
||||
msr psp, r0
|
||||
msr psp_s, r0
|
||||
msr psp_ns, r0
|
||||
mrs r0, MSP
|
||||
mrs r0, MSP_S
|
||||
mrs r0, MSP_NS
|
||||
mrs r0, PSP
|
||||
mrs r0, PSP_S
|
||||
mrs r0, PSP_NS
|
||||
mrs r0, msp
|
||||
mrs r0, msp_s
|
||||
mrs r0, msp_ns
|
||||
mrs r0, psp
|
||||
mrs r0, psp_s
|
||||
mrs r0, psp_ns
|
||||
12
gas/testsuite/gas/arm/archv8m-cmse.s
Normal file
12
gas/testsuite/gas/arm/archv8m-cmse.s
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
.thumb
|
||||
.syntax unified
|
||||
|
||||
sg
|
||||
blxns r4
|
||||
blxns r9
|
||||
bxns r4
|
||||
bxns r9
|
||||
tta r0, r1
|
||||
tta r8, r9
|
||||
ttat r0, r1
|
||||
ttat r8, r9
|
||||
|
|
@ -1,3 +1,10 @@
|
|||
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||||
|
||||
* opcode/arm.h (ARM_EXT2_V8M_MAIN): new feature bit.
|
||||
(ARM_AEXT2_V8M_MAIN): New architecture extension feature set.
|
||||
(ARM_ARCH_V8M_MAIN): Use ARM_AEXT2_V8M_MAIN instead of ARM_AEXT2_V8M
|
||||
for the high core bits.
|
||||
|
||||
2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
|
||||
|
||||
* opcode/arc.h (ARC_SYNTAX_1OP): Declare
|
||||
|
|
|
|||
|
|
@ -62,6 +62,7 @@
|
|||
#define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */
|
||||
#define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */
|
||||
#define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */
|
||||
#define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */
|
||||
|
||||
/* Co-processor space extensions. */
|
||||
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
|
||||
|
|
@ -150,6 +151,7 @@
|
|||
#define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV)
|
||||
#define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
|
||||
#define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M)
|
||||
#define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN)
|
||||
|
||||
/* Processors with specific extensions in the co-processor space. */
|
||||
#define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
|
||||
|
|
@ -265,7 +267,8 @@
|
|||
#define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \
|
||||
CRC_EXT_ARMV8)
|
||||
#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)
|
||||
#define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, ARM_AEXT2_V8M)
|
||||
#define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \
|
||||
ARM_AEXT2_V8M_MAIN)
|
||||
|
||||
/* Some useful combinations: */
|
||||
#define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)
|
||||
|
|
|
|||
|
|
@ -1,3 +1,14 @@
|
|||
2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||||
|
||||
* arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
|
||||
Mainline Security Extensions instructions.
|
||||
(thumb_opcodes): Add entries for narrow ARMv8-M Security
|
||||
Extensions instructions.
|
||||
(thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
|
||||
instructions.
|
||||
(psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
|
||||
special registers.
|
||||
|
||||
2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
|
||||
|
||||
* sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
|
||||
|
|
|
|||
|
|
@ -408,6 +408,12 @@ static const struct opcode32 coprocessor_opcodes[] =
|
|||
{ARM_FEATURE_COPROC (FPU_FPA_EXT_V2),
|
||||
0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
|
||||
|
||||
/* ARMv8-M Mainline Security Extensions instructions. */
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
|
||||
0xec300a00, 0xfff0ffff, "vlldm\t%16-19r"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN),
|
||||
0xec200a00, 0xfff0ffff, "vlstm\t%16-19r"},
|
||||
|
||||
/* Register load/store. */
|
||||
{ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1),
|
||||
0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
|
||||
|
|
@ -2469,6 +2475,10 @@ static const struct opcode16 thumb_opcodes[] =
|
|||
{
|
||||
/* Thumb instructions. */
|
||||
|
||||
/* ARMv8-M Security Extensions instructions. */
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4784, 0xff87, "blxns\t%3-6r"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0x4704, 0xff07, "bxns\t%3-6r"},
|
||||
|
||||
/* ARM V8 instructions. */
|
||||
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xbf50, 0xffff, "sevl%c"},
|
||||
{ARM_FEATURE_CORE_LOW (ARM_EXT_V8), 0xba80, 0xffc0, "hlt\t%0-5x"},
|
||||
|
|
@ -2674,11 +2684,16 @@ static const struct opcode16 thumb_opcodes[] =
|
|||
makes heavy use of special-case bit patterns. */
|
||||
static const struct opcode32 thumb32_opcodes[] =
|
||||
{
|
||||
/* V8-M instructions. */
|
||||
/* ARMv8-M and ARMv8-M Security Extensions instructions. */
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M), 0xe97fe97f, 0xffffffff, "sg"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
||||
0xe840f000, 0xfff0f0ff, "tt\t%8-11r, %16-19r"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
||||
0xe840f040, 0xfff0f0ff, "ttt\t%8-11r, %16-19r"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
||||
0xe840f080, 0xfff0f0ff, "tta\t%8-11r, %16-19r"},
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M),
|
||||
0xe840f0c0, 0xfff0f0ff, "ttat\t%8-11r, %16-19r"},
|
||||
|
||||
/* ARM V8.2 RAS extension instructions. */
|
||||
{ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A),
|
||||
|
|
@ -5426,6 +5441,8 @@ psr_name (int regno)
|
|||
case 18: return "BASEPRI_MAX";
|
||||
case 19: return "FAULTMASK";
|
||||
case 20: return "CONTROL";
|
||||
case 0x88: return "MSP_NS";
|
||||
case 0x89: return "PSP_NS";
|
||||
default: return "<unknown>";
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue