include/opcode/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips.h: Document new VU0 operand characters. (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types. (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R) (OP_REG_R5900_ACC): New mips_reg_operand_types. (INSN2_VU0_CHANNEL_SUFFIX): New macro. (mips_vu0_channel_mask): Declare. opcodes/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (print_vu0_channel): New function. (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (print_insn_args): Handle '#'. (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX. * mips-opc.c (mips_vu0_channel_mask): New constant. (decode_mips_operand): Handle new VU0 operand types. (VU0, VU0CH): New macros. (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E" for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2. Use "+6" rather than "G" for QMFC2 and QMTC2. gas/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> Richard Sandiford <rdsandiford@googlemail.com> * config/tc-mips.c (MAX_OPERANDS): Bump to 6. (RWARN): Bump to 0x8000000. (RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R) (RTYPE_R5900_ACC): New register types. (RTYPE_MASK): Include them. (R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New macros. (reg_names): Include them. (mips_parse_register_1): New function, split out from... (mips_parse_register): ...here. Add a channels_ptr parameter. Look for VU0 channel suffixes when nonnull. (reg_lookup): Update the call to mips_parse_register. (mips_parse_vu0_channels): New function. (OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types. (mips_operand_token): Add a "channels" field to the union. Extend the comment above "ch" to OT_DOUBLE_CHAR. (mips_parse_base_start): Match -- and ++. Handle channel suffixes. (mips_parse_argument_token): Handle channel suffixes here too. (validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX. Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits. Handle '#' formats. (md_begin): Register $vfN and $vfI registers. (operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC. (match_vu0_suffix_operand): New function. (match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX. (macro): Use "+7" rather than "E" for LDQ2 and STQ2. (mips_lookup_insn): New function. (mips_ip): Use it. Allow "+K" operands to be elided at the end of an instruction. Handle '#' sequences. gas/testsuite/ 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de> * gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric coprocessor registers. * gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d, gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d, gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests. * gas/mips/mips.exp: Run them.
This commit is contained in:
Richard Sandiford
parent
ba5b2044e8
commit
14daeee3ae
16 changed files with 20949 additions and 137 deletions
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@ -1,3 +1,38 @@
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2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
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Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
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(RWARN): Bump to 0x8000000.
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(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
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(RTYPE_R5900_ACC): New register types.
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(RTYPE_MASK): Include them.
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(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
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macros.
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(reg_names): Include them.
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(mips_parse_register_1): New function, split out from...
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(mips_parse_register): ...here. Add a channels_ptr parameter.
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Look for VU0 channel suffixes when nonnull.
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(reg_lookup): Update the call to mips_parse_register.
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(mips_parse_vu0_channels): New function.
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(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
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(mips_operand_token): Add a "channels" field to the union.
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Extend the comment above "ch" to OT_DOUBLE_CHAR.
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(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
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(mips_parse_argument_token): Handle channel suffixes here too.
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(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
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Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
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Handle '#' formats.
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(md_begin): Register $vfN and $vfI registers.
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(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
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(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
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OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
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(match_vu0_suffix_operand): New function.
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(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
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(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
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(mips_lookup_insn): New function.
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(mips_ip): Use it. Allow "+K" operands to be elided at the end
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of an instruction. Handle '#' sequences.
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2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (macro, mips16_macro): Create an array of operand
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@ -690,7 +690,7 @@ static int mips_debug = 0;
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static struct mips_cl_insn history[1 + MAX_NOPS];
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/* Arrays of operands for each instruction. */
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#define MAX_OPERANDS 5
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#define MAX_OPERANDS 6
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struct mips_operand_array {
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const struct mips_operand *operand[MAX_OPERANDS];
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};
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@ -2206,18 +2206,24 @@ struct regname {
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unsigned int num;
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};
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#define RTYPE_MASK 0x1ff00
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#define RTYPE_NUM 0x00100
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#define RTYPE_FPU 0x00200
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#define RTYPE_FCC 0x00400
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#define RTYPE_VEC 0x00800
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#define RTYPE_GP 0x01000
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#define RTYPE_CP0 0x02000
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#define RTYPE_PC 0x04000
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#define RTYPE_ACC 0x08000
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#define RTYPE_CCC 0x10000
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#define RNUM_MASK 0x000ff
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#define RWARN 0x80000
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#define RNUM_MASK 0x00000ff
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#define RTYPE_MASK 0x0efff00
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#define RTYPE_NUM 0x0000100
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#define RTYPE_FPU 0x0000200
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#define RTYPE_FCC 0x0000400
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#define RTYPE_VEC 0x0000800
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#define RTYPE_GP 0x0001000
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#define RTYPE_CP0 0x0002000
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#define RTYPE_PC 0x0004000
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#define RTYPE_ACC 0x0008000
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#define RTYPE_CCC 0x0010000
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#define RTYPE_VI 0x0020000
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#define RTYPE_VF 0x0040000
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#define RTYPE_R5900_I 0x0080000
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#define RTYPE_R5900_Q 0x0100000
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#define RTYPE_R5900_R 0x0200000
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#define RTYPE_R5900_ACC 0x0400000
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#define RWARN 0x8000000
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#define GENERIC_REGISTER_NUMBERS \
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{"$0", RTYPE_NUM | 0}, \
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@ -2403,6 +2409,18 @@ struct regname {
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{"$v30", RTYPE_VEC | 30}, \
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{"$v31", RTYPE_VEC | 31}
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#define R5900_I_NAMES \
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{"$I", RTYPE_R5900_I | 0}
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#define R5900_Q_NAMES \
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{"$Q", RTYPE_R5900_Q | 0}
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#define R5900_R_NAMES \
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{"$R", RTYPE_R5900_R | 0}
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#define R5900_ACC_NAMES \
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{"$ACC", RTYPE_R5900_ACC | 0 }
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#define MIPS_DSP_ACCUMULATOR_NAMES \
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{"$ac0", RTYPE_ACC | 0}, \
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{"$ac1", RTYPE_ACC | 1}, \
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@ -2423,6 +2441,10 @@ static const struct regname reg_names[] = {
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MIPS16_SPECIAL_REGISTER_NAMES,
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MDMX_VECTOR_REGISTER_NAMES,
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R5900_I_NAMES,
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R5900_Q_NAMES,
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R5900_R_NAMES,
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R5900_ACC_NAMES,
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MIPS_DSP_ACCUMULATOR_NAMES,
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{0, 0}
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};
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@ -2450,24 +2472,14 @@ mips_prefer_vec_regno (unsigned int symval)
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return symval;
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}
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/* Return true if the string at *SPTR is a valid register name. If so,
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move *SPTR past the register and store the register's symbol value
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in *SYMVAL. This symbol value includes the register number
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(RNUM_MASK) and register type (RTYPE_MASK). */
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/* Return true if string [S, E) is a valid register name, storing its
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symbol value in *SYMVAL_PTR if so. */
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static bfd_boolean
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mips_parse_register (char **sptr, unsigned int *symval)
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mips_parse_register_1 (char *s, char *e, unsigned int *symval_ptr)
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{
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symbolS *symbol;
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char *s, *e;
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char save_c;
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/* Find end of name. */
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s = e = *sptr;
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if (is_name_beginner (*e))
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++e;
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while (is_part_of_name (*e))
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++e;
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symbolS *symbol;
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/* Terminate name. */
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save_c = *e;
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@ -2480,8 +2492,63 @@ mips_parse_register (char **sptr, unsigned int *symval)
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if (!symbol || S_GET_SEGMENT (symbol) != reg_section)
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return FALSE;
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*symval_ptr = S_GET_VALUE (symbol);
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return TRUE;
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}
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/* Return true if the string at *SPTR is a valid register name. Allow it
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to have a VU0-style channel suffix of the form x?y?z?w? if CHANNELS_PTR
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is nonnull.
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When returning true, move *SPTR past the register, store the
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register's symbol value in *SYMVAL_PTR and the channel mask in
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*CHANNELS_PTR (if nonnull). The symbol value includes the register
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number (RNUM_MASK) and register type (RTYPE_MASK). The channel mask
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is a 4-bit value of the form XYZW and is 0 if no suffix was given. */
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static bfd_boolean
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mips_parse_register (char **sptr, unsigned int *symval_ptr,
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unsigned int *channels_ptr)
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{
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char *s, *e, *m;
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const char *q;
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unsigned int channels, symval, bit;
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/* Find end of name. */
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s = e = *sptr;
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if (is_name_beginner (*e))
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++e;
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while (is_part_of_name (*e))
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++e;
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channels = 0;
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if (!mips_parse_register_1 (s, e, &symval))
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{
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if (!channels_ptr)
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return FALSE;
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/* Eat characters from the end of the string that are valid
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channel suffixes. The preceding register must be $ACC or
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end with a digit, so there is no ambiguity. */
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bit = 1;
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m = e;
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for (q = "wzyx"; *q; q++, bit <<= 1)
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if (m > s && m[-1] == *q)
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{
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--m;
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channels |= bit;
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}
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if (channels == 0
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|| !mips_parse_register_1 (s, m, &symval)
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|| (symval & (RTYPE_VI | RTYPE_VF | RTYPE_R5900_ACC)) == 0)
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return FALSE;
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}
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*sptr = e;
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*symval = S_GET_VALUE (symbol);
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*symval_ptr = symval;
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if (channels_ptr)
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*channels_ptr = channels;
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return TRUE;
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}
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@ -2494,7 +2561,7 @@ reg_lookup (char **s, unsigned int types, unsigned int *regnop)
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{
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unsigned int regno;
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if (mips_parse_register (s, ®no))
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if (mips_parse_register (s, ®no, NULL))
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{
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if (types & RTYPE_VEC)
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regno = mips_prefer_vec_regno (regno);
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@ -2514,11 +2581,32 @@ reg_lookup (char **s, unsigned int types, unsigned int *regnop)
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return regno <= RNUM_MASK;
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}
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/* Parse a VU0 "x?y?z?w?" channel mask at S and store the associated
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mask in *CHANNELS. Return a pointer to the first unconsumed character. */
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static char *
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mips_parse_vu0_channels (char *s, unsigned int *channels)
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{
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unsigned int i;
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*channels = 0;
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for (i = 0; i < 4; i++)
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if (*s == "xyzw"[i])
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{
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*channels |= 1 << (3 - i);
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++s;
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}
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return s;
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}
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/* Token types for parsed operand lists. */
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enum mips_operand_token_type {
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/* A plain register, e.g. $f2. */
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OT_REG,
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/* A 4-bit XYZW channel mask. */
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OT_CHANNELS,
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/* An element of a vector, e.g. $v0[1]. */
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OT_REG_ELEMENT,
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@ -2535,6 +2623,9 @@ enum mips_operand_token_type {
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before OT_REGs. */
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OT_CHAR,
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/* A doubled character, either "--" or "++". */
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OT_DOUBLE_CHAR,
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/* The end of the operand list. */
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OT_END
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};
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@ -2549,6 +2640,9 @@ struct mips_operand_token
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/* The register symbol value for an OT_REG. */
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unsigned int regno;
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/* The 4-bit channel mask for an OT_CHANNEL_SUFFIX. */
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unsigned int channels;
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/* The register symbol value and index for an OT_REG_ELEMENT. */
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struct {
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unsigned int regno;
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@ -2577,7 +2671,7 @@ struct mips_operand_token
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int length;
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} flt;
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/* The character represented by an OT_CHAR. */
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/* The character represented by an OT_CHAR or OT_DOUBLE_CHAR. */
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char ch;
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} u;
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};
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@ -2603,22 +2697,56 @@ static char *
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mips_parse_base_start (char *s)
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{
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struct mips_operand_token token;
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unsigned int regno;
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unsigned int regno, channels;
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bfd_boolean decrement_p;
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if (*s != '(')
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return 0;
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++s;
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SKIP_SPACE_TABS (s);
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if (!mips_parse_register (&s, ®no))
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/* Only match "--" as part of a base expression. In other contexts "--X"
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is a double negative. */
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decrement_p = (s[0] == '-' && s[1] == '-');
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if (decrement_p)
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{
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s += 2;
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SKIP_SPACE_TABS (s);
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}
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/* Allow a channel specifier because that leads to better error messages
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than treating something like "$vf0x++" as an expression. */
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if (!mips_parse_register (&s, ®no, &channels))
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return 0;
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token.u.ch = '(';
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mips_add_token (&token, OT_CHAR);
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if (decrement_p)
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{
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token.u.ch = '-';
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mips_add_token (&token, OT_DOUBLE_CHAR);
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}
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token.u.regno = regno;
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mips_add_token (&token, OT_REG);
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if (channels)
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{
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token.u.channels = channels;
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mips_add_token (&token, OT_CHANNELS);
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}
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/* For consistency, only match "++" as part of base expressions too. */
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SKIP_SPACE_TABS (s);
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if (s[0] == '+' && s[1] == '+')
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{
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s += 2;
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token.u.ch = '+';
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mips_add_token (&token, OT_DOUBLE_CHAR);
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}
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return s;
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}
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@ -2631,7 +2759,7 @@ static char *
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mips_parse_argument_token (char *s, char float_format)
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{
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char *end, *save_in, *err;
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unsigned int regno1, regno2;
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unsigned int regno1, regno2, channels;
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struct mips_operand_token token;
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/* First look for "($reg", since we want to treat that as an
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@ -2650,15 +2778,26 @@ mips_parse_argument_token (char *s, char float_format)
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}
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/* Handle tokens that start with a register. */
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if (mips_parse_register (&s, ®no1))
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if (mips_parse_register (&s, ®no1, &channels))
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{
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if (channels)
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{
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/* A register and a VU0 channel suffix. */
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token.u.regno = regno1;
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mips_add_token (&token, OT_REG);
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token.u.channels = channels;
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mips_add_token (&token, OT_CHANNELS);
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return s;
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}
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SKIP_SPACE_TABS (s);
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if (*s == '-')
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{
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/* A register range. */
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++s;
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SKIP_SPACE_TABS (s);
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if (!mips_parse_register (&s, ®no2))
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if (!mips_parse_register (&s, ®no2, NULL))
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{
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insn_error = _("Invalid register range");
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return 0;
|
||||
|
|
@ -2897,6 +3036,8 @@ validate_mips_insn (const struct mips_opcode *opcode,
|
|||
}
|
||||
used_bits = 0;
|
||||
opno = 0;
|
||||
if (opcode->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
|
||||
used_bits = mips_insert_operand (&mips_vu0_channel_mask, used_bits, -1);
|
||||
for (s = opcode->args; *s; ++s)
|
||||
switch (*s)
|
||||
{
|
||||
|
|
@ -2905,6 +3046,10 @@ validate_mips_insn (const struct mips_opcode *opcode,
|
|||
case ')':
|
||||
break;
|
||||
|
||||
case '#':
|
||||
s++;
|
||||
break;
|
||||
|
||||
default:
|
||||
if (!decode_operand)
|
||||
operand = decode_mips16_operand (*s, FALSE);
|
||||
|
|
@ -2918,9 +3063,9 @@ validate_mips_insn (const struct mips_opcode *opcode,
|
|||
}
|
||||
gas_assert (opno < MAX_OPERANDS);
|
||||
operands->operand[opno] = operand;
|
||||
if (operand)
|
||||
if (operand && operand->type != OP_VU0_MATCH_SUFFIX)
|
||||
{
|
||||
used_bits |= ((1 << operand->size) - 1) << operand->lsb;
|
||||
used_bits = mips_insert_operand (operand, used_bits, -1);
|
||||
if (operand->type == OP_MDMX_IMM_REG)
|
||||
/* Bit 5 is the format selector (OB vs QH). The opcode table
|
||||
has separate entries for each format. */
|
||||
|
|
@ -3160,6 +3305,23 @@ md_begin (void)
|
|||
reg_names_o32[i].num, /* & RNUM_MASK, */
|
||||
&zero_address_frag));
|
||||
|
||||
for (i = 0; i < 32; i++)
|
||||
{
|
||||
char regname[7];
|
||||
|
||||
/* R5900 VU0 floating-point register. */
|
||||
regname[sizeof (rename) - 1] = 0;
|
||||
snprintf (regname, sizeof (regname) - 1, "$vf%d", i);
|
||||
symbol_table_insert (symbol_new (regname, reg_section,
|
||||
RTYPE_VF | i, &zero_address_frag));
|
||||
|
||||
/* R5900 VU0 integer register. */
|
||||
snprintf (regname, sizeof (regname) - 1, "$vi%d", i);
|
||||
symbol_table_insert (symbol_new (regname, reg_section,
|
||||
RTYPE_VI | i, &zero_address_frag));
|
||||
|
||||
}
|
||||
|
||||
obstack_init (&mips_operand_tokens);
|
||||
|
||||
mips_no_prev_insn ();
|
||||
|
|
@ -3701,6 +3863,8 @@ operand_reg_mask (const struct mips_cl_insn *insn,
|
|||
case OP_REPEAT_DEST_REG:
|
||||
case OP_REPEAT_PREV_REG:
|
||||
case OP_PC:
|
||||
case OP_VU0_SUFFIX:
|
||||
case OP_VU0_MATCH_SUFFIX:
|
||||
abort ();
|
||||
|
||||
case OP_REG:
|
||||
|
|
@ -4113,6 +4277,24 @@ convert_reg_type (const struct mips_opcode *opcode,
|
|||
|
||||
case OP_REG_HW:
|
||||
return RTYPE_NUM;
|
||||
|
||||
case OP_REG_VI:
|
||||
return RTYPE_NUM | RTYPE_VI;
|
||||
|
||||
case OP_REG_VF:
|
||||
return RTYPE_NUM | RTYPE_VF;
|
||||
|
||||
case OP_REG_R5900_I:
|
||||
return RTYPE_R5900_I;
|
||||
|
||||
case OP_REG_R5900_Q:
|
||||
return RTYPE_R5900_Q;
|
||||
|
||||
case OP_REG_R5900_R:
|
||||
return RTYPE_R5900_R;
|
||||
|
||||
case OP_REG_R5900_ACC:
|
||||
return RTYPE_R5900_ACC;
|
||||
}
|
||||
abort ();
|
||||
}
|
||||
|
|
@ -5046,6 +5228,42 @@ match_float_constant (struct mips_arg_info *arg, expressionS *imm,
|
|||
return TRUE;
|
||||
}
|
||||
|
||||
/* OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX matcher; MATCH_P selects between
|
||||
them. */
|
||||
|
||||
static bfd_boolean
|
||||
match_vu0_suffix_operand (struct mips_arg_info *arg,
|
||||
const struct mips_operand *operand,
|
||||
bfd_boolean match_p)
|
||||
{
|
||||
unsigned int uval;
|
||||
|
||||
/* The operand can be an XYZW mask or a single 2-bit channel index
|
||||
(with X being 0). */
|
||||
gas_assert (operand->size == 2 || operand->size == 4);
|
||||
|
||||
/* The suffix can be omitted when matching a previous 4-bit mask. */
|
||||
if (arg->token->type != OT_CHANNELS)
|
||||
return operand->size == 4 && match_p;
|
||||
|
||||
uval = arg->token->u.channels;
|
||||
if (operand->size == 2)
|
||||
{
|
||||
/* Check that a single bit is set and convert it into a 2-bit index. */
|
||||
if ((uval & -uval) != uval)
|
||||
return FALSE;
|
||||
uval = 4 - ffs (uval);
|
||||
}
|
||||
|
||||
if (match_p && insn_extract_operand (arg->insn, operand) != uval)
|
||||
return FALSE;
|
||||
|
||||
++arg->token;
|
||||
if (!match_p)
|
||||
insn_insert_operand (arg->insn, operand, uval);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/* S is the text seen for ARG. Match it against OPERAND. Return the end
|
||||
of the argument text if the match is successful, otherwise return null. */
|
||||
|
||||
|
|
@ -5102,6 +5320,12 @@ match_operand (struct mips_arg_info *arg,
|
|||
|
||||
case OP_PC:
|
||||
return match_pc_operand (arg);
|
||||
|
||||
case OP_VU0_SUFFIX:
|
||||
return match_vu0_suffix_operand (arg, operand, FALSE);
|
||||
|
||||
case OP_VU0_MATCH_SUFFIX:
|
||||
return match_vu0_suffix_operand (arg, operand, TRUE);
|
||||
}
|
||||
abort ();
|
||||
}
|
||||
|
|
@ -9913,7 +10137,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||
goto ld_st;
|
||||
case M_LQC2_AB:
|
||||
s = "lqc2";
|
||||
fmt = "E,o(b)";
|
||||
fmt = "+7,o(b)";
|
||||
/* Itbl support may require additional care here. */
|
||||
coproc = 1;
|
||||
goto ld_st;
|
||||
|
|
@ -10077,7 +10301,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||
goto ld_st;
|
||||
case M_SQC2_AB:
|
||||
s = "sqc2";
|
||||
fmt = "E,o(b)";
|
||||
fmt = "+7,o(b)";
|
||||
/* Itbl support may require additional care here. */
|
||||
coproc = 1;
|
||||
goto ld_st;
|
||||
|
|
@ -12078,6 +12302,74 @@ mips16_macro (struct mips_cl_insn *ip)
|
|||
}
|
||||
}
|
||||
|
||||
/* Look up instruction [START, START + LENGTH) in HASH. Record any extra
|
||||
opcode bits in *OPCODE_EXTRA. */
|
||||
|
||||
static struct mips_opcode *
|
||||
mips_lookup_insn (struct hash_control *hash, const char *start,
|
||||
unsigned int length, unsigned int *opcode_extra)
|
||||
{
|
||||
char *name, *dot, *p;
|
||||
unsigned int mask, suffix;
|
||||
size_t opend;
|
||||
struct mips_opcode *insn;
|
||||
|
||||
/* Make a copy of the instruction so that we can fiddle with it. */
|
||||
name = alloca (length + 1);
|
||||
memcpy (name, start, length);
|
||||
name[length] = '\0';
|
||||
|
||||
/* Look up the instruction as-is. */
|
||||
insn = (struct mips_opcode *) hash_find (hash, name);
|
||||
if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) == 0)
|
||||
return insn;
|
||||
|
||||
dot = strchr (name, '.');
|
||||
if (dot && dot[1])
|
||||
{
|
||||
/* Try to interpret the text after the dot as a VU0 channel suffix. */
|
||||
p = mips_parse_vu0_channels (dot + 1, &mask);
|
||||
if (*p == 0 && mask != 0)
|
||||
{
|
||||
*dot = 0;
|
||||
insn = (struct mips_opcode *) hash_find (hash, name);
|
||||
*dot = '.';
|
||||
if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) != 0)
|
||||
{
|
||||
*opcode_extra |= mask << mips_vu0_channel_mask.lsb;
|
||||
return insn;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (mips_opts.micromips)
|
||||
{
|
||||
/* See if there's an instruction size override suffix,
|
||||
either `16' or `32', at the end of the mnemonic proper,
|
||||
that defines the operation, i.e. before the first `.'
|
||||
character if any. Strip it and retry. */
|
||||
opend = dot != NULL ? dot - name : length;
|
||||
if (opend >= 3 && name[opend - 2] == '1' && name[opend - 1] == '6')
|
||||
suffix = 2;
|
||||
else if (name[opend - 2] == '3' && name[opend - 1] == '2')
|
||||
suffix = 4;
|
||||
else
|
||||
suffix = 0;
|
||||
if (suffix)
|
||||
{
|
||||
memcpy (name + opend - 2, name + opend, length - opend + 1);
|
||||
insn = (struct mips_opcode *) hash_find (hash, name);
|
||||
if (insn && (insn->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX) == 0)
|
||||
{
|
||||
forced_insn_length = suffix;
|
||||
return insn;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Assemble an instruction into its binary format. If the instruction
|
||||
is a macro, set imm_expr, imm2_expr and offset_expr to the values
|
||||
associated with "I", "+I" and "A" operands respectively. Otherwise
|
||||
|
|
@ -12095,16 +12387,14 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
|||
struct hash_control *hash;
|
||||
const char *args;
|
||||
char c = 0;
|
||||
struct mips_opcode *insn;
|
||||
long opend;
|
||||
char *name;
|
||||
char *dot;
|
||||
struct mips_opcode *first, *insn;
|
||||
char format;
|
||||
long end;
|
||||
size_t end;
|
||||
const struct mips_operand *operand;
|
||||
struct mips_arg_info arg;
|
||||
struct mips_operand_token *tokens;
|
||||
bfd_boolean optional_reg;
|
||||
unsigned int opcode_extra;
|
||||
|
||||
insn_error = NULL;
|
||||
|
||||
|
|
@ -12120,50 +12410,22 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
|||
}
|
||||
forced_insn_length = 0;
|
||||
insn = NULL;
|
||||
opcode_extra = 0;
|
||||
|
||||
/* We first try to match an instruction up to a space or to the end. */
|
||||
for (end = 0; str[end] != '\0' && !ISSPACE (str[end]); end++)
|
||||
continue;
|
||||
|
||||
/* Make a copy of the instruction so that we can fiddle with it. */
|
||||
name = alloca (end + 1);
|
||||
memcpy (name, str, end);
|
||||
name[end] = '\0';
|
||||
|
||||
for (;;)
|
||||
{
|
||||
insn = (struct mips_opcode *) hash_find (hash, name);
|
||||
|
||||
if (insn != NULL || !mips_opts.micromips)
|
||||
break;
|
||||
if (forced_insn_length)
|
||||
break;
|
||||
|
||||
/* See if there's an instruction size override suffix,
|
||||
either `16' or `32', at the end of the mnemonic proper,
|
||||
that defines the operation, i.e. before the first `.'
|
||||
character if any. Strip it and retry. */
|
||||
dot = strchr (name, '.');
|
||||
opend = dot != NULL ? dot - name : end;
|
||||
if (opend < 3)
|
||||
break;
|
||||
if (name[opend - 2] == '1' && name[opend - 1] == '6')
|
||||
forced_insn_length = 2;
|
||||
else if (name[opend - 2] == '3' && name[opend - 1] == '2')
|
||||
forced_insn_length = 4;
|
||||
else
|
||||
break;
|
||||
memcpy (name + opend - 2, name + opend, end - opend + 1);
|
||||
}
|
||||
first = insn = mips_lookup_insn (hash, str, end, &opcode_extra);
|
||||
if (insn == NULL)
|
||||
{
|
||||
insn_error = _("Unrecognized opcode");
|
||||
return;
|
||||
}
|
||||
|
||||
if (strcmp (name, "li.s") == 0)
|
||||
if (strcmp (insn->name, "li.s") == 0)
|
||||
format = 'f';
|
||||
else if (strcmp (name, "li.d") == 0)
|
||||
else if (strcmp (insn->name, "li.d") == 0)
|
||||
format = 'd';
|
||||
else
|
||||
format = 0;
|
||||
|
|
@ -12184,7 +12446,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
|||
bfd_boolean ok;
|
||||
bfd_boolean more_alts;
|
||||
|
||||
gas_assert (strcmp (insn->name, name) == 0);
|
||||
gas_assert (strcmp (insn->name, first->name) == 0);
|
||||
|
||||
ok = is_opcode_valid (insn);
|
||||
size_ok = is_size_valid (insn);
|
||||
|
|
@ -12240,6 +12502,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
|||
offset_reloc[2] = BFD_RELOC_UNUSED;
|
||||
|
||||
create_insn (ip, insn);
|
||||
ip->insn_opcode |= opcode_extra;
|
||||
insn_error = NULL;
|
||||
memset (&arg, 0, sizeof (arg));
|
||||
arg.insn = ip;
|
||||
|
|
@ -12272,6 +12535,9 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
|||
if (strcmp (args, "(b)") == 0)
|
||||
args += 3;
|
||||
|
||||
if (args[0] == '+' && args[1] == 'K')
|
||||
args += 2;
|
||||
|
||||
/* Fail the match if there were too few operands. */
|
||||
if (*args)
|
||||
break;
|
||||
|
|
@ -12301,6 +12567,17 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
|||
continue;
|
||||
break;
|
||||
}
|
||||
if (*args == '#')
|
||||
{
|
||||
++args;
|
||||
if (arg.token->type == OT_DOUBLE_CHAR
|
||||
&& arg.token->u.ch == *args)
|
||||
{
|
||||
++arg.token;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Handle special macro operands. Work out the properties of
|
||||
other operands. */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,12 @@
|
|||
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
|
||||
|
||||
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
|
||||
coprocessor registers.
|
||||
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
|
||||
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
|
||||
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
|
||||
* gas/mips/mips.exp: Run them.
|
||||
|
||||
2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* gas/mips/mips16-macro.s, gas/mips/mips16-macro.d: New test.
|
||||
|
|
|
|||
|
|
@ -1123,6 +1123,9 @@ if { [istarget mips*-*-vxworks*] } {
|
|||
run_dump_test "r5900-full"
|
||||
run_list_test "r5900-nollsc" "-mabi=o64 -march=r5900"
|
||||
run_dump_test "r5900-vu0"
|
||||
run_dump_test "r5900-full-vu0"
|
||||
run_dump_test "r5900-all-vu0"
|
||||
run_list_test "r5900-error-vu0" "-march=r5900"
|
||||
|
||||
run_list_test_arches "ext-ill" [mips_arch_list_matching mips64r2]
|
||||
|
||||
|
|
|
|||
9217
gas/testsuite/gas/mips/r5900-all-vu0.d
Normal file
9217
gas/testsuite/gas/mips/r5900-all-vu0.d
Normal file
File diff suppressed because it is too large
Load diff
9217
gas/testsuite/gas/mips/r5900-all-vu0.s
Normal file
9217
gas/testsuite/gas/mips/r5900-all-vu0.s
Normal file
File diff suppressed because it is too large
Load diff
677
gas/testsuite/gas/mips/r5900-error-vu0.l
Normal file
677
gas/testsuite/gas/mips/r5900-error-vu0.l
Normal file
|
|
@ -0,0 +1,677 @@
|
|||
.*: Assembler messages:
|
||||
.*: Error: Illegal operands `vabs\.w \$vf0w,\$vf0z'
|
||||
.*: Error: Illegal operands `vabs\.w \$vf0z,\$vf31w'
|
||||
.*: Error: Illegal operands `vabs\.xw \$vf0xw,\$vf0w'
|
||||
.*: Error: Illegal operands `vabs\.xw \$vf0x,\$vf31xw'
|
||||
.*: Error: Illegal operands `vabs\.xyzw \$vf0xyz,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vaddai\.w \$ACCw,\$vf0w,\$Q'
|
||||
.*: Error: Illegal operands `vaddai\.w \$ACCz,\$vf0w,\$Q'
|
||||
.*: Error: Illegal operands `vaddai\.xyzw \$ACCxyw,\$vf0xyzw,\$I'
|
||||
.*: Error: Illegal operands `vaddaq\.w \$ACCw,\$vf31z,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.x \$ACCx,\$vf0w,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.x \$ACCw,\$vf1x,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.xw \$ACCxw,\$vf1z,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.xw \$ACCw,\$vf31xw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.xyw \$ACCxw,\$vf0xyw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.xyw \$ACCxyw,\$vf1yw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.xyzw \$ACCxyzw,\$vf1yzw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.z \$ACCxz,\$vf0xz,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.x \$ACCxz,\$vf1xz,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.xzw \$ACCxw,\$vf0xzw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.y \$ACCy,\$vf0y,\$R'
|
||||
.*: Error: Illegal operands `vaddaq\.y \$ACCy,\$vf1y,\$I'
|
||||
.*: Error: Illegal operands `vaddaq\.yw \$ACCxyw,\$vf0yw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.yw \$ACCwy,\$vf1yw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.yw \$ACCyw,\$vf31wy,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.yz \$ACCy,\$vf0yz,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.yzw \$ACCxyzw,\$vf0yzw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.yzw \$ACCyzw,\$vf1xyzw,\$Q'
|
||||
.*: Error: Illegal operands `vaddaq\.yzw \$ACCyzw,\$vf31yzw,\$Qyzw'
|
||||
.*: Error: Illegal operands `vadda\.w \$ACCw,\$vf1w,\$vf2z'
|
||||
.*: Error: Illegal operands `vadda\.w \$ACCw,\$vf31w,\$vf0x'
|
||||
.*: Error: Illegal operands `vaddaw\.xyzw \$ACCxyzw,\$vf0xyzw,\$vf0x'
|
||||
.*: Error: Illegal operands `vaddaw\.xyzw \$ACCxyzw,\$vf0xyzw,\$vf31xyzw'
|
||||
.*: Error: Illegal operands `vaddaw\.xz \$ACCxyz,\$vf0xz,\$vf0w'
|
||||
.*: Error: Illegal operands `vaddaw\.xz \$ACCxzw,\$vf0xz,\$vf31w'
|
||||
.*: Error: Illegal operands `vaddaw\.xz \$ACCxz,\$vf1xyz,\$vf2w'
|
||||
.*: Error: Illegal operands `vaddaw\.xz \$ACCxz,\$vf31xzw,\$vf0w'
|
||||
.*: Error: Illegal operands `vaddaw\.xz \$ACCxz,\$vf31z,\$vf15w'
|
||||
.*: Error: Illegal operands `vaddaw\.xzw \$ACCxyzw,\$vf0xzw,\$vf0w'
|
||||
.*: Error: Illegal operands `vaddaw\.xzw \$ACC,\$vf0,\$vf31z'
|
||||
.*: Error: Illegal operands `vaddaw\.xzw \$ACCxzw,\$vf1xzw,\$vf2z'
|
||||
.*: Error: Illegal operands `vaddaw\.xzw \$ACCxzw,\$vf31xzw,\$vf0x'
|
||||
.*: Error: Illegal operands `vaddaw\.y \$ACCy,\$vf0y,\$vf0z'
|
||||
.*: Error: Illegal operands `vaddax\.w \$ACCw,\$vf0w,\$vf31z'
|
||||
.*: Error: Illegal operands `vaddax\.w \$ACC,\$vf1,\$vf2z'
|
||||
.*: Error: Illegal operands `vaddax\.w \$ACCw,\$vf31w,\$vf0w'
|
||||
.*: Error: Illegal operands `vaddax\.w \$ACCw,\$vf31w,\$vf15y'
|
||||
.*: Error: Illegal operands `vadda\.xw \$ACCxw,\$vf0xw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vadda\.xw \$ACCxw,\$vf0xw,\$vf31wx'
|
||||
.*: Error: Illegal operands `vaddax\.x \$ACCw,\$vf0x,\$vf0x'
|
||||
.*: Error: Illegal operands `vaddax\.x \$ACCx,\$vf0x,\$vf31w'
|
||||
.*: Error: Illegal operands `vaddax\.x \$ACCx,\$vf1x,\$vf2y'
|
||||
.*: Error: Illegal operands `vaddax\.x \$ACCx,\$vf31x,\$vf0z'
|
||||
.*: Error: Illegal operands `vaddax\.xw \$ACCxw,\$vf0xw,\$vf0y'
|
||||
.*: Error: Illegal operands `vaddax\.xw \$ACCxw,\$vf0xw,\$vf31z'
|
||||
.*: Error: Illegal operands `vaddax\.xw \$ACCxw,\$vf1xw,\$vf2w'
|
||||
.*: Error: Illegal operands `vaddax\.xw \$ACCxw,\$vf31wx,\$vf0'
|
||||
.*: Error: Illegal operands `vaddax\.xyzw \$ACC,\$vf1,\$vf2y'
|
||||
.*: Error: Illegal operands `vaddax\.xyzw \$ACC,\$vf31,\$vf0z'
|
||||
.*: Error: Illegal operands `vadda\.zw \$ACCzw,\$vf0zw,\$vf0wz'
|
||||
.*: Error: Illegal operands `vadda\.zw \$ACCzw,\$vf0w,\$vf31zw'
|
||||
.*: Error: Illegal operands `vadda\.zw \$ACCw,\$vf1zw,\$vf2zw'
|
||||
.*: Error: Illegal operands `vadda\.zw \$ACCxzw,\$vf31zw,\$vf0zw'
|
||||
.*: Error: Illegal operands `vadda\.zw \$ACCzw,\$vf31xzw,\$vf15zw'
|
||||
.*: Error: Illegal operands `vadda\.zw \$ACCzw,\$vf31zw,\$vf31yzw'
|
||||
.*: Error: Illegal operands `vaddaz\.x \$ACCx,\$vf0x,\$vf0x'
|
||||
.*: Error: Illegal operands `vaddaz\.x \$ACCx,\$vf0x,\$vf31y'
|
||||
.*: Error: Illegal operands `vaddaz\.xw \$ACCxw,\$vf31w,\$vf15z'
|
||||
.*: Error: Illegal operands `vaddaz\.xw \$ACCx,\$vf31xw,\$vf31z'
|
||||
.*: Error: Illegal operands `vaddaz\.xy \$ACCx,\$vf0xy,\$vf0z'
|
||||
.*: Error: Illegal operands `vaddaz\.xy \$ACCxyz,\$vf0xy,\$vf31z'
|
||||
.*: Error: Illegal operands `vaddaz\.y \$ACCx,\$vf31y,\$vf0z'
|
||||
.*: Error: Illegal operands `vaddaz\.yw \$ACCyw,\$vf0yw,\$a0'
|
||||
.*: Error: Illegal operands `vaddaz\.yw \$ACC,\$0,\$31'
|
||||
.*: Error: Illegal operands `vaddi\.w \$vf0w,\$vf31w,\$Q'
|
||||
.*: Error: Illegal operands `vaddi\.w \$vf1w,\$vf2w,\$R'
|
||||
.*: Error: Illegal operands `vaddi\.w \$vf31w,\$vf0w,\$ACC'
|
||||
.*: Error: Illegal operands `vaddi\.w \$vf31w,\$vf15w,\$ACCw'
|
||||
.*: Error: Illegal operands `vaddi\.xzw \$vf1xyzw,\$vf2xzw,\$I'
|
||||
.*: Error: Illegal operands `vaddi\.xzw \$vf31xw,\$vf0xzw,\$I'
|
||||
.*: Error: Illegal operands `vaddi\.xzw \$vf31xzw,\$vf15xzw,\$Ixzw'
|
||||
.*: Error: Illegal operands `vaddq\.w \$vf1w,\$vf2w,\$Qw'
|
||||
.*: Error: Illegal operands `vaddq\.w \$vf31w,\$vf0w,\$R'
|
||||
.*: Error: Illegal operands `vaddq\.w \$vf31w,\$vf15w,\$ACCw'
|
||||
.*: Error: Illegal operands `vaddq\.w \$vf31w,\$vf31w,\$ACC'
|
||||
.*: Error: Illegal operands `vaddq\.xyzw \$vf31xyzw,\$vf32xyzw,\$Q'
|
||||
.*: Error: Illegal operands `vaddq\.xyzw \$vf31xyzw,\$32,\$Q'
|
||||
.*: Error: Illegal operands `vaddq\.xz \$vf0xz,\$\-1,\$Q'
|
||||
.*: Error: Illegal operands `vaddw\.xyzw \$vf31xyzw,\$vf15xyzw,\$vf7z'
|
||||
.*: Error: Illegal operands `vaddx\.yw \$vf31yw,\$vf31yw,\$vf31y'
|
||||
.*: Error: Illegal operands `vadd\.xyz \$vf0xyz,\$vf0xyz,\$vf0xz'
|
||||
.*: Error: Illegal operands `vadd\.xyz \$vf0xyz,\$vf0xyz,\$vf31xyzw'
|
||||
.*: Error: Illegal operands `vadd\.xyz \$vf0xyz,\$vf31xyzw,\$vf0xyz'
|
||||
.*: Error: Illegal operands `vaddx\.yz \$vf0yz,\$vf0xyz,\$vf0x'
|
||||
.*: Error: Illegal operands `vaddz\.xyzw \$vf31xyzw,\$vf0xyzw,\$vf0x'
|
||||
.*: Error: Illegal operands `vaddz\.xyzw \$vf31xyzw,\$vf15xyzw,\$vf7y'
|
||||
.*: Error: Illegal operands `vaddz\.xyzw \$vf31xyzw,\$vf31xyzw,\$vf31w'
|
||||
.*: Error: Operand 1 of `vcallms' must be in the range \[0x0, 0x3fff8\], was \-1\.
|
||||
.*: Error: Operand 1 of `vcallms' must be in the range \[0x0, 0x3fff8\], was \-128\.
|
||||
.*: Error: Operand 1 of `vcallms' must be a factor of 8, was 0x1\.
|
||||
.*: Error: Operand 1 of `vcallms' must be a factor of 8, was 0x7\.
|
||||
.*: Error: Operand 1 of `vcallms' must be a factor of 8, was 0x4\.
|
||||
.*: Error: Operand 1 of `vcallms' must be a factor of 8, was 0x2\.
|
||||
.*: Error: Operand 1 of `vcallms' must be in the range \[0x0, 0x3fff8\], was 0x40000\.
|
||||
.*: Error: Operand 1 of `vcallms' must be in the range \[0x0, 0x3fff8\], was 0x40008\.
|
||||
.*: Error: Illegal operands `vclipw\.xyz \$vf0xyz,\$vf0x'
|
||||
.*: Error: Illegal operands `vclipw\.xyz \$vf0xyz,\$vf31y'
|
||||
.*: Error: Illegal operands `vclipw\.xyz \$vf1xyz,\$vf2z'
|
||||
.*: Error: Illegal operands `vdiv \$Q,\$vf0x,\$vf0xy'
|
||||
.*: Error: Illegal operands `vdiv \$Q,\$vf0xyzw,\$vf31y'
|
||||
.*: Error: Illegal operands `vdiv \$Q,\$vf1,\$vf2z'
|
||||
.*: Error: Illegal operands `vdiv \$Q,\$vf31x,\$vf15'
|
||||
.*: Error: Illegal operands `vdiv \$0,\$vf31w,\$vf31y'
|
||||
.*: Error: Illegal operands `vdiv \$Q,\$vf32y,\$vf0w'
|
||||
.*: Error: Illegal operands `vftoi0\.w \$vf0w,\$vf0x'
|
||||
.*: Error: Illegal operands `vftoi0\.w \$vf0x,\$vf31w'
|
||||
.*: Error: Illegal operands `vftoi0\.w \$vf1xw,\$vf2w'
|
||||
.*: Error: Illegal operands `vftoi0\.w \$vf31wx,\$vf0w'
|
||||
.*: Error: Illegal operands `vftoi0\.w \$vf31w,\$vf15wz'
|
||||
.*: Error: Illegal operands `vftoi12\.xw \$vf0xw,\$vf0w'
|
||||
.*: Error: Illegal operands `vftoi12\.xw \$vf0x,\$vf31xw'
|
||||
.*: Error: Illegal operands `vftoi15\.xyz \$vf31xyzw,\$vf15xyz'
|
||||
.*: Error: Illegal operands `vftoi15\.xyz \$vf31xyz,\$vf31xyzw'
|
||||
.*: Error: Illegal operands `vftoi15\.xyzw \$vf0xyzw,\$vf0xyz'
|
||||
.*: Error: Illegal operands `vftoi15\.y \$vf1y,\$vf2x'
|
||||
.*: Error: Illegal operands `vftoi15\.y \$vf31y,\$vf0w'
|
||||
.*: Error: Operand 3 of `viaddi' must be in the range \[\-16, 15\], was \-17\.
|
||||
.*: Error: Operand 3 of `viaddi' must be in the range \[\-16, 15\], was 16\.
|
||||
.*: Error: Operand 3 of `viaddi' must be in the range \[\-16, 15\], was 17\.
|
||||
.*: Error: Operand 3 of `viaddi' must be in the range \[\-16, 15\], was 32\.
|
||||
.*: Error: Operand 3 of `viaddi' must be in the range \[\-16, 15\], was 31\.
|
||||
.*: Error: Illegal operands `viand \$vi0xyzw,\$vi0,\$vi0'
|
||||
.*: Error: Illegal operands `viand \$vi0,\$vi0xyzw,\$vi31'
|
||||
.*: Error: Illegal operands `viand \$vi0,\$vi31,\$vi0xyzw'
|
||||
.*: Error: Illegal operands `viand \$vi1,\$vi2,\$vi3x'
|
||||
.*: Error: Illegal operands `viand \$vi31,\$vi0y,\$vi0'
|
||||
.*: Error: Illegal operands `viand \$vi31w,\$vi15,\$vi7'
|
||||
.*: Error: Illegal operands `viand \$vi31,\$vi31,\$vi31x'
|
||||
.*: Error: Illegal operands `vilwr\.w \$vi0,\(\$vi0x\)'
|
||||
.*: Error: Illegal operands `vilwr\.w \$vi0,\(\$vi31y\)'
|
||||
.*: Error: Illegal operands `vilwr\.w \$vi1,\(\$vi2z\)'
|
||||
.*: Error: Illegal operands `vilwr\.w \$vi31,\(\$vi0w\)'
|
||||
.*: Error: Illegal operands `vilwr\.w \$vi31,\(\$vi15xyzw\)'
|
||||
.*: Error: Illegal operands `vilwr\.w \$vi31x,\(\$vi31\)'
|
||||
.*: Error: Illegal operands `vilwr\.x \$vi0y,\(\$vi0\)'
|
||||
.*: Error: Illegal operands `vilwr\.x \$vi0z,\(\$vi31\)'
|
||||
.*: Error: Illegal operands `vilwr\.x \$vi1w,\(\$vi2\)'
|
||||
.*: Error: Illegal operands `vilwr\.x \$vi31xyzw,\(\$vi0\)'
|
||||
.*: Error: Illegal operands `vilwr\.x \$vi31xy,\(\$vi15\)'
|
||||
.*: Error: Illegal operands `vilwr\.x \$vi31zw,\(\$vi31\)'
|
||||
.*: Error: Illegal operands `vilwr\.y \$vi0wx,\(\$vi0\)'
|
||||
.*: Error: Illegal operands `vilwr\.y \$vi0xyzw,\(\$vi31\)'
|
||||
.*: Error: Illegal operands `vilwr\.y \$vi1y,\(\$vi2\)'
|
||||
.*: Error: Illegal operands `vilwr\.y \$vi31,\(\$vi0y\)'
|
||||
.*: Error: Illegal operands `vilwr\.z \$vi0z,\(\$vi0\)'
|
||||
.*: Error: Illegal operands `vilwr\.z \$vi0,\(\$vi31z\)'
|
||||
.*: Error: Illegal operands `vior \$vi0x,\$vi0,\$vi0'
|
||||
.*: Error: Illegal operands `vior \$vi0,\$vi0x,\$vi31'
|
||||
.*: Error: Illegal operands `vior \$vi0,\$vi31,\$vi0x'
|
||||
.*: Error: Illegal operands `vior \$vi1y,\$vi2,\$vi3'
|
||||
.*: Error: Illegal operands `vior \$vi31,\$vi0y,\$vi0'
|
||||
.*: Error: Illegal operands `vior \$vi31,\$vi15,\$vi7y'
|
||||
.*: Error: Illegal operands `vior \$vi31xyzw,\$vi31,\$vi31'
|
||||
.*: Error: Illegal operands `visub \$vi0x,\$vi0,\$vi0'
|
||||
.*: Error: Illegal operands `visub \$vi0,\$vi0y,\$vi31'
|
||||
.*: Error: Illegal operands `visub \$vi0,\$vi31,\$vi0z'
|
||||
.*: Error: Illegal operands `visub \$vi1w,\$vi2,\$vi3'
|
||||
.*: Error: Illegal operands `visub \$vi31,\$vi0xy,\$vi0'
|
||||
.*: Error: Illegal operands `visub \$vi31,\$vi15,\$vi7zw'
|
||||
.*: Error: Illegal operands `visub \$vi31,\$vi31,\$vi31w'
|
||||
.*: Error: Illegal operands `viswr\.w \$vi0,\(\$vi0w\)'
|
||||
.*: Error: Illegal operands `viswr\.w \$vi0w,\(\$vi31\)'
|
||||
.*: Error: Illegal operands `viswr\.x \$vi0x,\(\$vi31\)'
|
||||
.*: Error: Illegal operands `viswr\.x \$vi1,\(\$vi2x\)'
|
||||
.*: Error: Illegal operands `viswr\.x \$vi31x,\(\$vi0x\)'
|
||||
.*: Error: Illegal operands `viswr\.y \$vi31y,\(\$vi15\)'
|
||||
.*: Error: Illegal operands `viswr\.y \$vi31,\(\$vi31y\)'
|
||||
.*: Error: Illegal operands `viswr\.z \$vi0,\(\$vi0z\)'
|
||||
.*: Error: Illegal operands `viswr\.z \$vi0z,\(\$vi31\)'
|
||||
.*: Error: Illegal operands `viswr\.z \$vi1z,\(\$vi2z\)'
|
||||
.*: Error: Illegal operands `vitof0\.w \$vf1w,\$vf2x'
|
||||
.*: Error: Illegal operands `vitof0\.w \$vf31z,\$vf0w'
|
||||
.*: Error: Illegal operands `vitof0\.xw \$vf0xw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vitof0\.xw \$vf0xw,\$vf31w'
|
||||
.*: Error: Illegal operands `vitof12\.xw \$vf31xw,\$vf0x'
|
||||
.*: Error: Illegal operands `vitof12\.xzw \$vf0xzw,\$vf31xz'
|
||||
.*: Error: Illegal operands `vitof12\.xzw \$vf1xzw,\$vf2xw'
|
||||
.*: Error: Illegal operands `vitof12\.xzw \$vf31xzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vitof12\.xzw \$vf31xyzw,\$vf15xzw'
|
||||
.*: Error: Illegal operands `vitof12\.xzw \$vf31xw,\$vf31xzw'
|
||||
.*: Error: Illegal operands `vitof12\.y \$vf0y,\$vf0w'
|
||||
.*: Error: Illegal operands `vitof12\.y \$vf0x,\$vf31y'
|
||||
.*: Error: Illegal operands `vitof15\.xyw \$vf0xyw,\$vf31xw'
|
||||
.*: Error: Illegal operands `vitof15\.xyw \$vf1xyw,\$vf2yxw'
|
||||
.*: Error: Illegal operands `vitof15\.xyw \$vf31xwy,\$vf15xyw'
|
||||
.*: Error: Illegal operands `vitof15\.xyzw \$vf1\.xyzw,\$vf2xyzw'
|
||||
.*: Error: Illegal operands `vitof15\.xyzw \$vf31xyzw,\$vf0\.xyzw'
|
||||
.*: Error: Illegal operands `vitof4\.xw \$vf31xw,\$31xw'
|
||||
.*: Error: Illegal operands `vitof4\.xy \$0xy,\$vf0xy'
|
||||
.*: Error: Illegal operands `vitof4\.xyzw \$vf0yzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vitof4\.yzw \$vf1yzw,\$vf2yw'
|
||||
.*: Error: Illegal operands `vlqd\.w \$vf0,\(\-\-\$vi0w\)'
|
||||
.*: Error: Illegal operands `vlqd\.w \$vf0,\(\-\-\$vi31w\)'
|
||||
.*: Error: Illegal operands `vlqd\.w \$vf0x,\(\-\-\$vi0\)'
|
||||
.*: Error: Illegal operands `vlqd\.x \$vf0w,\(\-\-\$vi0x\)'
|
||||
.*: Error: Illegal operands `vlqd\.x \$vf0x,\(\-\-\$vi31x\)'
|
||||
.*: Error: Illegal operands `vlqd\.x \$vf0w,\(\-\-\$vi0\)'
|
||||
.*: Error: Illegal operands `vlqd\.xw \$vf0,\(\-\-\$vi0xw\)'
|
||||
.*: Error: Illegal operands `vlqd\.xy \$vf0,\(\-\-\$vi0xy\)'
|
||||
.*: Error: Illegal operands `vlqd\.xyw \$vf0,\(\-\-\$vi0xyw\)'
|
||||
.*: Error: Illegal operands `vlqd\.xyz \$vf0,\(\-\-\$vi0xyz\)'
|
||||
.*: Error: Illegal operands `vlqd\.xyzw \$vf0,\(\-\-\$vi0xyzw\)'
|
||||
.*: Error: Illegal operands `vlqd\.xz \$vf0,\(\-\-\$vi0xz\)'
|
||||
.*: Error: Illegal operands `vlqd\.xzw \$vf0,\(\-\-\$vi0xzw\)'
|
||||
.*: Error: Illegal operands `vlqd\.y \$vf0,\(\-\-\$vi0y\)'
|
||||
.*: Error: Illegal operands `vlqd\.yw \$vf0,\(\-\-\$vi0yw\)'
|
||||
.*: Error: Illegal operands `vlqd\.yz \$vf0,\(\-\-\$vi0yz\)'
|
||||
.*: Error: Illegal operands `vlqd\.yzw \$vf0,\(\-\-\$vi0yzw\)'
|
||||
.*: Error: Illegal operands `vlqd\.z \$vf0,\(\-\-\$vi0z\)'
|
||||
.*: Error: Illegal operands `vlqd\.zw \$vf0,\(\-\-\$vi0zw\)'
|
||||
.*: Error: Illegal operands `vlqi\.w \$vf0,\(\$vi0w\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.x \$vf31,\(\$vi15x\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xw \$vf0x,\(\$vi0\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xw \$vf0,\(\$vi31xw\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xy \$vf0,\(\$vi0xy\+\+\)'
|
||||
.*: Error: bad expression
|
||||
.*: Error: missing '\)'
|
||||
.*: Error: Illegal operands `vlqi\.xy \$vf1,\(\$2xy\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xyw \$vf0,\(\$vi0xyw\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xyz \$vf0,\(\$vi0xyz\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xyzw \$vf0,\(\$vi0xyzw\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xz \$vf0,\(\$vi0xz\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.xzw \$vf0,\(\$vi0xzw\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.y \$vf0,\(\$vi0y\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.yw \$vf0,\(\$vi0yw\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.yz \$vf0yz,\(\$vi0yz\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.yzw \$vf0,\(\$vi0yzw\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.z \$vf0,\(\$vi0z\+\+\)'
|
||||
.*: Error: Illegal operands `vlqi\.zw \$vf0,\(\$vi0zw\+\+\)'
|
||||
.*: Error: Illegal operands `vmaddai\.w \$ACCw,\$vf0w,\$R'
|
||||
.*: Error: Illegal operands `vmaddai\.w \$ACCw,\$vf1w,\$Iw'
|
||||
.*: Error: Illegal operands `vmaddai\.w \$ACCw,\$vf31w,\$Q'
|
||||
.*: Error: Illegal operands `vmaddai\.x \$ACCx,\$vf0x,\$ACC'
|
||||
.*: Error: Illegal operands `vmaddai\.x \$ACCy,\$vf1w,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.x \$ACCxy,\$vf31x,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.xw \$ACCxw,\$vf0xyw,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.xy \$ACCxy,\$vf0xyw,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.xy \$ACCxy,\$vf1xyz,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.xy \$ACCxyz,\$vf31xy,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.xyw \$ACCxy,\$vf0xyw,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.yw \$ACCyw,\$vf1w,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.yw \$ACCyw,\$vf31y,\$I'
|
||||
.*: Error: Illegal operands `vmaddai\.yz \$ACCyz,\$vf0yz,\$R'
|
||||
.*: Error: Illegal operands `vmaddaq\.xyz \$ACCxyz,\$vf0xyz,\$R'
|
||||
.*: Error: Illegal operands `vmaddaq\.xyz \$ACCxyz,\$vf1xyz,\$Qxyz'
|
||||
.*: Error: Illegal operands `vmaddaq\.xzw \$ACCxzw,\$vf31xzw,\$Qxzw'
|
||||
.*: Error: Illegal operands `vmaddaq\.y \$ACCy,\$vf0y,\$R'
|
||||
.*: Error: Illegal operands `vmaddaq\.y \$ACCy,\$vf1y,\$ACCy'
|
||||
.*: Error: Illegal operands `vmaddaq\.y \$ACCy,\$vf31y,\$ACC'
|
||||
.*: Error: Illegal operands `vmaddaw\.z \$ACCz,\$vf31z,\$vf0x'
|
||||
.*: Error: Illegal operands `vmaddaw\.zw \$ACCzw,\$vf31zw,\$vf15y'
|
||||
.*: Error: Illegal operands `vmaddax\.w \$ACCw,\$vf1w,\$vf2w'
|
||||
.*: Error: Illegal operands `vmadda\.xw \$ACCxw,\$vf31xw,\$vf31wx'
|
||||
.*: Error: Illegal operands `vmaddax\.xyz \$ACCxyz,\$vf0xyz,\$vf0xyz'
|
||||
.*: Error: Illegal operands `vmaddax\.xyzw \$ACCxyzw,\$vf0xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vmaddax\.xz \$ACCxz,\$vf0xz,\$vf31xz'
|
||||
.*: Error: Illegal operands `vmaddax\.xzw \$ACCxzw,\$vf0xzw,\$vf0xzw'
|
||||
.*: Error: Illegal operands `vmaddax\.z \$ACCz,\$vf31z,\$vf15z'
|
||||
.*: Error: Illegal operands `vmaddax\.zw \$ACCzw,\$vf1zw,\$vf2zw'
|
||||
.*: Error: Illegal operands `vmadday\.w \$ACCw,\$vf1w,\$vf2w'
|
||||
.*: Error: Illegal operands `vmadday\.w \$ACCw,\$vf31y,\$vf0y'
|
||||
.*: Error: Illegal operands `vmadday\.w \$ACCy,\$vf31w,\$vf15y'
|
||||
.*: Error: Illegal operands `vmadday\.w \$ACCy,\$vf31y,\$vf31y'
|
||||
.*: Error: Illegal operands `vmadday\.xyzw \$ACCxyzw,\$vf0xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vmadday\.xyzw \$ACCxyzw,\$vf0y,\$vf31y'
|
||||
.*: Error: Illegal operands `vmadday\.xyzw \$ACCy,\$vf1xyzw,\$vf2y'
|
||||
.*: Error: Illegal operands `vmadday\.xyzw \$ACCy,\$vf31y,\$vf0y'
|
||||
.*: Error: Illegal operands `vmaddi\.x \$vf0x,\$vf31x,\$Ix'
|
||||
.*: Error: Illegal operands `vmaddi\.xw \$vf1xw,\$vf2xw,\$Ixw'
|
||||
.*: Error: Illegal operands `vmaddi\.xy \$vf31xy,\$vf0xy,\$Ixy'
|
||||
.*: Error: Illegal operands `vmaddi\.xyw \$vf0xyw,\$vf0xyw,\$Ixyw'
|
||||
.*: Error: Illegal operands `vmaddi\.xyzw \$vf1xyzw,\$vf2xyzw,\$Ixyzw'
|
||||
.*: Error: Illegal operands `vmaddi\.y \$vf0y,\$vf0y,\$Iy'
|
||||
.*: Error: Illegal operands `vmaddi\.yw \$vf0yw,\$vf0yw,\$Iyw'
|
||||
.*: Error: Illegal operands `vmaddi\.zw \$vf0zw,\$vf31zw,\$0'
|
||||
.*: Error: Illegal operands `vmaddq\.w \$vf0w,\$vf0w,\$0'
|
||||
.*: Error: Illegal operands `vmadd\.w \$vf0w,\$vf0w,\$vf0y'
|
||||
.*: Error: Illegal operands `vmaddw\.xyz \$vf31xyz,\$vf15xyz'
|
||||
.*: Error: Illegal operands `vmaddw\.xyzw \$vf0xyzw,\$vf31xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vmaddx\.yw \$vf1yw,\$vf2yw,\$vf3yw'
|
||||
.*: Error: Illegal operands `vmaddy\.xy \$vf31xy,\$vf15xy,\$vf7xy'
|
||||
.*: Error: Illegal operands `vmadd\.z \$vf1z,\$vf2z,\$vf3x'
|
||||
.*: Error: Illegal operands `vmadd\.z \$vf31z,\$vf0z,\$vf0w'
|
||||
.*: Error: Illegal operands `vmaddz\.xyw \$vf0xyw,\$vf0xyw,\$vf31x'
|
||||
.*: Error: Illegal operands `vmaddz\.xz \$vf0xz,\$vf31xz,\$vf0xz'
|
||||
.*: Error: Illegal operands `vmaddz\.y \$vf31y,\$vf0y,\$vf0y'
|
||||
.*: Error: Illegal operands `vmaxi\.w \$vf31w,\$vf15w,\$Q'
|
||||
.*: Error: Illegal operands `vmaxi\.w \$vf31w,\$vf31w,\$0'
|
||||
.*: Error: Illegal operands `vmax\.w \$vf31w,\$vf31w,\$vf31x'
|
||||
.*: Error: Illegal operands `vmaxw\.w \$vf0w,\$vf0w,\$vf0x'
|
||||
.*: Error: Illegal operands `vmaxw\.x \$vf0x,\$vf0x,\$vf0x'
|
||||
.*: Error: Illegal operands `vmaxw\.x \$vf0w,\$vf0w,\$vf31w'
|
||||
.*: Error: Illegal operands `vmaxw\.xw \$vf0xw,\$vf0xw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vmaxw\.xw \$vf0w,\$vf0w,\$vf31w'
|
||||
.*: Error: Illegal operands `vmaxw\.xy \$vf0xy,\$vf31xy,\$vf0xy'
|
||||
.*: Error: Illegal operands `vmaxw\.xy \$vf1xy,\$vf2w,\$vf3w'
|
||||
.*: Error: Illegal operands `vmaxw\.xy \$vf31w,\$vf0xy,\$vf0w'
|
||||
.*: Error: Illegal operands `vmax\.x \$vf0x,\$vf0x,\$vf31w'
|
||||
.*: Error: Illegal operands `vmaxx\.w \$vf0w,\$vf0w,\$vf31w'
|
||||
.*: Error: Illegal operands `vmaxx\.w \$vf0x,\$vf31x,\$vf0x'
|
||||
.*: Error: Illegal operands `vmaxx\.w \$vf31w,\$vf0w,\$vf0w'
|
||||
.*: Error: Illegal operands `vmaxx\.w \$vf31x,\$vf15x,\$vf7x'
|
||||
.*: Error: Illegal operands `vmax\.xw \$vf31xw,\$vf15xw,\$vf7w'
|
||||
.*: Error: Illegal operands `vmaxx\.x \$vf0x,\$vf0x,\$vf0w'
|
||||
.*: Error: Illegal operands `vmaxx\.x \$vf31w,\$vf15x,\$vf7x'
|
||||
.*: Error: Illegal operands `vmaxx\.x \$vf31x,\$vf31w,\$vf31x'
|
||||
.*: Error: Illegal operands `vmaxx\.xw \$vf31xw,\$vf15xw,\$vf7xw'
|
||||
.*: Error: Illegal operands `vmaxx\.xy \$vf0xy,\$vf31xy,\$vf0xy'
|
||||
.*: Error: Illegal operands `vmaxx\.xyw \$vf0xyw,\$vf0xyw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vmaxx\.xyz \$vf0xyz,\$vf0xyz,\$vf0xyz'
|
||||
.*: Error: Illegal operands `vmaxx\.xyzw \$vf0xyzw,\$vf0xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vmaxx\.xyzw \$vf0xyzw,\$vf0x,\$vf31x'
|
||||
.*: Error: Illegal operands `vmaxx\.xyzw \$vf0x,\$vf31xyzw,\$vf0x'
|
||||
.*: Error: Illegal operands `vmaxx\.xyzw \$vf1x,\$vf2x,\$vf3x'
|
||||
.*: Error: Illegal operands `vmaxx\.xzw \$vf31xzw,\$vf15xzw,\$vf7xzw'
|
||||
.*: Error: Illegal operands `vmaxx\.y \$vf0y,\$vf0y,\$vf0y'
|
||||
.*: Error: Illegal operands `vmaxx\.y \$vf0y,\$vf0x,\$vf31x'
|
||||
.*: Error: Illegal operands `vmaxx\.y \$vf0x,\$vf31y,\$vf0x'
|
||||
.*: Error: Illegal operands `vmaxx\.yw \$vf1yw,\$vf2yw,\$vf3yw'
|
||||
.*: Error: Illegal operands `vmaxx\.yz \$vf0yz,\$vf0yz,\$vf0yz'
|
||||
.*: Error: Illegal operands `vmaxx\.yz \$vf0x,\$vf0x,\$vf31x'
|
||||
.*: Error: Illegal operands `vmaxx\.z \$vf31z,\$vf0z,\$vf0z'
|
||||
.*: Error: Illegal operands `vmaxx\.z \$vf31z,\$vf15x,\$vf7x'
|
||||
.*: Error: Illegal operands `vmaxx\.z \$vf31x,\$vf31z,\$vf31x'
|
||||
.*: Error: Illegal operands `vmaxx\.zw \$vf1zw,\$vf2zw,\$vf3zw'
|
||||
.*: Error: Illegal operands `vmax\.y \$vf0y,\$vf0y,\$vf31x'
|
||||
.*: Error: Illegal operands `vmax\.yw \$vf0yw,\$vf0yw,\$vf31w'
|
||||
.*: Error: Illegal operands `vmax\.yw \$vf0yw,\$vf31yw,\$vf0y'
|
||||
.*: Error: Illegal operands `vmaxy\.xz \$vf31xz,\$vf15xz,\$vf7xz'
|
||||
.*: Error: Illegal operands `vmaxy\.xzw \$vf1xzw,\$vf2xzw,\$vf3xzw'
|
||||
.*: Error: Illegal operands `vmaxy\.y \$vf1y,\$vf2y'
|
||||
.*: Error: Illegal operands `vmaxy\.yz \$vf0yz,\$vf31yz,\$vf0yz'
|
||||
.*: Error: Illegal operands `vmaxy\.yzw \$vf0yzw,\$vf0yzw,\$vf0yzw'
|
||||
.*: Error: Illegal operands `vmaxy\.yzw \$vf31y,\$vf15y,\$vf7y'
|
||||
.*: Error: Illegal operands `vmaxy\.yzw \$vf31yzw,\$vf31yw,\$vf31y'
|
||||
.*: Error: Illegal operands `vmaxy\.z \$vf0z,\$vf0z,\$vf0z'
|
||||
.*: Error: Illegal operands `vmaxy\.z \$vf0z,\$vf0y,\$vf31y'
|
||||
.*: Error: Illegal operands `vmaxy\.z \$vf0y,\$vf31z,\$vf0y'
|
||||
.*: Error: Illegal operands `vmaxz\.xw \$vf31xw,\$vf31xw,\$vf31xw'
|
||||
.*: Error: Illegal operands `vmaxz\.xy \$vf0xy,\$vf0xy,\$vf0xy'
|
||||
.*: Error: Illegal operands `vmaxz\.xyw \$vf0xyw,\$vf0xyw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vmaxz\.xyz \$vf1xyz,\$vf2xyz,\$vf3xyz'
|
||||
.*: Error: Illegal operands `vmaxz\.xyz \$vf31xyz,\$vf0z,\$vf0z'
|
||||
.*: Error: Illegal operands `vmaxz\.xyz \$vf31z,\$vf15xyz,\$vf7z'
|
||||
.*: Error: Illegal operands `vmaxz\.xyz \$vf31z,\$vf31z,\$vf31z'
|
||||
.*: Error: Illegal operands `vmaxz\.xyzw \$vf0xyzw,\$vf0xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vmaxz\.xyzw \$vf0xyzw,\$vf0z,\$vf31z'
|
||||
.*: Error: Illegal operands `vmaxz\.xyzw \$vf0z,\$vf31z,\$vf0z'
|
||||
.*: Error: Illegal operands `vmaxz\.xyzw \$vf1xyzw,\$vf2xyzw,\$vfz'
|
||||
.*: Error: Illegal operands `vmaxz\.xyzw \$vf31xyzw,\$vf0xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vmaxz\.xz \$vf0xz,\$vf0xz,\$vf0xz'
|
||||
.*: Error: Illegal operands `vmaxz\.y \$vf31y,\$vf15z,\$vf7z'
|
||||
.*: Error: Illegal operands `vmaxz\.y \$vf31y,\$vf31y,\$vf31y'
|
||||
.*: Error: Illegal operands `vmaxz\.yw \$vf0yw,\$vf0yw,\$vf0yw'
|
||||
.*: Error: Illegal operands `vmaxz\.yzw \$vf0yzw,\$vf0yzw,\$vf31yzw'
|
||||
.*: Error: Illegal operands `vmaxz\.yzw \$vf0yzw,\$vf31z,\$vf0z'
|
||||
.*: Error: Illegal operands `vmaxz\.yzw \$vf1z,\$vf2yzw,\$vf3z'
|
||||
.*: Error: Illegal operands `vmaxz\.yzw \$vf31z,\$vf0z,\$vf0z'
|
||||
.*: Error: Illegal operands `vmaxz\.z \$vf31z,\$vf31z,\$vf31x'
|
||||
.*: Error: Illegal operands `vmfir\.w \$vf0w,\$vi0w'
|
||||
.*: Error: Illegal operands `vmfir\.w \$vf0,\$vi31w'
|
||||
.*: Error: Illegal operands `vmfir\.x \$vf0x,\$vi0x'
|
||||
.*: Error: Illegal operands `vmfir\.x \$vf0,\$vi31x'
|
||||
.*: Error: Illegal operands `vmfir\.xw \$vf0xw,\$vi31xw'
|
||||
.*: Error: Illegal operands `vmfir\.xy \$vf1xy,\$vi2xy'
|
||||
.*: Error: Illegal operands `vmfir\.xy \$vf31,\$vi0xy'
|
||||
.*: Error: Illegal operands `vmfir\.xyw \$vf0xyw,\$vi31xyw'
|
||||
.*: Error: Illegal operands `vmfir\.xyw \$vf31xyw,\$vi0x'
|
||||
.*: Error: Illegal operands `vmfir\.xyz \$vf0xyz,\$vi0xyz'
|
||||
.*: Error: Illegal operands `vmfir\.xyzw \$vf1xyzw,\$vi2xyzw'
|
||||
.*: Error: Illegal operands `vmfir\.xz \$vf0xz,\$vi31xz'
|
||||
.*: Error: Illegal operands `vmfir\.xzw \$vf0xzw,\$vi31xzw'
|
||||
.*: Error: Illegal operands `vmfir\.y \$vf0y,\$vi0y'
|
||||
.*: Error: Illegal operands `vmfir\.yw \$vf0yw,\$vi0yw'
|
||||
.*: Error: Illegal operands `vmfir\.yz \$vf0yz,\$vi31yz'
|
||||
.*: Error: Illegal operands `vmfir\.yzw \$vf0yzw,\$vi0yzw'
|
||||
.*: Error: Illegal operands `vmfir\.z \$vf0z,\$vi0z'
|
||||
.*: Error: Illegal operands `vmfir\.z \$0z,\$vi31'
|
||||
.*: Error: Illegal operands `vmfir\.zw \$vf0zw,\$vi0zw'
|
||||
.*: Error: Illegal operands `vminii\.w \$vf0w,\$vf0w,\$Iw'
|
||||
.*: Error: Illegal operands `vminii\.w \$vf0w,\$vf31x,\$I'
|
||||
.*: Error: Illegal operands `vminii\.w \$vf1x,\$vf2w,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xw \$vf0xw,\$vf31xw,\$Ixw'
|
||||
.*: Error: Illegal operands `vminii\.xw \$vf1xw,\$vf2w,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xw \$vf31x,\$vf0xw,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xyw \$vf31xw,\$vf0xyw,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xyz \$vf0xy,\$vf0xyz,\$I'
|
||||
.*: Error: Unrecognized opcode `minii\.xz \$vf31z,\$vf15xz,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xz \$vf31xz,\$vf31x,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xzw \$vf0xzw,\$vf0xw,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xzw \$vf0zw,\$vf31xzw,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xzw \$vf1xyzw,\$vf2xzw,\$I'
|
||||
.*: Error: Illegal operands `vminii\.xzw \$vf31xzw,\$vf0xyzw,\$I'
|
||||
.*: Error: Illegal operands `vminii\.yw \$vf31yw,\$vf31yw,\$R'
|
||||
.*: Error: Illegal operands `vminii\.yz \$vf0yz,\$vf0yz,\$Q'
|
||||
.*: Error: Illegal operands `vminii\.yz \$vf0yz,\$vf31yz,\$ACC'
|
||||
.*: Error: Illegal operands `vminii\.yzw \$vf31yzw,\$vf0yzw,\$R'
|
||||
.*: Error: Illegal operands `vminii\.yzw \$vf31yzw,\$vf15yzw,\$ACC'
|
||||
.*: Error: Illegal operands `vminii\.yzw \$vf31yzw,\$vf31yzw,\$Q'
|
||||
.*: Error: Illegal operands `vmini\.w \$vf0w,\$vf0w,\$vf0x'
|
||||
.*: Error: Illegal operands `vminiw\.w \$vf31w,\$vf31w,\$vf31x'
|
||||
.*: Error: Illegal operands `vminiw\.x \$vf0x,\$vf0x,\$vf0x'
|
||||
.*: Error: Illegal operands `vminiw\.x \$vf0x,\$vf0w,\$vf31w'
|
||||
.*: Error: Illegal operands `vminiw\.x \$vf0w,\$vf31x,\$vf0w'
|
||||
.*: Error: Illegal operands `vminiw\.x \$vf1w,\$vf2w,\$vf3w'
|
||||
.*: Error: Illegal operands `vminiw\.xw \$vf0xw,\$vf31xw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vminiw\.xw \$vf1w,\$vf2w,\$vf3w'
|
||||
.*: Error: Illegal operands `vminiw\.xyzw \$vf0xyzw,\$vf0xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vminiw\.xyzw \$vf0xyzw,\$vf0xxyzw,\$vf31w'
|
||||
.*: Error: Illegal operands `vminiw\.xyzw \$vf0xyzw,\$vf31xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vminiw\.xyzw \$vf1xyzw,\$vf2xyzw,\$vf3ww'
|
||||
.*: Error: Illegal operands `vminiw\.xz \$vf31xz,\$vf0xz,\$vf0xz'
|
||||
.*: Error: Illegal operands `vminiw\.yw \$vf0yw,\$vf0yw,\$vf0yw'
|
||||
.*: Error: Illegal operands `vminiw\.yz \$vf31yz,\$vf0yz,\$vf0yz'
|
||||
.*: Error: Illegal operands `vminiw\.z \$vf31z,\$vf0z,\$vf0z'
|
||||
.*: Error: Illegal operands `vminiw\.z \$vf31z,\$vf15w,\$vf7w'
|
||||
.*: Error: Illegal operands `vminiw\.z \$vf31w,\$vf31z,\$vf31w'
|
||||
.*: Error: Illegal operands `vminix\.xw \$vf0xw,\$vf31xw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vminix\.xyw \$vf0xyw,\$vf0xyw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vminix\.xyzw \$vf0xyzw,\$vf31xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vminix\.yw \$vf31yw,\$vf31yw,\$vf31yw'
|
||||
.*: Error: Illegal operands `vminix\.zw \$vf31zw,\$vf31zw,\$vf31zw'
|
||||
.*: Error: Illegal operands `vmini\.y \$vf0y,\$vf0x,\$vf0y'
|
||||
.*: Error: Illegal operands `vminiy\.w \$vf0w,\$vf31w,\$vf0w'
|
||||
.*: Error: Illegal operands `vminiy\.x \$vf31x,\$vf15x,\$vf7x'
|
||||
.*: Error: Illegal operands `vminiy\.x \$vf31x,\$vf31y,\$vf31y'
|
||||
.*: Error: Illegal operands `vminiy\.xw \$vf0y,\$vf0xw,\$vf0y'
|
||||
.*: Error: Illegal operands `vminiy\.xw \$vf0xw,\$vf0y,\$vf31y'
|
||||
.*: Error: Illegal operands `vminiy\.xw \$vf0xw,\$vf31xw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vminiy\.xyz \$vf31xyz,\$vf31xyz,\$vf31xyz'
|
||||
.*: Error: Illegal operands `vminiy\.xyzw \$vf0xyzw,\$vf0y,\$vf0y'
|
||||
.*: Error: Illegal operands `vminiy\.xyzw \$vf0y,\$vf0xyzw,\$vf31y'
|
||||
.*: Error: Illegal operands `vminiy\.xyzw \$vf0xyzw,\$vf31xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vminiy\.yw \$vf1yw,\$vf2yw,\$vf3yw'
|
||||
.*: Error: Illegal operands `vminiy\.zw \$vf1zw,\$vf2zw,\$vf3zw'
|
||||
.*: Error: Illegal operands `vmini\.z \$vf0z,\$vf0z,\$vf0x'
|
||||
.*: Error: Illegal operands `vminiz\.x \$vf0x,\$vf31x,\$vf0x'
|
||||
.*: Error: Illegal operands `vminiz\.xw \$vf0xw,\$vf31xw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vminiz\.xyw \$vf31xyw,\$vf0xyw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vminiz\.xyw \$vf31xyw,\$vf15z,\$vf7z'
|
||||
.*: Error: Illegal operands `vmove\.xyw \$vf0xyw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vmove\.y \$vf0y,\$vf31x'
|
||||
.*: Error: Illegal operands `vmr32\.xw \$vf0xw,\$vf0w'
|
||||
.*: Error: Illegal operands `vmr32\.xw \$vf0w,\$vf31xw'
|
||||
.*: Error: Illegal operands `vmsubai\.xy \$ACCxy,\$vf31xy,\$Q'
|
||||
.*: Error: Illegal operands `vmsubai\.xyw \$ACCxyw,\$vf0xyw,\$0'
|
||||
.*: Error: Illegal operands `vmsubai\.xyw \$ACCxyw,\$vf1xyw,\$ACC'
|
||||
.*: Error: Illegal operands `vmsubai\.xyw \$ACCxyw,\$vf31xw,\$I'
|
||||
.*: Error: Illegal operands `vmsubaq\.y \$ACCy,\$vf31y,\$Qy'
|
||||
.*: Error: Illegal operands `vmsubaq\.yw \$ACCw,\$vf0yw,\$Q'
|
||||
.*: Error: Illegal operands `vmsubaq\.yw \$ACCwy,\$vf1yw,\$Q'
|
||||
.*: Error: Illegal operands `vmsubaw\.x \$ACCx,\$vf31x,\$vf0x'
|
||||
.*: Error: Illegal operands `vmsubaw\.x \$ACCx,\$vf31w,\$vf15w'
|
||||
.*: Error: Illegal operands `vmsubaw\.x \$ACCw,\$vf31x,\$vf31w'
|
||||
.*: Error: Illegal operands `vmsubaw\.xw \$ACCw,\$vf0xw,\$vf0w'
|
||||
.*: Error: Illegal operands `vmsubaw\.xw \$ACCxw,\$vf0w,\$vf31w'
|
||||
.*: Error: Illegal operands `vmsubaw\.xw \$ACCxw,\$vf1xw,\$vf2xw'
|
||||
.*: Error: Illegal operands `vmsubax\.yzw \$ACCyzw,\$vf0yzw,\$vf31yzw'
|
||||
.*: Error: Illegal operands `vmsubax\.z \$ACCz,\$vf31z,\$vf0z'
|
||||
.*: Error: Illegal operands `vmsuba\.y \$ACCy,\$vf31y,\$vf15a'
|
||||
.*: Error: Illegal operands `vmsuba\.yw \$ACCyw,\$vf31yw,\$vf0w'
|
||||
.*: Error: Illegal operands `vmsubay\.x \$ACCx,\$vf31x,\$vf15x'
|
||||
.*: Error: Illegal operands `vmsubay\.x \$ACCx,\$vf31y,\$vf31y'
|
||||
.*: Error: Illegal operands `vmsubay\.xw \$ACCxw,\$vf0xw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vmsubaz\.xy \$ACCxy,\$vf0xy,\$vf31xy'
|
||||
.*: Error: Illegal operands `vmsubaz\.yw \$ACCyw,\$vf31yw,\$vf0yw'
|
||||
.*: Error: Illegal operands `vmsubi\.xyzw \$vf31xyzw,\$vf0xyzw,\$R'
|
||||
.*: Error: Illegal operands `vmsubw\.xyw \$vf0xyw,\$vf0xyw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vmsubw\.xzw \$vf0xzw,\$vf0xzw,\$vf31xzw'
|
||||
.*: Error: Illegal operands `vmsubw\.y \$vf31y,\$vf31y,\$vf31y'
|
||||
.*: Error: Illegal operands `vmsubw\.yw \$vf0yw,\$vf0y,\$vf0w'
|
||||
.*: Error: Illegal operands `vmsubw\.yw \$vf0w,\$vf0yw,\$vf31w'
|
||||
.*: Error: Illegal operands `vmsubw\.zw \$vf0zw,\$vf0zw,\$vf31zw'
|
||||
.*: Error: Illegal operands `vmsubx\.w \$vf0w,\$vf0w,\$vf0w'
|
||||
.*: Error: Illegal operands `vmsub\.y \$vf31y,\$vf15y,\$vf7w'
|
||||
.*: Error: Illegal operands `vmsuby\.x \$vf0x,\$vf0x,\$vf31x'
|
||||
.*: Error: Illegal operands `vmsuby\.x \$vf0x,\$vf31y,\$vf0y'
|
||||
.*: Error: Illegal operands `vmsubz\.x \$vf0x,\$vf31x,\$vf0x'
|
||||
.*: Error: Illegal operands `vmulai\.xyz \$ACCxyz,\$vf1xz,\$I'
|
||||
.*: Error: Illegal operands `vmulaq\.zw \$ACCzw,\$vf31zw,\$I'
|
||||
.*: Error: Illegal operands `vmula\.w \$ACCw,\$vf31w,\$vf0x'
|
||||
.*: Error: Illegal operands `vmulax\.xz \$ACCxz,\$vf0xz,\$vf31xz'
|
||||
.*: Error: Illegal operands `vmulax\.xz \$ACCxz,\$vf1x,\$vf2x'
|
||||
.*: Error: Illegal operands `vmulax\.xz \$ACCx,\$vf31xz,\$vf0x'
|
||||
.*: Error: Illegal operands `vmulay\.yzw \$ACCyzw,\$vf0yzw,\$vf31yzw'
|
||||
.*: Error: Illegal operands `vmulaz\.w \$ACCw,\$vf0w,\$vf31w'
|
||||
.*: Error: Unrecognized opcode `mulaz\.xy \$ACCz,\$vf31xy,\$vf0z'
|
||||
.*: Error: Illegal operands `vmulaz\.xy \$ACCxy,\$vf31z,\$vf15z'
|
||||
.*: Error: Illegal operands `vmulaz\.z \$ACCz,\$vf1z,\$vf2x'
|
||||
.*: Error: Illegal operands `vmuli\.x \$vf31x,\$vf15x,\$ACC'
|
||||
.*: Error: Illegal operands `vmulq\.x \$vf0x,\$vf31x,\$0'
|
||||
.*: Error: Illegal operands `vmulq\.x \$vf1x,\$vf2x,\$ACC'
|
||||
.*: Error: Illegal operands `vmulq\.x \$vf31x,\$vf0x,\$R'
|
||||
.*: Error: Illegal operands `vmulq\.x \$vf31x,\$vf15x,\$I'
|
||||
.*: Error: Illegal operands `vmulw\.z \$vf31z,\$vf15z,\$vf7z'
|
||||
.*: Error: Illegal operands `vmulw\.z \$vf31z,\$vf31w,\$vf31w'
|
||||
.*: Error: Illegal operands `vmulw\.zw \$vf0zw,\$vf0zw,\$vf0zw'
|
||||
.*: Error: Illegal operands `vmuly\.xyzw \$vf0xyzw,\$vf0y,\$vf31y'
|
||||
.*: Error: Illegal operands `vmuly\.xyzw \$vf0xyzw,\$vf31xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vmuly\.xyzw \$vf1xyzw,\$vf2y,\$vf3y'
|
||||
.*: Error: Illegal operands `vmuly\.xyzw \$vf31y,\$vf0xyzw,\$vf0y'
|
||||
.*: Error: Illegal operands `vmulz\.y \$vf0y,\$vf31y,\$vf0y'
|
||||
.*: Error: Illegal operands `vmulz\.y \$vf1y,\$vf2z,\$vf3z'
|
||||
.*: Error: Illegal operands `vmulz\.y \$vf31z,\$vf0y,\$vf0z'
|
||||
.*: Error: Illegal operands `vmulz\.y \$vf31z,\$vf15z,\$vf7z'
|
||||
.*: Error: Illegal operands `vopmsub \$vf0x,\$vf0,\$vf31'
|
||||
.*: Error: Illegal operands `vopmsub \$vf0,\$vf31x,\$vf0'
|
||||
.*: Error: Illegal operands `vopmsub \$vf1,\$vf2,\$vf3x'
|
||||
.*: Error: Illegal operands `vopmsub \$ACC,\$vf0,\$vf0'
|
||||
.*: Error: Illegal operands `vopmsub \$vf31,\$R,\$vf7'
|
||||
.*: Error: Illegal operands `vopmsub \$vf31,\$vf31,\$I'
|
||||
.*: Error: Illegal operands `vopmsub\.xyz \$vf0xyz,\$vf0xyz,\$vf0xy'
|
||||
.*: Error: Illegal operands `vopmula \$0,\$vf0,\$vf0'
|
||||
.*: Error: Illegal operands `vopmula \$Q,\$vf0,\$vf31'
|
||||
.*: Error: Illegal operands `vopmula \$R,\$vf1,\$vf2'
|
||||
.*: Error: Illegal operands `vopmula \$I,\$vf31,\$vf0'
|
||||
.*: Error: Illegal operands `vopmula \$ACCx,\$vf31,\$vf15'
|
||||
.*: Error: Illegal operands `vopmula \$ACCxyzw,\$vf31,\$vf31'
|
||||
.*: Error: Illegal operands `vopmula\.xyz \$ACCxyzw,\$vf0xyz,\$vf0xyz'
|
||||
.*: Error: Unrecognized opcode `vopmula\.xyzw \$ACCxyzw,\$vf0xyzw,\$vf31xyzw'
|
||||
.*: Error: Illegal operands `vrget\.w \$vf0w,\$0'
|
||||
.*: Error: Illegal operands `vrget\.w \$vf1w,\$I'
|
||||
.*: Error: Illegal operands `vrget\.w \$vf31w,\$Q'
|
||||
.*: Error: Illegal operands `vrget\.x \$vf0x,\$ACC'
|
||||
.*: Error: Illegal operands `vrget\.x \$vf1y,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xy \$vf31x,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyw \$vf0xw,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyw \$vf1yw,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyw \$vf31xy,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyz \$vf0xy,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyz \$vf1xyzw,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyz \$vf31xyzw,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyzw \$vf0xyz,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyzw \$vf1xzw,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xyzw \$vf31yzw,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xz \$vf0xz,\$0'
|
||||
.*: Error: Illegal operands `vrget\.xz \$vf1z,\$R'
|
||||
.*: Error: Illegal operands `vrget\.xzw \$vf0xw,\$R'
|
||||
.*: Error: Illegal operands `vrget\.y \$vf0z,\$R'
|
||||
.*: Error: Illegal operands `vrget\.y \$vf1y,\$I'
|
||||
.*: Error: Illegal operands `vrget\.z \$vf31z,\$Q'
|
||||
.*: Error: Illegal operands `vrget\.zw \$vf0zw,\$ACC'
|
||||
.*: Error: Illegal operands `vrnext\.xyzw \$vf0xyz,\$R'
|
||||
.*: Error: Illegal operands `vrnext\.xyzw \$vf1xyzw,\$0'
|
||||
.*: Error: Illegal operands `vrnext\.xyzw \$vf31xyzw,\$Rxyzw'
|
||||
.*: Error: Illegal operands `vrnext\.yz \$vf31yz,\$Ryz'
|
||||
.*: Error: Illegal operands `vrnext\.z \$vf0z,\$Rz'
|
||||
.*: Error: Illegal operands `vrsqrt \$Q,\$vf0xz,\$vf31y'
|
||||
.*: Error: Illegal operands `vrsqrt \$Q,\$vf1z,\$vf2xz'
|
||||
.*: Error: Illegal operands `vrsqrt \$Q,\$vf31yx,\$vf15w'
|
||||
.*: Error: Illegal operands `vrsqrt \$Qx,\$vf31x,\$vf31y'
|
||||
.*: Error: Illegal operands `vrsqrt \$0,\$vf31y,\$vf0w'
|
||||
.*: Error: Illegal operands `vrxor \$0,\$vf0w'
|
||||
.*: Error: Illegal operands `vrxor \$R,\$vf0xy'
|
||||
.*: Error: Illegal operands `vrxor \$R,\$vf0zw'
|
||||
.*: Error: Illegal operands `vrxor \$R,\$vf1yz'
|
||||
.*: Error: Illegal operands `vrxor \$ACC,\$vf31x'
|
||||
.*: Error: Illegal operands `vrxor \$Q,\$vf31y'
|
||||
.*: Error: Illegal operands `vsqd\.w \$vf0,\(\-\-\$vi0w\)'
|
||||
.*: Error: Illegal operands `vsqd\.w \$vf0,\(\-\-\$vi31w\)'
|
||||
.*: Error: Illegal operands `vsqd\.x \$vf1,\(\-\-\$vi2x\)'
|
||||
.*: Error: Illegal operands `vsqd\.xw \$vf0,\(\-\-\$vi0xw\)'
|
||||
.*: Error: Illegal operands `vsqd\.xy \$vf0,\(\-\-\$vi0xy\)'
|
||||
.*: Error: Illegal operands `vsqd\.xyw \$vf0,\(\-\-\$vi0xyw\)'
|
||||
.*: Error: Illegal operands `vsqd\.xyz \$vf0,\(\-\-\$vi31xyz\)'
|
||||
.*: Error: Illegal operands `vsqd\.xyzw \$vf0,\(\-\-\$vi0xyzw\)'
|
||||
.*: Error: Illegal operands `vsqd\.xz \$vf0,\(\-\-\$vi31xz\)'
|
||||
.*: Error: Illegal operands `vsqd\.xzw \$vf0,\(\-\-\$vi0xzw\)'
|
||||
.*: Error: Illegal operands `vsqd\.y \$vf0,\(\-\-\$vi0y\)'
|
||||
.*: Error: Illegal operands `vsqd\.yw \$vf0,\(\-\-\$vi31yw\)'
|
||||
.*: Error: Illegal operands `vsqd\.yz \$vf0,\(\-\-\$vi31yz\)'
|
||||
.*: Error: Illegal operands `vsqd\.yzw \$vf0,\(\-\-\$vi31yzw\)'
|
||||
.*: Error: Illegal operands `vsqd\.yzw \$vf0yzw,\(\-\-\$vi0x\)'
|
||||
.*: Error: Illegal operands `vsqd\.z \$vf1,\(\-\-\$vi2z\)'
|
||||
.*: Error: Illegal operands `vsqd\.zw \$vf1,\(\-\-\$vi2zw\)'
|
||||
.*: Error: Illegal operands `vsqi\.w \$vf0,\(\$vi0w\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.x \$vf0x,\(\$vi0x\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xw \$vf0xw,\(\$vi0xw\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xw \$vf1x,\(\$vi2\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xw \$vf31w,\(\$vi0\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xy \$vf0,\(\$vi31xy\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xyw \$vf0x,\(\$vi0\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xyw \$vf0,\(\$vi31xyw\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xyz \$vf0xyz,\(\$vi0xyz\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xyzw \$vf0,\(\$vi31xyzw\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xz \$vf0xz,\(\$vi0xz\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.xzw \$vf0xzw,\(\$vi0xzw\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.y \$vf1,\(\$vi2y\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.yw \$vf0yw,\(\$vi0yw\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.yz \$vf1,\(\$vi2yz\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.yzw \$vf0yzw,\(\$vi0yzw\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.z \$vf0,\(\$vi31z\+\+\)'
|
||||
.*: Error: Illegal operands `vsqi\.zw \$vf0zw,\(\$vi0zw\+\+\)'
|
||||
.*: Error: Illegal operands `vsqrt \$Q,\$vf1zw'
|
||||
.*: Error: Illegal operands `vsqrt \$Q,\$vf31xw'
|
||||
.*: Error: Illegal operands `vsqrt \$Q,\$vf31xy'
|
||||
.*: Error: Illegal operands `vsubai\.w \$ACCw,\$vf0w,\$0'
|
||||
.*: Error: Illegal operands `vsubai\.w \$ACCw,\$vf1x,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.w \$ACCx,\$vf31w,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.x \$ACCw,\$vf31x,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.xw \$ACCw,\$vf0xw,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.xw \$ACCxw,\$vf1x,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.xw \$ACCxw,\$vf31xw,\$0'
|
||||
.*: Error: Illegal operands `vsubai\.xy \$ACCxy,\$vf0y,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.xy \$ACCxy,\$vf1x,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.xy \$ACCxy,\$vf311xy,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.xyz \$ACCxyz,\$vf1yz,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.xyz \$ACCxyz,\$vf31xyz,\$ACC'
|
||||
.*: Error: Illegal operands `vsubai\.xyzw \$ACCxyzw,\$vf0xyzw,\$R'
|
||||
.*: Error: Illegal operands `vsubai\.xyzw \$ACCxyzw,\$vf1xyzw,\$Q'
|
||||
.*: Error: Illegal operands `vsubai\.xz \$ACCxz,\$vf1z,\$I'
|
||||
.*: Error: Illegal operands `vsubai\.y \$ACCy,\$vf31,\$3'
|
||||
.*: Error: Illegal operands `vsubai\.yw \$ACCyw,\$vf0yw,\$Iyw'
|
||||
.*: Error: Illegal operands `vsubai\.zw \$ACCzw,\$vf1zw,\$Izw'
|
||||
.*: Error: Illegal operands `vsubai\.zw \$ACCzw,\$vf31w,\$I'
|
||||
.*: Error: Illegal operands `vsubaq\.w \$ACCw,\$Q,\$Q'
|
||||
.*: Error: Illegal operands `vsubaq\.w \$ACCw,\$I,\$Q'
|
||||
.*: Error: Illegal operands `vsubaq\.xyw \$ACCxyw,\$vf0xw,\$Q'
|
||||
.*: Error: Illegal operands `vsubaq\.xyzw \$ACCxyzw,\$vf0xyz,\$Q'
|
||||
.*: Error: Illegal operands `vsubaq\.xzw \$ACCxzw,\$vf1xw,\$Q'
|
||||
.*: Error: Illegal operands `vsubaq\.yw \$ACCyw,\$vf31y,\$Q'
|
||||
.*: Error: Illegal operands `vsubaq\.yz \$ACCyz,\$vf0yz,\$ACC'
|
||||
.*: Error: Illegal operands `vsubaq\.yz \$ACCyz,\$vf1yz,\$I'
|
||||
.*: Error: Illegal operands `vsubax\.w \$ACCw,\$vf0w,\$vf0w'
|
||||
.*: Error: Illegal operands `vsubax\.w \$ACCw,\$vf0x,\$vf31x'
|
||||
.*: Error: Illegal operands `vsubax\.w \$ACCx,\$vf1w,\$vf2x'
|
||||
.*: Error: Illegal operands `vsubax\.w \$ACCx,\$vf31x,\$vf0x'
|
||||
.*: Error: Illegal operands `vsubax\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf0xyzw'
|
||||
.*: Error: Illegal operands `vsubax\.xzw \$ACCxzw,\$vf1xzw,\$vf2xzw'
|
||||
.*: Error: Illegal operands `vsubax\.y \$ACCy,\$vf1y,\$vf2'
|
||||
.*: Error: Illegal operands `vsubax\.y \$ACCy,\$vf31y,\$vf0y'
|
||||
.*: Error: Illegal operands `vsubax\.yw \$ACCyw,\$vf0yw,\$vf0yw'
|
||||
.*: Error: Illegal operands `vsubay\.yw \$ACCyw,\$vf0yw,\$vf31yw'
|
||||
.*: Error: Illegal operands `vsubay\.yzw \$ACCyzw,\$vf0yzw,\$vf31yzw'
|
||||
.*: Error: Illegal operands `vsubay\.z \$ACCz,\$vf0z,\$vf31z'
|
||||
.*: Error: Illegal operands `vsubay\.zw \$ACCzw,\$vf0zw,\$vf0zw'
|
||||
.*: Error: Illegal operands `vsubaz\.w \$ACCw,\$vf31w,\$vf15w'
|
||||
.*: Error: Illegal operands `vsubaz\.x \$ACCx,\$vf0x,\$vf31x'
|
||||
.*: Error: Illegal operands `vsubaz\.xy \$ACCxy,\$vf0xy,\$vf0xy'
|
||||
.*: Error: Illegal operands `vsubaz\.xz \$ACCxz,\$vf31xz,\$vf15xz'
|
||||
.*: Error: Illegal operands `vsubaz\.xz \$ACCxz,\$vf31z,\$vf31z'
|
||||
.*: Error: Illegal operands `vsubaz\.xzw \$ACCxw,\$vf0xzw,\$vf0z'
|
||||
.*: Error: Illegal operands `vsubaz\.xzw \$ACCz,\$vf0xzw,\$vf31z'
|
||||
.*: Error: Illegal operands `vsubaz\.xzw \$ACCxzw,\$vf1z,\$vf2z'
|
||||
.*: Error: Illegal operands `vsubaz\.yw \$ACCyw,\$vf1yw,\$vf2yw'
|
||||
.*: Error: Illegal operands `vsubi\.w \$vf31w,\$vf15w,\$0'
|
||||
.*: Error: Illegal operands `vsubi\.w \$vf31w,\$vf31w,\$R'
|
||||
.*: Error: Illegal operands `vsubi\.x \$vf0x,\$vf0y,\$I'
|
||||
.*: Error: Illegal operands `vsubi\.x \$vf0x,\$vf31x,\$Ix'
|
||||
.*: Error: Illegal operands `vsubi\.xy \$vf0xy,\$vf31y,\$I'
|
||||
.*: Error: Illegal operands `vsubi\.xy \$vf1x,\$vf2xy,\$I'
|
||||
.*: Error: Illegal operands `vsubq\.x \$vf31x,\$vf15x,\$Qx'
|
||||
.*: Error: Illegal operands `vsubq\.x \$vf31x,\$vf31y,\$Q'
|
||||
.*: Error: Illegal operands `vsubq\.xw \$vf0xw,\$vf0xw,\$0'
|
||||
.*: Error: Illegal operands `vsubq\.xw \$vf0xw,\$vf31xw,\$2'
|
||||
.*: Error: Illegal operands `vsubq\.xyzw \$vf1yzw,\$vf2xyzw,\$Q'
|
||||
.*: Error: Illegal operands `vsubq\.yw \$vf31w,\$vf15yw,\$Q'
|
||||
.*: Error: Illegal operands `vsubq\.yw \$vf31yw,\$vf31y,\$Q'
|
||||
.*: Error: Illegal operands `vsubx\.xyw \$vf0xyw,\$vf31xyw,\$vf0xyw'
|
||||
.*: Error: Illegal operands `vsubx\.xzw \$vf1xzw,\$vf2xzw,\$vf3xzw'
|
||||
.*: Error: Illegal operands `vsuby\.xw \$vf0xw,\$vf0xw,\$vf0xw'
|
||||
.*: Error: Illegal operands `vsuby\.zw \$vf0zw,\$vf0zw,\$vf0zw'
|
||||
.*: Error: Illegal operands `vsub\.z \$vf0z,\$vf31z,\$vf0x'
|
||||
.*: Error: Illegal operands `vsubz\.xyw \$vf31yw,\$vf15xyw,\$vf7z'
|
||||
.*: Error: Illegal operands `vsubz\.xyw \$vf31xyw,\$vf31yw,\$vf31z'
|
||||
.*: Error: Illegal operands `vsubz\.xyz \$vf0xyz,\$vf0xyz,\$vf0x'
|
||||
.*: Error: Illegal operands `vwaitq \$vf0x'
|
||||
684
gas/testsuite/gas/mips/r5900-error-vu0.s
Normal file
684
gas/testsuite/gas/mips/r5900-error-vu0.s
Normal file
|
|
@ -0,0 +1,684 @@
|
|||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.globl text_label .text
|
||||
text_label:
|
||||
# All instructions have at least one error in suffix or in register
|
||||
# usage. All errors should be detected by the assembler.
|
||||
vabs.w $vf0w, $vf0z
|
||||
vabs.w $vf0z, $vf31w
|
||||
vabs.xw $vf0xw, $vf0w
|
||||
vabs.xw $vf0x, $vf31xw
|
||||
vabs.xyzw $vf0xyz, $vf0xyzw
|
||||
vaddai.w $ACCw, $vf0w, $Q
|
||||
vaddai.w $ACCz, $vf0w, $Q
|
||||
vaddai.xyzw $ACCxyw, $vf0xyzw, $I
|
||||
vaddaq.w $ACCw, $vf31z, $Q
|
||||
vaddaq.x $ACCx, $vf0w, $Q
|
||||
vaddaq.x $ACCw, $vf1x, $Q
|
||||
vaddaq.xw $ACCxw, $vf1z, $Q
|
||||
vaddaq.xw $ACCw, $vf31xw, $Q
|
||||
vaddaq.xyw $ACCxw, $vf0xyw, $Q
|
||||
vaddaq.xyw $ACCxyw, $vf1yw, $Q
|
||||
vaddaq.xyzw $ACCxyzw, $vf1yzw, $Q
|
||||
vaddaq.z $ACCxz, $vf0xz, $Q
|
||||
vaddaq.x $ACCxz, $vf1xz, $Q
|
||||
vaddaq.xzw $ACCxw, $vf0xzw, $Q
|
||||
vaddaq.y $ACCy, $vf0y, $R
|
||||
vaddaq.y $ACCy, $vf1y, $I
|
||||
vaddaq.yw $ACCxyw, $vf0yw, $Q
|
||||
vaddaq.yw $ACCwy, $vf1yw, $Q
|
||||
vaddaq.yw $ACCyw, $vf31wy, $Q
|
||||
vaddaq.yz $ACCy, $vf0yz, $Q
|
||||
vaddaq.yzw $ACCxyzw, $vf0yzw, $Q
|
||||
vaddaq.yzw $ACCyzw, $vf1xyzw, $Q
|
||||
vaddaq.yzw $ACCyzw, $vf31yzw, $Qyzw
|
||||
vadda.w $ACCw, $vf1w, $vf2z
|
||||
vadda.w $ACCw, $vf31w, $vf0x
|
||||
vaddaw.xyzw $ACCxyzw, $vf0xyzw, $vf0x
|
||||
vaddaw.xyzw $ACCxyzw, $vf0xyzw, $vf31xyzw
|
||||
vaddaw.xz $ACCxyz, $vf0xz, $vf0w
|
||||
vaddaw.xz $ACCxzw, $vf0xz, $vf31w
|
||||
vaddaw.xz $ACCxz, $vf1xyz, $vf2w
|
||||
vaddaw.xz $ACCxz, $vf31xzw, $vf0w
|
||||
vaddaw.xz $ACCxz, $vf31z, $vf15w
|
||||
vaddaw.xzw $ACCxyzw, $vf0xzw, $vf0w
|
||||
vaddaw.xzw $ACC, $vf0, $vf31z
|
||||
vaddaw.xzw $ACCxzw, $vf1xzw, $vf2z
|
||||
vaddaw.xzw $ACCxzw, $vf31xzw, $vf0x
|
||||
vaddaw.y $ACCy, $vf0y, $vf0z
|
||||
vaddax.w $ACCw, $vf0w, $vf31z
|
||||
vaddax.w $ACC, $vf1, $vf2z
|
||||
vaddax.w $ACCw, $vf31w, $vf0w
|
||||
vaddax.w $ACCw, $vf31w, $vf15y
|
||||
vadda.xw $ACCxw, $vf0xw, $vf0xyw
|
||||
vadda.xw $ACCxw, $vf0xw, $vf31wx
|
||||
vaddax.x $ACCw, $vf0x, $vf0x
|
||||
vaddax.x $ACCx, $vf0x, $vf31w
|
||||
vaddax.x $ACCx, $vf1x, $vf2y
|
||||
vaddax.x $ACCx, $vf31x, $vf0z
|
||||
vaddax.xw $ACCxw, $vf0xw, $vf0y
|
||||
vaddax.xw $ACCxw, $vf0xw, $vf31z
|
||||
vaddax.xw $ACCxw, $vf1xw, $vf2w
|
||||
vaddax.xw $ACCxw, $vf31wx, $vf0
|
||||
vaddax.xyzw $ACC, $vf1, $vf2y
|
||||
vaddax.xyzw $ACC, $vf31, $vf0z
|
||||
vadda.zw $ACCzw, $vf0zw, $vf0wz
|
||||
vadda.zw $ACCzw, $vf0w, $vf31zw
|
||||
vadda.zw $ACCw, $vf1zw, $vf2zw
|
||||
vadda.zw $ACCxzw, $vf31zw, $vf0zw
|
||||
vadda.zw $ACCzw, $vf31xzw, $vf15zw
|
||||
vadda.zw $ACCzw, $vf31zw, $vf31yzw
|
||||
vaddaz.x $ACCx, $vf0x, $vf0x
|
||||
vaddaz.x $ACCx, $vf0x, $vf31y
|
||||
vaddaz.xw $ACCxw, $vf31w, $vf15z
|
||||
vaddaz.xw $ACCx, $vf31xw, $vf31z
|
||||
vaddaz.xy $ACCx, $vf0xy, $vf0z
|
||||
vaddaz.xy $ACCxyz, $vf0xy, $vf31z
|
||||
vaddaz.y $ACCx, $vf31y, $vf0z
|
||||
vaddaz.yw $ACCyw, $vf0yw, $a0
|
||||
vaddaz.yw $ACC, $0, $31
|
||||
vaddi.w $vf0w, $vf31w, $Q
|
||||
vaddi.w $vf1w, $vf2w, $R
|
||||
vaddi.w $vf31w, $vf0w, $ACC
|
||||
vaddi.w $vf31w, $vf15w, $ACCw
|
||||
vaddi.xzw $vf1xyzw, $vf2xzw, $I
|
||||
vaddi.xzw $vf31xw, $vf0xzw, $I
|
||||
vaddi.xzw $vf31xzw, $vf15xzw, $Ixzw
|
||||
vaddq.w $vf1w, $vf2w, $Qw
|
||||
vaddq.w $vf31w, $vf0w, $R
|
||||
vaddq.w $vf31w, $vf15w, $ACCw
|
||||
vaddq.w $vf31w, $vf31w, $ACC
|
||||
vaddq.xyzw $vf31xyzw, $vf32xyzw, $Q
|
||||
vaddq.xyzw $vf31xyzw, $32, $Q
|
||||
vaddq.xz $vf0xz, $-1, $Q
|
||||
vaddw.xyzw $vf31xyzw, $vf15xyzw, $vf7z
|
||||
vaddx.yw $vf31yw, $vf31yw, $vf31y
|
||||
vadd.xyz $vf0xyz, $vf0xyz, $vf0xz
|
||||
vadd.xyz $vf0xyz, $vf0xyz, $vf31xyzw
|
||||
vadd.xyz $vf0xyz, $vf31xyzw, $vf0xyz
|
||||
vaddx.yz $vf0yz, $vf0xyz, $vf0x
|
||||
vaddz.xyzw $vf31xyzw, $vf0xyzw, $vf0x
|
||||
vaddz.xyzw $vf31xyzw, $vf15xyzw, $vf7y
|
||||
vaddz.xyzw $vf31xyzw, $vf31xyzw, $vf31w
|
||||
vcallms -1
|
||||
vcallms -0x0080
|
||||
vcallms 0x1
|
||||
vcallms 0x7
|
||||
vcallms 0x4
|
||||
vcallms 0x2
|
||||
vcallms 0x40000
|
||||
vcallms 0x40008
|
||||
vclipw.xyz $vf0xyz, $vf0x
|
||||
vclipw.xyz $vf0xyz, $vf31y
|
||||
vclipw.xyz $vf1xyz, $vf2z
|
||||
vdiv $Q, $vf0x, $vf0xy
|
||||
vdiv $Q, $vf0xyzw, $vf31y
|
||||
vdiv $Q, $vf1, $vf2z
|
||||
vdiv $Q, $vf31x, $vf15
|
||||
vdiv $0, $vf31w, $vf31y
|
||||
vdiv $Q, $vf32y, $vf0w
|
||||
vftoi0.w $vf0w, $vf0x
|
||||
vftoi0.w $vf0x, $vf31w
|
||||
vftoi0.w $vf1xw, $vf2w
|
||||
vftoi0.w $vf31wx, $vf0w
|
||||
vftoi0.w $vf31w, $vf15wz
|
||||
vftoi12.xw $vf0xw, $vf0w
|
||||
vftoi12.xw $vf0x, $vf31xw
|
||||
vftoi15.xyz $vf31xyzw, $vf15xyz
|
||||
vftoi15.xyz $vf31xyz, $vf31xyzw
|
||||
vftoi15.xyzw $vf0xyzw, $vf0xyz
|
||||
vftoi15.y $vf1y, $vf2x
|
||||
vftoi15.y $vf31y, $vf0w
|
||||
viaddi $vi0, $vi0, -17
|
||||
viaddi $vi1, $vi2, 16
|
||||
viaddi $vi31, $vi0, 17
|
||||
viaddi $vi31, $vi15, 32
|
||||
viaddi $vi31, $vi31, 31
|
||||
viand $vi0xyzw, $vi0, $vi0
|
||||
viand $vi0, $vi0xyzw, $vi31
|
||||
viand $vi0, $vi31, $vi0xyzw
|
||||
viand $vi1, $vi2, $vi3x
|
||||
viand $vi31, $vi0y, $vi0
|
||||
viand $vi31w, $vi15, $vi7
|
||||
viand $vi31, $vi31, $vi31x
|
||||
vilwr.w $vi0, ($vi0x)
|
||||
vilwr.w $vi0, ($vi31y)
|
||||
vilwr.w $vi1, ($vi2z)
|
||||
vilwr.w $vi31, ($vi0w)
|
||||
vilwr.w $vi31, ($vi15xyzw)
|
||||
vilwr.w $vi31x, ($vi31)
|
||||
vilwr.x $vi0y, ($vi0)
|
||||
vilwr.x $vi0z, ($vi31)
|
||||
vilwr.x $vi1w, ($vi2)
|
||||
vilwr.x $vi31xyzw, ($vi0)
|
||||
vilwr.x $vi31xy, ($vi15)
|
||||
vilwr.x $vi31zw, ($vi31)
|
||||
vilwr.y $vi0wx, ($vi0)
|
||||
vilwr.y $vi0xyzw, ($vi31)
|
||||
vilwr.y $vi1y, ($vi2)
|
||||
vilwr.y $vi31, ($vi0y)
|
||||
vilwr.z $vi0z, ($vi0)
|
||||
vilwr.z $vi0, ($vi31z)
|
||||
vior $vi0x, $vi0, $vi0
|
||||
vior $vi0, $vi0x, $vi31
|
||||
vior $vi0, $vi31, $vi0x
|
||||
vior $vi1y, $vi2, $vi3
|
||||
vior $vi31, $vi0y, $vi0
|
||||
vior $vi31, $vi15, $vi7y
|
||||
vior $vi31xyzw, $vi31, $vi31
|
||||
visub $vi0x, $vi0, $vi0
|
||||
visub $vi0, $vi0y, $vi31
|
||||
visub $vi0, $vi31, $vi0z
|
||||
visub $vi1w, $vi2, $vi3
|
||||
visub $vi31, $vi0xy, $vi0
|
||||
visub $vi31, $vi15, $vi7zw
|
||||
visub $vi31, $vi31, $vi31w
|
||||
viswr.w $vi0, ($vi0w)
|
||||
viswr.w $vi0w, ($vi31)
|
||||
viswr.x $vi0x, ($vi31)
|
||||
viswr.x $vi1, ($vi2x)
|
||||
viswr.x $vi31x, ($vi0x)
|
||||
viswr.y $vi31y, ($vi15)
|
||||
viswr.y $vi31, ($vi31y)
|
||||
viswr.z $vi0, ($vi0z)
|
||||
viswr.z $vi0z, ($vi31)
|
||||
viswr.z $vi1z, ($vi2z)
|
||||
vitof0.w $vf1w, $vf2x
|
||||
vitof0.w $vf31z, $vf0w
|
||||
vitof0.xw $vf0xw, $vf0xyw
|
||||
vitof0.xw $vf0xw, $vf31w
|
||||
vitof12.xw $vf31xw, $vf0x
|
||||
vitof12.xzw $vf0xzw, $vf31xz
|
||||
vitof12.xzw $vf1xzw, $vf2xw
|
||||
vitof12.xzw $vf31xzw, $vf0xyzw
|
||||
vitof12.xzw $vf31xyzw, $vf15xzw
|
||||
vitof12.xzw $vf31xw, $vf31xzw
|
||||
vitof12.y $vf0y, $vf0w
|
||||
vitof12.y $vf0x, $vf31y
|
||||
vitof15.xyw $vf0xyw, $vf31xw
|
||||
vitof15.xyw $vf1xyw, $vf2yxw
|
||||
vitof15.xyw $vf31xwy, $vf15xyw
|
||||
vitof15.xyzw $vf1.xyzw, $vf2xyzw
|
||||
vitof15.xyzw $vf31xyzw, $vf0.xyzw
|
||||
vitof4.xw $vf31xw, $31xw
|
||||
vitof4.xy $0xy, $vf0xy
|
||||
vitof4.xyzw $vf0yzw, $vf0xyzw
|
||||
vitof4.yzw $vf1yzw, $vf2yw
|
||||
vlqd.w $vf0, (--$vi0w)
|
||||
vlqd.w $vf0, (--$vi31w)
|
||||
vlqd.w $vf0x, (--$vi0)
|
||||
vlqd.x $vf0w, (--$vi0x)
|
||||
vlqd.x $vf0x, (--$vi31x)
|
||||
vlqd.x $vf0w, (--$vi0)
|
||||
vlqd.xw $vf0, (--$vi0xw)
|
||||
vlqd.xy $vf0, (--$vi0xy)
|
||||
vlqd.xyw $vf0, (--$vi0xyw)
|
||||
vlqd.xyz $vf0, (--$vi0xyz)
|
||||
vlqd.xyzw $vf0, (--$vi0xyzw)
|
||||
vlqd.xz $vf0, (--$vi0xz)
|
||||
vlqd.xzw $vf0, (--$vi0xzw)
|
||||
vlqd.y $vf0, (--$vi0y)
|
||||
vlqd.yw $vf0, (--$vi0yw)
|
||||
vlqd.yz $vf0, (--$vi0yz)
|
||||
vlqd.yzw $vf0, (--$vi0yzw)
|
||||
vlqd.z $vf0, (--$vi0z)
|
||||
vlqd.zw $vf0, (--$vi0zw)
|
||||
vlqi.w $vf0, ($vi0w++)
|
||||
vlqi.x $vf31, ($vi15x++)
|
||||
vlqi.xw $vf0x, ($vi0++)
|
||||
vlqi.xw $vf0, ($vi31xw++)
|
||||
vlqi.xy $vf0, ($vi0xy++)
|
||||
vlqi.xy $vf1, ($2xy++)
|
||||
vlqi.xyw $vf0, ($vi0xyw++)
|
||||
vlqi.xyz $vf0, ($vi0xyz++)
|
||||
vlqi.xyzw $vf0, ($vi0xyzw++)
|
||||
vlqi.xz $vf0, ($vi0xz++)
|
||||
vlqi.xzw $vf0, ($vi0xzw++)
|
||||
vlqi.y $vf0, ($vi0y++)
|
||||
vlqi.yw $vf0, ($vi0yw++)
|
||||
vlqi.yz $vf0yz, ($vi0yz++)
|
||||
vlqi.yzw $vf0, ($vi0yzw++)
|
||||
vlqi.z $vf0, ($vi0z++)
|
||||
vlqi.zw $vf0, ($vi0zw++)
|
||||
vmaddai.w $ACCw, $vf0w, $R
|
||||
vmaddai.w $ACCw, $vf1w, $Iw
|
||||
vmaddai.w $ACCw, $vf31w, $Q
|
||||
vmaddai.x $ACCx, $vf0x, $ACC
|
||||
vmaddai.x $ACCy, $vf1w, $I
|
||||
vmaddai.x $ACCxy, $vf31x, $I
|
||||
vmaddai.xw $ACCxw, $vf0xyw, $I
|
||||
vmaddai.xy $ACCxy, $vf0xyw, $I
|
||||
vmaddai.xy $ACCxy, $vf1xyz, $I
|
||||
vmaddai.xy $ACCxyz, $vf31xy, $I
|
||||
vmaddai.xyw $ACCxy, $vf0xyw, $I
|
||||
vmaddai.yw $ACCyw, $vf1w, $I
|
||||
vmaddai.yw $ACCyw, $vf31y, $I
|
||||
vmaddai.yz $ACCyz, $vf0yz, $R
|
||||
vmaddaq.xyz $ACCxyz, $vf0xyz, $R
|
||||
vmaddaq.xyz $ACCxyz, $vf1xyz, $Qxyz
|
||||
vmaddaq.xzw $ACCxzw, $vf31xzw, $Qxzw
|
||||
vmaddaq.y $ACCy, $vf0y, $R
|
||||
vmaddaq.y $ACCy, $vf1y, $ACCy
|
||||
vmaddaq.y $ACCy, $vf31y, $ACC
|
||||
vmaddaw.z $ACCz, $vf31z, $vf0x
|
||||
vmaddaw.zw $ACCzw, $vf31zw, $vf15y
|
||||
vmaddax.w $ACCw, $vf1w, $vf2w
|
||||
vmadda.xw $ACCxw, $vf31xw, $vf31wx
|
||||
vmaddax.xyz $ACCxyz, $vf0xyz, $vf0xyz
|
||||
vmaddax.xyzw $ACCxyzw, $vf0xyzw, $vf0xyzw
|
||||
vmaddax.xz $ACCxz, $vf0xz, $vf31xz
|
||||
vmaddax.xzw $ACCxzw, $vf0xzw, $vf0xzw
|
||||
vmaddax.z $ACCz, $vf31z, $vf15z
|
||||
vmaddax.zw $ACCzw, $vf1zw, $vf2zw
|
||||
vmadday.w $ACCw, $vf1w, $vf2w
|
||||
vmadday.w $ACCw, $vf31y, $vf0y
|
||||
vmadday.w $ACCy, $vf31w, $vf15y
|
||||
vmadday.w $ACCy, $vf31y, $vf31y
|
||||
vmadday.xyzw $ACCxyzw, $vf0xyzw, $vf0xyzw
|
||||
vmadday.xyzw $ACCxyzw, $vf0y, $vf31y
|
||||
vmadday.xyzw $ACCy, $vf1xyzw, $vf2y
|
||||
vmadday.xyzw $ACCy, $vf31y, $vf0y
|
||||
vmaddi.x $vf0x, $vf31x, $Ix
|
||||
vmaddi.xw $vf1xw, $vf2xw, $Ixw
|
||||
vmaddi.xy $vf31xy, $vf0xy, $Ixy
|
||||
vmaddi.xyw $vf0xyw, $vf0xyw, $Ixyw
|
||||
vmaddi.xyzw $vf1xyzw, $vf2xyzw, $Ixyzw
|
||||
vmaddi.y $vf0y, $vf0y, $Iy
|
||||
vmaddi.yw $vf0yw, $vf0yw, $Iyw
|
||||
vmaddi.zw $vf0zw, $vf31zw, $0
|
||||
vmaddq.w $vf0w, $vf0w, $0
|
||||
vmadd.w $vf0w, $vf0w, $vf0y
|
||||
vmaddw.xyz $vf31xyz, $vf15xyz
|
||||
vmaddw.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
|
||||
vmaddx.yw $vf1yw, $vf2yw, $vf3yw
|
||||
vmaddy.xy $vf31xy, $vf15xy, $vf7xy
|
||||
vmadd.z $vf1z, $vf2z, $vf3x
|
||||
vmadd.z $vf31z, $vf0z, $vf0w
|
||||
vmaddz.xyw $vf0xyw, $vf0xyw, $vf31x
|
||||
vmaddz.xz $vf0xz, $vf31xz, $vf0xz
|
||||
vmaddz.y $vf31y, $vf0y, $vf0y
|
||||
vmaxi.w $vf31w, $vf15w, $Q
|
||||
vmaxi.w $vf31w, $vf31w, $0
|
||||
vmax.w $vf31w, $vf31w, $vf31x
|
||||
vmaxw.w $vf0w, $vf0w, $vf0x
|
||||
vmaxw.x $vf0x, $vf0x, $vf0x
|
||||
vmaxw.x $vf0w, $vf0w, $vf31w
|
||||
vmaxw.xw $vf0xw, $vf0xw, $vf0xw
|
||||
vmaxw.xw $vf0w, $vf0w, $vf31w
|
||||
vmaxw.xy $vf0xy, $vf31xy, $vf0xy
|
||||
vmaxw.xy $vf1xy, $vf2w, $vf3w
|
||||
vmaxw.xy $vf31w, $vf0xy, $vf0w
|
||||
vmax.x $vf0x, $vf0x, $vf31w
|
||||
vmaxx.w $vf0w, $vf0w, $vf31w
|
||||
vmaxx.w $vf0x, $vf31x, $vf0x
|
||||
vmaxx.w $vf31w, $vf0w, $vf0w
|
||||
vmaxx.w $vf31x, $vf15x, $vf7x
|
||||
vmax.xw $vf31xw, $vf15xw, $vf7w
|
||||
vmaxx.x $vf0x, $vf0x, $vf0w
|
||||
vmaxx.x $vf31w, $vf15x, $vf7x
|
||||
vmaxx.x $vf31x, $vf31w, $vf31x
|
||||
vmaxx.xw $vf31xw, $vf15xw, $vf7xw
|
||||
vmaxx.xy $vf0xy, $vf31xy, $vf0xy
|
||||
vmaxx.xyw $vf0xyw, $vf0xyw, $vf0xyw
|
||||
vmaxx.xyz $vf0xyz, $vf0xyz, $vf0xyz
|
||||
vmaxx.xyzw $vf0xyzw, $vf0xyzw, $vf0xyzw
|
||||
vmaxx.xyzw $vf0xyzw, $vf0x, $vf31x
|
||||
vmaxx.xyzw $vf0x, $vf31xyzw, $vf0x
|
||||
vmaxx.xyzw $vf1x, $vf2x, $vf3x
|
||||
vmaxx.xzw $vf31xzw, $vf15xzw, $vf7xzw
|
||||
vmaxx.y $vf0y, $vf0y, $vf0y
|
||||
vmaxx.y $vf0y, $vf0x, $vf31x
|
||||
vmaxx.y $vf0x, $vf31y, $vf0x
|
||||
vmaxx.yw $vf1yw, $vf2yw, $vf3yw
|
||||
vmaxx.yz $vf0yz, $vf0yz, $vf0yz
|
||||
vmaxx.yz $vf0x, $vf0x, $vf31x
|
||||
vmaxx.z $vf31z, $vf0z, $vf0z
|
||||
vmaxx.z $vf31z, $vf15x, $vf7x
|
||||
vmaxx.z $vf31x, $vf31z, $vf31x
|
||||
vmaxx.zw $vf1zw, $vf2zw, $vf3zw
|
||||
vmax.y $vf0y, $vf0y, $vf31x
|
||||
vmax.yw $vf0yw, $vf0yw, $vf31w
|
||||
vmax.yw $vf0yw, $vf31yw, $vf0y
|
||||
vmaxy.xz $vf31xz, $vf15xz, $vf7xz
|
||||
vmaxy.xzw $vf1xzw, $vf2xzw, $vf3xzw
|
||||
vmaxy.y $vf1y, $vf2y
|
||||
vmaxy.yz $vf0yz, $vf31yz, $vf0yz
|
||||
vmaxy.yzw $vf0yzw, $vf0yzw, $vf0yzw
|
||||
vmaxy.yzw $vf31y, $vf15y, $vf7y
|
||||
vmaxy.yzw $vf31yzw, $vf31yw, $vf31y
|
||||
vmaxy.z $vf0z, $vf0z, $vf0z
|
||||
vmaxy.z $vf0z, $vf0y, $vf31y
|
||||
vmaxy.z $vf0y, $vf31z, $vf0y
|
||||
vmaxz.xw $vf31xw, $vf31xw, $vf31xw
|
||||
vmaxz.xy $vf0xy, $vf0xy, $vf0xy
|
||||
vmaxz.xyw $vf0xyw, $vf0xyw, $vf0xyw
|
||||
vmaxz.xyz $vf1xyz, $vf2xyz, $vf3xyz
|
||||
vmaxz.xyz $vf31xyz, $vf0z, $vf0z
|
||||
vmaxz.xyz $vf31z, $vf15xyz, $vf7z
|
||||
vmaxz.xyz $vf31z, $vf31z, $vf31z
|
||||
vmaxz.xyzw $vf0xyzw, $vf0xyzw, $vf0xyzw
|
||||
vmaxz.xyzw $vf0xyzw, $vf0z, $vf31z
|
||||
vmaxz.xyzw $vf0z, $vf31z, $vf0z
|
||||
vmaxz.xyzw $vf1xyzw, $vf2xyzw, $vfz
|
||||
vmaxz.xyzw $vf31xyzw, $vf0xyzw, $vf0xyzw
|
||||
vmaxz.xz $vf0xz, $vf0xz, $vf0xz
|
||||
vmaxz.y $vf31y, $vf15z, $vf7z
|
||||
vmaxz.y $vf31y, $vf31y, $vf31y
|
||||
vmaxz.yw $vf0yw, $vf0yw, $vf0yw
|
||||
vmaxz.yzw $vf0yzw, $vf0yzw, $vf31yzw
|
||||
vmaxz.yzw $vf0yzw, $vf31z, $vf0z
|
||||
vmaxz.yzw $vf1z, $vf2yzw, $vf3z
|
||||
vmaxz.yzw $vf31z, $vf0z, $vf0z
|
||||
vmaxz.z $vf31z, $vf31z, $vf31x
|
||||
vmfir.w $vf0w, $vi0w
|
||||
vmfir.w $vf0, $vi31w
|
||||
vmfir.x $vf0x, $vi0x
|
||||
vmfir.x $vf0, $vi31x
|
||||
vmfir.xw $vf0xw, $vi31xw
|
||||
vmfir.xy $vf1xy, $vi2xy
|
||||
vmfir.xy $vf31, $vi0xy
|
||||
vmfir.xyw $vf0xyw, $vi31xyw
|
||||
vmfir.xyw $vf31xyw, $vi0x
|
||||
vmfir.xyz $vf0xyz, $vi0xyz
|
||||
vmfir.xyzw $vf1xyzw, $vi2xyzw
|
||||
vmfir.xz $vf0xz, $vi31xz
|
||||
vmfir.xzw $vf0xzw, $vi31xzw
|
||||
vmfir.y $vf0y, $vi0y
|
||||
vmfir.yw $vf0yw, $vi0yw
|
||||
vmfir.yz $vf0yz, $vi31yz
|
||||
vmfir.yzw $vf0yzw, $vi0yzw
|
||||
vmfir.z $vf0z, $vi0z
|
||||
vmfir.z $0z, $vi31
|
||||
vmfir.zw $vf0zw, $vi0zw
|
||||
vminii.w $vf0w, $vf0w, $Iw
|
||||
vminii.w $vf0w, $vf31x, $I
|
||||
vminii.w $vf1x, $vf2w, $I
|
||||
vminii.xw $vf0xw, $vf31xw, $Ixw
|
||||
vminii.xw $vf1xw, $vf2w, $I
|
||||
vminii.xw $vf31x, $vf0xw, $I
|
||||
vminii.xyw $vf31xw, $vf0xyw, $I
|
||||
vminii.xyz $vf0xy, $vf0xyz, $I
|
||||
minii.xz $vf31z, $vf15xz, $I
|
||||
vminii.xz $vf31xz, $vf31x, $I
|
||||
vminii.xzw $vf0xzw, $vf0xw, $I
|
||||
vminii.xzw $vf0zw, $vf31xzw, $I
|
||||
vminii.xzw $vf1xyzw, $vf2xzw, $I
|
||||
vminii.xzw $vf31xzw, $vf0xyzw, $I
|
||||
vminii.yw $vf31yw, $vf31yw, $R
|
||||
vminii.yz $vf0yz, $vf0yz, $Q
|
||||
vminii.yz $vf0yz, $vf31yz, $ACC
|
||||
vminii.yzw $vf31yzw, $vf0yzw, $R
|
||||
vminii.yzw $vf31yzw, $vf15yzw, $ACC
|
||||
vminii.yzw $vf31yzw, $vf31yzw, $Q
|
||||
vmini.w $vf0w, $vf0w, $vf0x
|
||||
vminiw.w $vf31w, $vf31w, $vf31x
|
||||
vminiw.x $vf0x, $vf0x, $vf0x
|
||||
vminiw.x $vf0x, $vf0w, $vf31w
|
||||
vminiw.x $vf0w, $vf31x, $vf0w
|
||||
vminiw.x $vf1w, $vf2w, $vf3w
|
||||
vminiw.xw $vf0xw, $vf31xw, $vf0xw
|
||||
vminiw.xw $vf1w, $vf2w, $vf3w
|
||||
vminiw.xyzw $vf0xyzw, $vf0xyzw, $vf0xyzw
|
||||
vminiw.xyzw $vf0xyzw, $vf0xxyzw, $vf31w
|
||||
vminiw.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
|
||||
vminiw.xyzw $vf1xyzw, $vf2xyzw, $vf3ww
|
||||
vminiw.xz $vf31xz, $vf0xz, $vf0xz
|
||||
vminiw.yw $vf0yw, $vf0yw, $vf0yw
|
||||
vminiw.yz $vf31yz, $vf0yz, $vf0yz
|
||||
vminiw.z $vf31z, $vf0z, $vf0z
|
||||
vminiw.z $vf31z, $vf15w, $vf7w
|
||||
vminiw.z $vf31w, $vf31z, $vf31w
|
||||
vminix.xw $vf0xw, $vf31xw, $vf0xw
|
||||
vminix.xyw $vf0xyw, $vf0xyw, $vf0xyw
|
||||
vminix.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
|
||||
vminix.yw $vf31yw, $vf31yw, $vf31yw
|
||||
vminix.zw $vf31zw, $vf31zw, $vf31zw
|
||||
vmini.y $vf0y, $vf0x, $vf0y
|
||||
vminiy.w $vf0w, $vf31w, $vf0w
|
||||
vminiy.x $vf31x, $vf15x, $vf7x
|
||||
vminiy.x $vf31x, $vf31y, $vf31y
|
||||
vminiy.xw $vf0y, $vf0xw, $vf0y
|
||||
vminiy.xw $vf0xw, $vf0y, $vf31y
|
||||
vminiy.xw $vf0xw, $vf31xw, $vf0xw
|
||||
vminiy.xyz $vf31xyz, $vf31xyz, $vf31xyz
|
||||
vminiy.xyzw $vf0xyzw, $vf0y, $vf0y
|
||||
vminiy.xyzw $vf0y, $vf0xyzw, $vf31y
|
||||
vminiy.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
|
||||
vminiy.yw $vf1yw, $vf2yw, $vf3yw
|
||||
vminiy.zw $vf1zw, $vf2zw, $vf3zw
|
||||
vmini.z $vf0z, $vf0z, $vf0x
|
||||
vminiz.x $vf0x, $vf31x, $vf0x
|
||||
vminiz.xw $vf0xw, $vf31xw, $vf0xw
|
||||
vminiz.xyw $vf31xyw, $vf0xyw, $vf0xyw
|
||||
vminiz.xyw $vf31xyw, $vf15z, $vf7z
|
||||
vmove.xyw $vf0xyw, $vf0xw
|
||||
vmove.y $vf0y, $vf31x
|
||||
vmr32.xw $vf0xw, $vf0w
|
||||
vmr32.xw $vf0w, $vf31xw
|
||||
vmsubai.xy $ACCxy, $vf31xy, $Q
|
||||
vmsubai.xyw $ACCxyw, $vf0xyw, $0
|
||||
vmsubai.xyw $ACCxyw, $vf1xyw, $ACC
|
||||
vmsubai.xyw $ACCxyw, $vf31xw, $I
|
||||
vmsubaq.y $ACCy, $vf31y, $Qy
|
||||
vmsubaq.yw $ACCw, $vf0yw, $Q
|
||||
vmsubaq.yw $ACCwy, $vf1yw, $Q
|
||||
vmsubaw.x $ACCx, $vf31x, $vf0x
|
||||
vmsubaw.x $ACCx, $vf31w, $vf15w
|
||||
vmsubaw.x $ACCw, $vf31x, $vf31w
|
||||
vmsubaw.xw $ACCw, $vf0xw, $vf0w
|
||||
vmsubaw.xw $ACCxw, $vf0w, $vf31w
|
||||
vmsubaw.xw $ACCxw, $vf1xw, $vf2xw
|
||||
vmsubax.yzw $ACCyzw, $vf0yzw, $vf31yzw
|
||||
vmsubax.z $ACCz, $vf31z, $vf0z
|
||||
vmsuba.y $ACCy, $vf31y, $vf15a
|
||||
vmsuba.yw $ACCyw, $vf31yw, $vf0w
|
||||
vmsubay.x $ACCx, $vf31x, $vf15x
|
||||
vmsubay.x $ACCx, $vf31y, $vf31y
|
||||
vmsubay.xw $ACCxw, $vf0xw, $vf0xw
|
||||
vmsubaz.xy $ACCxy, $vf0xy, $vf31xy
|
||||
vmsubaz.yw $ACCyw, $vf31yw, $vf0yw
|
||||
vmsubi.xyzw $vf31xyzw, $vf0xyzw, $R
|
||||
vmsubw.xyw $vf0xyw, $vf0xyw, $vf0xyw
|
||||
vmsubw.xzw $vf0xzw, $vf0xzw, $vf31xzw
|
||||
vmsubw.y $vf31y, $vf31y, $vf31y
|
||||
vmsubw.yw $vf0yw, $vf0y, $vf0w
|
||||
vmsubw.yw $vf0w, $vf0yw, $vf31w
|
||||
vmsubw.zw $vf0zw, $vf0zw, $vf31zw
|
||||
vmsubx.w $vf0w, $vf0w, $vf0w
|
||||
vmsub.y $vf31y, $vf15y, $vf7w
|
||||
vmsuby.x $vf0x, $vf0x, $vf31x
|
||||
vmsuby.x $vf0x, $vf31y, $vf0y
|
||||
vmsubz.x $vf0x, $vf31x, $vf0x
|
||||
vmulai.xyz $ACCxyz, $vf1xz, $I
|
||||
vmulaq.zw $ACCzw, $vf31zw, $I
|
||||
vmula.w $ACCw, $vf31w, $vf0x
|
||||
vmulax.xz $ACCxz, $vf0xz, $vf31xz
|
||||
vmulax.xz $ACCxz, $vf1x, $vf2x
|
||||
vmulax.xz $ACCx, $vf31xz, $vf0x
|
||||
vmulay.yzw $ACCyzw, $vf0yzw, $vf31yzw
|
||||
vmulaz.w $ACCw, $vf0w, $vf31w
|
||||
mulaz.xy $ACCz, $vf31xy, $vf0z
|
||||
vmulaz.xy $ACCxy, $vf31z, $vf15z
|
||||
vmulaz.z $ACCz, $vf1z, $vf2x
|
||||
vmuli.x $vf31x, $vf15x, $ACC
|
||||
vmulq.x $vf0x, $vf31x, $0
|
||||
vmulq.x $vf1x, $vf2x, $ACC
|
||||
vmulq.x $vf31x, $vf0x, $R
|
||||
vmulq.x $vf31x, $vf15x, $I
|
||||
vmulw.z $vf31z, $vf15z, $vf7z
|
||||
vmulw.z $vf31z, $vf31w, $vf31w
|
||||
vmulw.zw $vf0zw, $vf0zw, $vf0zw
|
||||
vmuly.xyzw $vf0xyzw, $vf0y, $vf31y
|
||||
vmuly.xyzw $vf0xyzw, $vf31xyzw, $vf0xyzw
|
||||
vmuly.xyzw $vf1xyzw, $vf2y, $vf3y
|
||||
vmuly.xyzw $vf31y, $vf0xyzw, $vf0y
|
||||
vmulz.y $vf0y, $vf31y, $vf0y
|
||||
vmulz.y $vf1y, $vf2z, $vf3z
|
||||
vmulz.y $vf31z, $vf0y, $vf0z
|
||||
vmulz.y $vf31z, $vf15z, $vf7z
|
||||
vopmsub $vf0x, $vf0, $vf31
|
||||
vopmsub $vf0, $vf31x, $vf0
|
||||
vopmsub $vf1, $vf2, $vf3x
|
||||
vopmsub $ACC, $vf0, $vf0
|
||||
vopmsub $vf31, $R, $vf7
|
||||
vopmsub $vf31, $vf31, $I
|
||||
vopmsub.xyz $vf0xyz, $vf0xyz, $vf0xy
|
||||
vopmula $0, $vf0, $vf0
|
||||
vopmula $Q, $vf0, $vf31
|
||||
vopmula $R, $vf1, $vf2
|
||||
vopmula $I, $vf31, $vf0
|
||||
vopmula $ACCx, $vf31, $vf15
|
||||
vopmula $ACCxyzw, $vf31, $vf31
|
||||
vopmula.xyz $ACCxyzw, $vf0xyz, $vf0xyz
|
||||
vopmula.xyzw $ACCxyzw, $vf0xyzw, $vf31xyzw
|
||||
vrget.w $vf0w, $0
|
||||
vrget.w $vf1w, $I
|
||||
vrget.w $vf31w, $Q
|
||||
vrget.x $vf0x, $ACC
|
||||
vrget.x $vf1y, $R
|
||||
vrget.xy $vf31x, $R
|
||||
vrget.xyw $vf0xw, $R
|
||||
vrget.xyw $vf1yw, $R
|
||||
vrget.xyw $vf31xy, $R
|
||||
vrget.xyz $vf0xy, $R
|
||||
vrget.xyz $vf1xyzw, $R
|
||||
vrget.xyz $vf31xyzw, $R
|
||||
vrget.xyzw $vf0xyz, $R
|
||||
vrget.xyzw $vf1xzw, $R
|
||||
vrget.xyzw $vf31yzw, $R
|
||||
vrget.xz $vf0xz, $0
|
||||
vrget.xz $vf1z, $R
|
||||
vrget.xzw $vf0xw, $R
|
||||
vrget.y $vf0z, $R
|
||||
vrget.y $vf1y, $I
|
||||
vrget.z $vf31z, $Q
|
||||
vrget.zw $vf0zw, $ACC
|
||||
vrnext.xyzw $vf0xyz, $R
|
||||
vrnext.xyzw $vf1xyzw, $0
|
||||
vrnext.xyzw $vf31xyzw, $Rxyzw
|
||||
vrnext.yz $vf31yz, $Ryz
|
||||
vrnext.z $vf0z, $Rz
|
||||
vrsqrt $Q, $vf0xz, $vf31y
|
||||
vrsqrt $Q, $vf1z, $vf2xz
|
||||
vrsqrt $Q, $vf31yx, $vf15w
|
||||
vrsqrt $Qx, $vf31x, $vf31y
|
||||
vrsqrt $0, $vf31y, $vf0w
|
||||
vrxor $0, $vf0w
|
||||
vrxor $R, $vf0xy
|
||||
vrxor $R, $vf0zw
|
||||
vrxor $R, $vf1yz
|
||||
vrxor $ACC, $vf31x
|
||||
vrxor $Q, $vf31y
|
||||
vsqd.w $vf0, (--$vi0w)
|
||||
vsqd.w $vf0, (--$vi31w)
|
||||
vsqd.x $vf1, (--$vi2x)
|
||||
vsqd.xw $vf0, (--$vi0xw)
|
||||
vsqd.xy $vf0, (--$vi0xy)
|
||||
vsqd.xyw $vf0, (--$vi0xyw)
|
||||
vsqd.xyz $vf0, (--$vi31xyz)
|
||||
vsqd.xyzw $vf0, (--$vi0xyzw)
|
||||
vsqd.xz $vf0, (--$vi31xz)
|
||||
vsqd.xzw $vf0, (--$vi0xzw)
|
||||
vsqd.y $vf0, (--$vi0y)
|
||||
vsqd.yw $vf0, (--$vi31yw)
|
||||
vsqd.yz $vf0, (--$vi31yz)
|
||||
vsqd.yzw $vf0, (--$vi31yzw)
|
||||
vsqd.yzw $vf0yzw, (--$vi0x)
|
||||
vsqd.z $vf1, (--$vi2z)
|
||||
vsqd.zw $vf1, (--$vi2zw)
|
||||
vsqi.w $vf0, ($vi0w++)
|
||||
vsqi.x $vf0x, ($vi0x++)
|
||||
vsqi.xw $vf0xw, ($vi0xw++)
|
||||
vsqi.xw $vf1x, ($vi2++)
|
||||
vsqi.xw $vf31w, ($vi0++)
|
||||
vsqi.xy $vf0, ($vi31xy++)
|
||||
vsqi.xyw $vf0x, ($vi0++)
|
||||
vsqi.xyw $vf0, ($vi31xyw++)
|
||||
vsqi.xyz $vf0xyz, ($vi0xyz++)
|
||||
vsqi.xyzw $vf0, ($vi31xyzw++)
|
||||
vsqi.xz $vf0xz, ($vi0xz++)
|
||||
vsqi.xzw $vf0xzw, ($vi0xzw++)
|
||||
vsqi.y $vf1, ($vi2y++)
|
||||
vsqi.yw $vf0yw, ($vi0yw++)
|
||||
vsqi.yz $vf1, ($vi2yz++)
|
||||
vsqi.yzw $vf0yzw, ($vi0yzw++)
|
||||
vsqi.z $vf0, ($vi31z++)
|
||||
vsqi.zw $vf0zw, ($vi0zw++)
|
||||
vsqrt $Q, $vf1zw
|
||||
vsqrt $Q, $vf31xw
|
||||
vsqrt $Q, $vf31xy
|
||||
vsubai.w $ACCw, $vf0w, $0
|
||||
vsubai.w $ACCw, $vf1x, $I
|
||||
vsubai.w $ACCx, $vf31w, $I
|
||||
vsubai.x $ACCw, $vf31x, $I
|
||||
vsubai.xw $ACCw, $vf0xw, $I
|
||||
vsubai.xw $ACCxw, $vf1x, $I
|
||||
vsubai.xw $ACCxw, $vf31xw, $0
|
||||
vsubai.xy $ACCxy, $vf0y, $I
|
||||
vsubai.xy $ACCxy, $vf1x, $I
|
||||
vsubai.xy $ACCxy, $vf311xy, $I
|
||||
vsubai.xyz $ACCxyz, $vf1yz, $I
|
||||
vsubai.xyz $ACCxyz, $vf31xyz, $ACC
|
||||
vsubai.xyzw $ACCxyzw, $vf0xyzw, $R
|
||||
vsubai.xyzw $ACCxyzw, $vf1xyzw, $Q
|
||||
vsubai.xz $ACCxz, $vf1z, $I
|
||||
vsubai.y $ACCy, $vf31, $3
|
||||
vsubai.yw $ACCyw, $vf0yw, $Iyw
|
||||
vsubai.zw $ACCzw, $vf1zw, $Izw
|
||||
vsubai.zw $ACCzw, $vf31w, $I
|
||||
vsubaq.w $ACCw, $Q, $Q
|
||||
vsubaq.w $ACCw, $I, $Q
|
||||
vsubaq.xyw $ACCxyw, $vf0xw, $Q
|
||||
vsubaq.xyzw $ACCxyzw, $vf0xyz, $Q
|
||||
vsubaq.xzw $ACCxzw, $vf1xw, $Q
|
||||
vsubaq.yw $ACCyw, $vf31y, $Q
|
||||
vsubaq.yz $ACCyz, $vf0yz, $ACC
|
||||
vsubaq.yz $ACCyz, $vf1yz, $I
|
||||
vsubax.w $ACCw, $vf0w, $vf0w
|
||||
vsubax.w $ACCw, $vf0x, $vf31x
|
||||
vsubax.w $ACCx, $vf1w, $vf2x
|
||||
vsubax.w $ACCx, $vf31x, $vf0x
|
||||
vsubax.xyzw $ACCxyzw, $vf31xyzw, $vf0xyzw
|
||||
vsubax.xzw $ACCxzw, $vf1xzw, $vf2xzw
|
||||
vsubax.y $ACCy, $vf1y, $vf2
|
||||
vsubax.y $ACCy, $vf31y, $vf0y
|
||||
vsubax.yw $ACCyw, $vf0yw, $vf0yw
|
||||
vsubay.yw $ACCyw, $vf0yw, $vf31yw
|
||||
vsubay.yzw $ACCyzw, $vf0yzw, $vf31yzw
|
||||
vsubay.z $ACCz, $vf0z, $vf31z
|
||||
vsubay.zw $ACCzw, $vf0zw, $vf0zw
|
||||
vsubaz.w $ACCw, $vf31w, $vf15w
|
||||
vsubaz.x $ACCx, $vf0x, $vf31x
|
||||
vsubaz.xy $ACCxy, $vf0xy, $vf0xy
|
||||
vsubaz.xz $ACCxz, $vf31xz, $vf15xz
|
||||
vsubaz.xz $ACCxz, $vf31z, $vf31z
|
||||
vsubaz.xzw $ACCxw, $vf0xzw, $vf0z
|
||||
vsubaz.xzw $ACCz, $vf0xzw, $vf31z
|
||||
vsubaz.xzw $ACCxzw, $vf1z, $vf2z
|
||||
vsubaz.yw $ACCyw, $vf1yw, $vf2yw
|
||||
vsubi.w $vf31w, $vf15w, $0
|
||||
vsubi.w $vf31w, $vf31w, $R
|
||||
vsubi.x $vf0x, $vf0y, $I
|
||||
vsubi.x $vf0x, $vf31x, $Ix
|
||||
vsubi.xy $vf0xy, $vf31y, $I
|
||||
vsubi.xy $vf1x, $vf2xy, $I
|
||||
vsubq.x $vf31x, $vf15x, $Qx
|
||||
vsubq.x $vf31x, $vf31y, $Q
|
||||
vsubq.xw $vf0xw, $vf0xw, $0
|
||||
vsubq.xw $vf0xw, $vf31xw, $2
|
||||
vsubq.xyzw $vf1yzw, $vf2xyzw, $Q
|
||||
vsubq.yw $vf31w, $vf15yw, $Q
|
||||
vsubq.yw $vf31yw, $vf31y, $Q
|
||||
vsubx.xyw $vf0xyw, $vf31xyw, $vf0xyw
|
||||
vsubx.xzw $vf1xzw, $vf2xzw, $vf3xzw
|
||||
vsuby.xw $vf0xw, $vf0xw, $vf0xw
|
||||
vsuby.zw $vf0zw, $vf0zw, $vf0zw
|
||||
vsub.z $vf0z, $vf31z, $vf0x
|
||||
vsubz.xyw $vf31yw, $vf15xyw, $vf7z
|
||||
vsubz.xyw $vf31xyw, $vf31yw, $vf31z
|
||||
vsubz.xyz $vf0xyz, $vf0xyz, $vf0x
|
||||
vwaitq $vf0x
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
194
gas/testsuite/gas/mips/r5900-full-vu0.d
Normal file
194
gas/testsuite/gas/mips/r5900-full-vu0.d
Normal file
|
|
@ -0,0 +1,194 @@
|
|||
#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric -mmips:5900
|
||||
#name: MIPS R5900 Full VU0
|
||||
#as: -march=r5900
|
||||
|
||||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> 4be0f9fd vabs\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0faa8 vadd\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0faa2 vaddi\.xyzw \$vf10xyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0faa0 vaddq\.xyzw \$vf10xyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1fa83 vaddw\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1fa80 vaddx\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1fa81 vaddy\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1fa82 vaddz\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0fabc vadda\.xyzw \$ACCxyzw,\$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fa3e vaddai\.xyzw \$ACCxyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0fa3c vaddaq\.xyzw \$ACCxyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1f83f vaddaw\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1f83c vaddax\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1f83d vadday\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1f83e vaddaz\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4a000038 vcallms 0x0
|
||||
[0-9a-f]+ <[^>]*> 4a001a38 vcallms 0x340
|
||||
[0-9a-f]+ <[^>]*> 4a007ff8 vcallms 0xff8
|
||||
[0-9a-f]+ <[^>]*> 4a00d839 vcallmsr \$vi27
|
||||
[0-9a-f]+ <[^>]*> 4bc1f9ff vclipw\.xyz \$vf31xyz,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4a2b0bbc vdiv \$Q,\$vf1y,\$vf11x
|
||||
[0-9a-f]+ <[^>]*> 4be0f97c vftoi0\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0f97d vftoi4\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0f97e vftoi12\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0f97f vftoi15\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4a007870 viadd \$vi1,\$vi15,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4a007ff2 viaddi \$vi0,\$vi15,-1
|
||||
[0-9a-f]+ <[^>]*> 4a007874 viand \$vi1,\$vi15,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4a207bfe vilwr\.w \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4b007bfe vilwr\.x \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4a807bfe vilwr\.y \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4a407bfe vilwr\.z \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4a007875 vior \$vi1,\$vi15,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4a207bff viswr\.w \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4b007bff viswr\.x \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4a807bff viswr\.y \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4a407bff viswr\.z \$vi0,\(\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4a007871 visub \$vi1,\$vi15,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4be0f93c vitof0\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0f93d vitof4\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0f93e vitof12\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0f93f vitof15\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be07b7e vlqd\.xyzw \$vf0xyzw,\(\-\-\$vi15\)
|
||||
[0-9a-f]+ <[^>]*> 4be07b7c vlqi\.xyzw \$vf0xyzw,\(\$vi15\+\+\)
|
||||
[0-9a-f]+ <[^>]*> 4be0faa9 vmadd\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0faa3 vmaddi\.xyzw \$vf10xyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0faa1 vmaddq\.xyzw \$vf10xyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1fa8b vmaddw\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1fa88 vmaddx\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1fa89 vmaddy\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1fa8a vmaddz\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0fabd vmadda\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fa3f vmaddai\.xyzw \$ACCxyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0fa3d vmaddaq\.xyzw \$ACCxyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1f8bf vmaddaw\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1f8bc vmaddax\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1f8bd vmadday\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1f8be vmaddaz\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0faab vmax\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fa9d vmaxi\.xyzw \$vf10xyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be1fa93 vmaxw\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1fa90 vmaxx\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1fa91 vmaxy\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1fa92 vmaxz\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be07bfd vmfir\.xyzw \$vf0xyzw,\$vi15
|
||||
[0-9a-f]+ <[^>]*> 4be0faaf vmini\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fa9f vminii\.xyzw \$vf10xyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be1fa97 vminiw\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1fa94 vminix\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1fa95 vminiy\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1fa96 vminiz\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0fb3c vmove\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fb3d vmr32\.xyzw \$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0faad vmsub\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0faa7 vmsubi\.xyzw \$vf10xyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0faa5 vmsubq\.xyzw \$vf10xyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1fa8f vmsubw\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1fa8c vmsubx\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1fa8d vmsuby\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1fa8e vmsubz\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0fafd vmsuba\.xyzw \$ACCxyzw,\$vf0xyzw,\$vf31xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fa7f vmsubai\.xyzw \$ACCxyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0fa7d vmsubaq\.xyzw \$ACCxyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1f8ff vmsubaw\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1f8fc vmsubax\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1f8fd vmsubay\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1f8fe vmsubaz\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4a400bfc vmtir \$vi0,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0faaa vmul\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fa9e vmuli\.xyzw \$vf10xyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0fa9c vmulq\.xyzw \$vf10xyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1fa9b vmulw\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1fa98 vmulx\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1fa99 vmuly\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1fa9a vmulz\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0fabe vmula\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0f9fe vmulai\.xyzw \$ACCxyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0f9fc vmulaq\.xyzw \$ACCxyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1f9bf vmulaw\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1f9bc vmulax\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1f9bd vmulay\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1f9be vmulaz\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4a0002ff vnop
|
||||
[0-9a-f]+ <[^>]*> 4bc0fafe vopmula\.xyz \$ACCxyz,\$vf31xyz,\$vf0xyz
|
||||
[0-9a-f]+ <[^>]*> 4bc0faae vopmsub\.xyz \$vf10xyz,\$vf31xyz,\$vf0xyz
|
||||
[0-9a-f]+ <[^>]*> 4be0043d vrget.xyzw \$vf0xyzw,\$R
|
||||
[0-9a-f]+ <[^>]*> 4a600c3e vrinit \$R,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be0043c vrnext\.xyzw \$vf0xyzw,\$R
|
||||
[0-9a-f]+ <[^>]*> 4a6b0bbe vrsqrt \$Q,\$vf1w,\$vf11x
|
||||
[0-9a-f]+ <[^>]*> 4a000c3f vrxor \$R,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be0fb7f vsqd\.xyzw \$vf31xyzw,\(\-\-\$vi0\)
|
||||
[0-9a-f]+ <[^>]*> 4be0fb7d vsqi\.xyzw \$vf31xyzw,\(\$vi0\+\+\)
|
||||
[0-9a-f]+ <[^>]*> 4b2b03bd vsqrt \$Q,\$vf11z
|
||||
[0-9a-f]+ <[^>]*> 4be0faac vsub\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0faa6 vsubi\.xyzw \$vf10xyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0faa4 vsubq\.xyzw \$vf10xyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1fa87 vsubw\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1fa84 vsubx\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1fa85 vsuby\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1fa86 vsubz\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4be0fafc vsuba\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0fa7e vsubai\.xyzw \$ACCxyzw,\$vf31xyzw,\$I
|
||||
[0-9a-f]+ <[^>]*> 4be0fa7c vsubaq\.xyzw \$ACCxyzw,\$vf31xyzw,\$Q
|
||||
[0-9a-f]+ <[^>]*> 4be1f87f vsubaw\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1w
|
||||
[0-9a-f]+ <[^>]*> 4be1f87c vsubax\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1x
|
||||
[0-9a-f]+ <[^>]*> 4be1f87d vsubay\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1y
|
||||
[0-9a-f]+ <[^>]*> 4be1f87e vsubaz\.xyzw \$ACCxyzw,\$vf31xyzw,\$vf1z
|
||||
[0-9a-f]+ <[^>]*> 4a0003bf vwaitq
|
||||
[0-9a-f]+ <[^>]*> 4be0faa8 vadd\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4b80faa8 vadd\.xy \$vf10xy,\$vf31xy,\$vf0xy
|
||||
[0-9a-f]+ <[^>]*> 4be0faa8 vadd\.xyzw \$vf10xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4b807b7c vlqi\.xy \$vf0xy,\(\$vi15\+\+\)
|
||||
[0-9a-f]+ <[^>]*> 4be20828 vadd\.xyzw \$vf0xyzw,\$vf1xyzw,\$vf2xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be520e8 vadd\.xyzw \$vf3xyzw,\$vf4xyzw,\$vf5xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be839a8 vadd\.xyzw \$vf6xyzw,\$vf7xyzw,\$vf8xyzw
|
||||
[0-9a-f]+ <[^>]*> 4beb5268 vadd\.xyzw \$vf9xyzw,\$vf10xyzw,\$vf11xyzw
|
||||
[0-9a-f]+ <[^>]*> 4bee6b28 vadd\.xyzw \$vf12xyzw,\$vf13xyzw,\$vf14xyzw
|
||||
[0-9a-f]+ <[^>]*> 4bf183e8 vadd\.xyzw \$vf15xyzw,\$vf16xyzw,\$vf17xyzw
|
||||
[0-9a-f]+ <[^>]*> 4bf49ca8 vadd\.xyzw \$vf18xyzw,\$vf19xyzw,\$vf20xyzw
|
||||
[0-9a-f]+ <[^>]*> 4bf7b568 vadd\.xyzw \$vf21xyzw,\$vf22xyzw,\$vf23xyzw
|
||||
[0-9a-f]+ <[^>]*> 4bface28 vadd\.xyzw \$vf24xyzw,\$vf25xyzw,\$vf26xyzw
|
||||
[0-9a-f]+ <[^>]*> 4bfde6e8 vadd\.xyzw \$vf27xyzw,\$vf28xyzw,\$vf29xyzw
|
||||
[0-9a-f]+ <[^>]*> 4be0ffa8 vadd\.xyzw \$vf30xyzw,\$vf31xyzw,\$vf0xyzw
|
||||
[0-9a-f]+ <[^>]*> 4a020830 viadd \$vi0,\$vi1,\$vi2
|
||||
[0-9a-f]+ <[^>]*> 4a0520f0 viadd \$vi3,\$vi4,\$vi5
|
||||
[0-9a-f]+ <[^>]*> 4a0839b0 viadd \$vi6,\$vi7,\$vi8
|
||||
[0-9a-f]+ <[^>]*> 4a0b5270 viadd \$vi9,\$vi10,\$vi11
|
||||
[0-9a-f]+ <[^>]*> 4a0e6b30 viadd \$vi12,\$vi13,\$vi14
|
||||
[0-9a-f]+ <[^>]*> 4a1183f0 viadd \$vi15,\$vi16,\$vi17
|
||||
[0-9a-f]+ <[^>]*> 4a149cb0 viadd \$vi18,\$vi19,\$vi20
|
||||
[0-9a-f]+ <[^>]*> 4a17b570 viadd \$vi21,\$vi22,\$vi23
|
||||
[0-9a-f]+ <[^>]*> 4a1ace30 viadd \$vi24,\$vi25,\$vi26
|
||||
[0-9a-f]+ <[^>]*> 4a1de6f0 viadd \$vi27,\$vi28,\$vi29
|
||||
[0-9a-f]+ <[^>]*> 4a00ffb0 viadd \$vi30,\$vi31,\$vi0
|
||||
[0-9a-f]+ <[^>]*> d8000000 lqc2 \$vf0,0\(\$0\)
|
||||
[0-9a-f]+ <[^>]*> d8217fff lqc2 \$vf1,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> d9088000 lqc2 \$vf8,-32768\(\$8\)
|
||||
[0-9a-f]+ <[^>]*> dbffffff lqc2 \$vf31,-1\(\$31\)
|
||||
[0-9a-f]+ <[^>]*> f8000000 sqc2 \$vf0,0\(\$0\)
|
||||
[0-9a-f]+ <[^>]*> f8217fff sqc2 \$vf1,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> f9088000 sqc2 \$vf8,-32768\(\$8\)
|
||||
[0-9a-f]+ <[^>]*> fbffffff sqc2 \$vf31,-1\(\$31\)
|
||||
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48400001 cfc2\.i \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4840f801 cfc2\.i \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48c00001 ctc2\.i \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 48c0f801 ctc2\.i \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48200001 qmfc2\.i \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 4820f801 qmfc2\.i \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48a00001 qmtc2\.i \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 48a0f801 qmtc2\.i \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$vf31
|
||||
\.\.\.
|
||||
214
gas/testsuite/gas/mips/r5900-full-vu0.s
Normal file
214
gas/testsuite/gas/mips/r5900-full-vu0.s
Normal file
|
|
@ -0,0 +1,214 @@
|
|||
.set noreorder
|
||||
.set noat
|
||||
|
||||
.globl text_label .text
|
||||
text_label:
|
||||
|
||||
# VU Macromode instruction set
|
||||
vabs.xyzw $vf0xyzw,$vf31xyzw
|
||||
vadd.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
|
||||
vaddi.xyzw $vf10xyzw,$vf31xyzw,$I
|
||||
vaddq.xyzw $vf10xyzw,$vf31xyzw,$Q
|
||||
vaddw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
|
||||
vaddx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
|
||||
vaddy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
|
||||
vaddz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
|
||||
vadda.xyzw $ACCxyzw,$vf0xyzw,$vf31xyzw
|
||||
vaddai.xyzw $ACCxyzw,$vf31xyzw,$I
|
||||
vaddaq.xyzw $ACCxyzw,$vf31xyzw,$Q
|
||||
vaddaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
|
||||
vaddax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
|
||||
vadday.xyzw $ACCxyzw,$vf31xyzw,$vf1y
|
||||
vaddaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
|
||||
vcallms 0x0
|
||||
vcallms 0x340
|
||||
vcallms 0xff8
|
||||
vcallmsr $vi27
|
||||
vclipw.xyz $vf31xyz,$vf1w
|
||||
vdiv $Q,$vf1y,$vf11x
|
||||
vftoi0.xyzw $vf0xyzw,$vf31xyzw
|
||||
vftoi4.xyzw $vf0xyzw,$vf31xyzw
|
||||
vftoi12.xyzw $vf0xyzw,$vf31xyzw
|
||||
vftoi15.xyzw $vf0xyzw,$vf31xyzw
|
||||
viadd $vi1,$vi15,$vi0
|
||||
viaddi $vi0,$vi15,-1
|
||||
viand $vi1,$vi15,$vi0
|
||||
vilwr.w $vi0,($vi15)
|
||||
vilwr.x $vi0,($vi15)
|
||||
vilwr.y $vi0,($vi15)
|
||||
vilwr.z $vi0,($vi15)
|
||||
vior $vi1,$vi15,$vi0
|
||||
viswr.w $vi0,($vi15)
|
||||
viswr.x $vi0,($vi15)
|
||||
viswr.y $vi0,($vi15)
|
||||
viswr.z $vi0,($vi15)
|
||||
visub $vi1,$vi15,$vi0
|
||||
vitof0.xyzw $vf0xyzw,$vf31xyzw
|
||||
vitof4.xyzw $vf0xyzw,$vf31xyzw
|
||||
vitof12.xyzw $vf0xyzw,$vf31xyzw
|
||||
vitof15.xyzw $vf0xyzw,$vf31xyzw
|
||||
vlqd.xyzw $vf0xyzw,(--$vi15)
|
||||
vlqi.xyzw $vf0xyzw,($vi15++)
|
||||
vmadd.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
|
||||
vmaddi.xyzw $vf10xyzw,$vf31xyzw,$I
|
||||
vmaddq.xyzw $vf10xyzw,$vf31xyzw,$Q
|
||||
vmaddw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
|
||||
vmaddx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
|
||||
vmaddy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
|
||||
vmaddz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
|
||||
vmadda.xyzw $ACCxyzw,$vf31xyzw,$vf0xyzw
|
||||
vmaddai.xyzw $ACCxyzw,$vf31xyzw,$I
|
||||
vmaddaq.xyzw $ACCxyzw,$vf31xyzw,$Q
|
||||
vmaddaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
|
||||
vmaddax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
|
||||
vmadday.xyzw $ACCxyzw,$vf31xyzw,$vf1y
|
||||
vmaddaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
|
||||
vmax.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
|
||||
vmaxi.xyzw $vf10xyzw,$vf31xyzw,$I
|
||||
vmaxw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
|
||||
vmaxx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
|
||||
vmaxy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
|
||||
vmaxz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
|
||||
vmfir.xyzw $vf0xyzw,$vi15
|
||||
vmini.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
|
||||
vminii.xyzw $vf10xyzw,$vf31xyzw,$I
|
||||
vminiw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
|
||||
vminix.xyzw $vf10xyzw,$vf31xyzw,$vf1x
|
||||
vminiy.xyzw $vf10xyzw,$vf31xyzw,$vf1y
|
||||
vminiz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
|
||||
vmove.xyzw $vf0xyzw,$vf31xyzw
|
||||
vmr32.xyzw $vf0xyzw,$vf31xyzw
|
||||
vmsub.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
|
||||
vmsubi.xyzw $vf10xyzw,$vf31xyzw,$I
|
||||
vmsubq.xyzw $vf10xyzw,$vf31xyzw,$Q
|
||||
vmsubw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
|
||||
vmsubx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
|
||||
vmsuby.xyzw $vf10xyzw,$vf31xyzw,$vf1y
|
||||
vmsubz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
|
||||
vmsuba.xyzw $ACCxyzw,$vf0xyzw,$vf31xyzw
|
||||
vmsubai.xyzw $ACCxyzw,$vf31xyzw,$I
|
||||
vmsubaq.xyzw $ACCxyzw,$vf31xyzw,$Q
|
||||
vmsubaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
|
||||
vmsubax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
|
||||
vmsubay.xyzw $ACCxyzw,$vf31xyzw,$vf1y
|
||||
vmsubaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
|
||||
vmtir $vi0,$vf1z
|
||||
vmul.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
|
||||
vmuli.xyzw $vf10xyzw,$vf31xyzw,$I
|
||||
vmulq.xyzw $vf10xyzw,$vf31xyzw,$Q
|
||||
vmulw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
|
||||
vmulx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
|
||||
vmuly.xyzw $vf10xyzw,$vf31xyzw,$vf1y
|
||||
vmulz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
|
||||
vmula.xyzw $ACCxyzw,$vf31xyzw,$vf0xyzw
|
||||
vmulai.xyzw $ACCxyzw,$vf31xyzw,$I
|
||||
vmulaq.xyzw $ACCxyzw,$vf31xyzw,$Q
|
||||
vmulaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
|
||||
vmulax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
|
||||
vmulay.xyzw $ACCxyzw,$vf31xyzw,$vf1y
|
||||
vmulaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
|
||||
vnop
|
||||
vopmula.xyz $ACCxyz,$vf31xyz,$vf0xyz
|
||||
vopmsub.xyz $vf10xyz,$vf31xyz,$vf0xyz
|
||||
vrget.xyzw $vf0xyzw,$R
|
||||
vrinit $R,$vf1w
|
||||
vrnext.xyzw $vf0xyzw,$R
|
||||
vrsqrt $Q,$vf1w,$vf11x
|
||||
vrxor $R,$vf1x
|
||||
vsqd.xyzw $vf31xyzw,(--$vi0)
|
||||
vsqi.xyzw $vf31xyzw,($vi0++)
|
||||
vsqrt $Q,$vf11z
|
||||
vsub.xyzw $vf10xyzw,$vf31xyzw,$vf0xyzw
|
||||
vsubi.xyzw $vf10xyzw,$vf31xyzw,$I
|
||||
vsubq.xyzw $vf10xyzw,$vf31xyzw,$Q
|
||||
vsubw.xyzw $vf10xyzw,$vf31xyzw,$vf1w
|
||||
vsubx.xyzw $vf10xyzw,$vf31xyzw,$vf1x
|
||||
vsuby.xyzw $vf10xyzw,$vf31xyzw,$vf1y
|
||||
vsubz.xyzw $vf10xyzw,$vf31xyzw,$vf1z
|
||||
vsuba.xyzw $ACCxyzw,$vf31xyzw,$vf0xyzw
|
||||
vsubai.xyzw $ACCxyzw,$vf31xyzw,$I
|
||||
vsubaq.xyzw $ACCxyzw,$vf31xyzw,$Q
|
||||
vsubaw.xyzw $ACCxyzw,$vf31xyzw,$vf1w
|
||||
vsubax.xyzw $ACCxyzw,$vf31xyzw,$vf1x
|
||||
vsubay.xyzw $ACCxyzw,$vf31xyzw,$vf1y
|
||||
vsubaz.xyzw $ACCxyzw,$vf31xyzw,$vf1z
|
||||
vwaitq
|
||||
|
||||
# Implicit suffixes
|
||||
vadd.xyzw $vf10,$vf31,$vf0
|
||||
vadd.xy $vf10,$vf31,$vf0
|
||||
vadd.xyzw $vf10,$vf31,$vf0
|
||||
vlqi.xy $vf0,($vi15++)
|
||||
|
||||
# VU floating point registers
|
||||
vadd.xyzw $vf0,$vf1,$vf2
|
||||
vadd.xyzw $vf3,$vf4,$vf5
|
||||
vadd.xyzw $vf6,$vf7,$vf8
|
||||
vadd.xyzw $vf9,$vf10,$vf11
|
||||
vadd.xyzw $vf12,$vf13,$vf14
|
||||
vadd.xyzw $vf15,$vf16,$vf17
|
||||
vadd.xyzw $vf18,$vf19,$vf20
|
||||
vadd.xyzw $vf21,$vf22,$vf23
|
||||
vadd.xyzw $vf24,$vf25,$vf26
|
||||
vadd.xyzw $vf27,$vf28,$vf29
|
||||
vadd.xyzw $vf30,$vf31,$vf0
|
||||
|
||||
# VU integer registers
|
||||
viadd $vi0,$vi1,$vi2
|
||||
viadd $vi3,$vi4,$vi5
|
||||
viadd $vi6,$vi7,$vi8
|
||||
viadd $vi9,$vi10,$vi11
|
||||
viadd $vi12,$vi13,$vi14
|
||||
viadd $vi15,$vi16,$vi17
|
||||
viadd $vi18,$vi19,$vi20
|
||||
viadd $vi21,$vi22,$vi23
|
||||
viadd $vi24,$vi25,$vi26
|
||||
viadd $vi27,$vi28,$vi29
|
||||
viadd $vi30,$vi31,$vi0
|
||||
|
||||
# Floating point transfer to VU
|
||||
lqc2 $0,0($0)
|
||||
lqc2 $1, 0x7fff($1)
|
||||
lqc2 $8, -0x8000($8)
|
||||
lqc2 $31, -1($31)
|
||||
|
||||
# Floating point transfer from VU
|
||||
sqc2 $0,0($0)
|
||||
sqc2 $1, 0x7fff($1)
|
||||
sqc2 $8, -0x8000($8)
|
||||
sqc2 $31, -1($31)
|
||||
|
||||
# Integer transfer from VU
|
||||
cfc2 $0,$0
|
||||
cfc2 $0,$31
|
||||
cfc2.i $0,$0
|
||||
cfc2.i $0,$31
|
||||
cfc2.ni $0,$0
|
||||
cfc2.ni $0,$31
|
||||
|
||||
# Integer transfer to VU
|
||||
ctc2 $0,$0
|
||||
ctc2 $0,$31
|
||||
ctc2.i $0,$0
|
||||
ctc2.i $0,$31
|
||||
ctc2.ni $0,$0
|
||||
ctc2.ni $0,$31
|
||||
|
||||
# Floating point transfer from VU
|
||||
qmfc2 $0,$0
|
||||
qmfc2 $0,$31
|
||||
qmfc2.i $0,$0
|
||||
qmfc2.i $0,$31
|
||||
qmfc2.ni $0,$0
|
||||
qmfc2.ni $0,$31
|
||||
|
||||
# Floating point transfer to VU
|
||||
qmtc2 $0,$0
|
||||
qmtc2 $0,$31
|
||||
qmtc2.i $0,$0
|
||||
qmtc2.i $0,$31
|
||||
qmtc2.ni $0,$0
|
||||
qmtc2.ni $0,$31
|
||||
|
||||
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
|
||||
.space 8
|
||||
|
|
@ -5,56 +5,56 @@
|
|||
.*: +file format .*mips.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
[0-9a-f]+ <[^>]*> d8000000 lqc2 \$0,0\(\$0\)
|
||||
[0-9a-f]+ <[^>]*> d8217fff lqc2 \$1,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> d9088000 lqc2 \$8,-32768\(\$8\)
|
||||
[0-9a-f]+ <[^>]*> dbffffff lqc2 \$31,-1\(\$31\)
|
||||
[0-9a-f]+ <[^>]*> d8000000 lqc2 \$vf0,0\(\$0\)
|
||||
[0-9a-f]+ <[^>]*> d8217fff lqc2 \$vf1,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> d9088000 lqc2 \$vf8,-32768\(\$8\)
|
||||
[0-9a-f]+ <[^>]*> dbffffff lqc2 \$vf31,-1\(\$31\)
|
||||
[0-9a-f]+ <[^>]*> 3c010001 lui \$1,0x1
|
||||
[0-9a-f]+ <[^>]*> 00220821 addu \$1,\$1,\$2
|
||||
[0-9a-f]+ <[^>]*> d8208000 lqc2 \$0,-32768\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> d8208000 lqc2 \$vf0,-32768\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> 3c01ffff lui \$1,0xffff
|
||||
[0-9a-f]+ <[^>]*> 003f0821 addu \$1,\$1,\$31
|
||||
[0-9a-f]+ <[^>]*> d8287fff lqc2 \$8,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> d8287fff lqc2 \$vf8,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> 3c01f123 lui \$1,0xf123
|
||||
[0-9a-f]+ <[^>]*> 00240821 addu \$1,\$1,\$4
|
||||
[0-9a-f]+ <[^>]*> d83f4567 lqc2 \$31,17767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> f8000000 sqc2 \$0,0\(\$0\)
|
||||
[0-9a-f]+ <[^>]*> f8217fff sqc2 \$1,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> f9088000 sqc2 \$8,-32768\(\$8\)
|
||||
[0-9a-f]+ <[^>]*> fbffffff sqc2 \$31,-1\(\$31\)
|
||||
[0-9a-f]+ <[^>]*> d83f4567 lqc2 \$vf31,17767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> f8000000 sqc2 \$vf0,0\(\$0\)
|
||||
[0-9a-f]+ <[^>]*> f8217fff sqc2 \$vf1,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> f9088000 sqc2 \$vf8,-32768\(\$8\)
|
||||
[0-9a-f]+ <[^>]*> fbffffff sqc2 \$vf31,-1\(\$31\)
|
||||
[0-9a-f]+ <[^>]*> 3c010001 lui \$1,0x1
|
||||
[0-9a-f]+ <[^>]*> 00220821 addu \$1,\$1,\$2
|
||||
[0-9a-f]+ <[^>]*> f8208000 sqc2 \$0,-32768\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> f8208000 sqc2 \$vf0,-32768\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> 3c01ffff lui \$1,0xffff
|
||||
[0-9a-f]+ <[^>]*> 003f0821 addu \$1,\$1,\$31
|
||||
[0-9a-f]+ <[^>]*> f8287fff sqc2 \$8,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> f8287fff sqc2 \$vf8,32767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> 3c01f123 lui \$1,0xf123
|
||||
[0-9a-f]+ <[^>]*> 00240821 addu \$1,\$1,\$4
|
||||
[0-9a-f]+ <[^>]*> f83f4567 sqc2 \$31,17767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48400001 cfc2.i \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 4840f801 cfc2.i \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48c00001 ctc2.i \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 48c0f801 ctc2.i \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48200001 qmfc2.i \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 4820f801 qmfc2.i \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48a00001 qmtc2.i \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 48a0f801 qmtc2.i \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$0
|
||||
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$31
|
||||
[0-9a-f]+ <[^>]*> f83f4567 sqc2 \$vf31,17767\(\$1\)
|
||||
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48400001 cfc2.i \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4840f801 cfc2.i \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48400000 cfc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 4840f800 cfc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48c00001 ctc2.i \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 48c0f801 ctc2.i \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48c00000 ctc2 \$0,\$vi0
|
||||
[0-9a-f]+ <[^>]*> 48c0f800 ctc2 \$0,\$vi31
|
||||
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48200001 qmfc2.i \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 4820f801 qmfc2.i \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48200000 qmfc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 4820f800 qmfc2 \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48a00001 qmtc2.i \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 48a0f801 qmtc2.i \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 48a00000 qmtc2 \$0,\$vf0
|
||||
[0-9a-f]+ <[^>]*> 48a0f800 qmtc2 \$0,\$vf31
|
||||
[0-9a-f]+ <[^>]*> 4900ffff bc2f [0-9a-f]+ <branch_label>
|
||||
[0-9a-f]+ <[^>]*> 00000000 nop
|
||||
[0-9a-f]+ <[^>]*> 4902fffd bc2fl [0-9a-f]+ <branch_label>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,13 @@
|
|||
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
|
||||
Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* mips.h: Document new VU0 operand characters.
|
||||
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
|
||||
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
|
||||
(OP_REG_R5900_ACC): New mips_reg_operand_types.
|
||||
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
|
||||
(mips_vu0_channel_mask): Declare.
|
||||
|
||||
2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
|
||||
|
|
|
|||
|
|
@ -401,7 +401,15 @@ enum mips_operand_type {
|
|||
OP_REPEAT_PREV_REG,
|
||||
|
||||
/* $pc, which has no encoding in the architectural instruction. */
|
||||
OP_PC
|
||||
OP_PC,
|
||||
|
||||
/* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
|
||||
which. */
|
||||
OP_VU0_SUFFIX,
|
||||
|
||||
/* Like OP_VU0_SUFFIX, but used when the operand's value has already
|
||||
been set. Any suffix used here must match the previous value. */
|
||||
OP_VU0_MATCH_SUFFIX
|
||||
};
|
||||
|
||||
/* Enumerates the types of MIPS register. */
|
||||
|
|
@ -430,7 +438,19 @@ enum mips_reg_operand_type {
|
|||
|
||||
/* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
|
||||
also be used in some contexts. */
|
||||
OP_REG_HW
|
||||
OP_REG_HW,
|
||||
|
||||
/* Floating-point registers $vf0-$vf31. */
|
||||
OP_REG_VF,
|
||||
|
||||
/* Integer registers $vi0-$vi31. */
|
||||
OP_REG_VI,
|
||||
|
||||
/* R5900 VU0 registers $I, $Q, $R and $ACC. */
|
||||
OP_REG_R5900_I,
|
||||
OP_REG_R5900_Q,
|
||||
OP_REG_R5900_R,
|
||||
OP_REG_R5900_ACC
|
||||
};
|
||||
|
||||
/* Base class for all operands. */
|
||||
|
|
@ -781,6 +801,26 @@ struct mips_opcode
|
|||
"Y" source register (OP_*_FS)
|
||||
"Z" source register (OP_*_FT)
|
||||
|
||||
R5900 VU0 Macromode instructions:
|
||||
"+5" 5 bit floating point register (FD)
|
||||
"+6" 5 bit floating point register (FS)
|
||||
"+7" 5 bit floating point register (FT)
|
||||
"+8" 5 bit integer register (FD)
|
||||
"+9" 5 bit integer register (FS)
|
||||
"+0" 5 bit integer register (FT)
|
||||
"+K" match an existing 4-bit channel mask starting at bit 21
|
||||
"+L" 2-bit channel index starting at bit 21
|
||||
"+M" 2-bit channel index starting at bit 23
|
||||
"+N" match an existing 2-bit channel index starting at bit 0
|
||||
"+f" 15 bit immediate for VCALLMS
|
||||
"+g" 5 bit signed immediate for VIADDI
|
||||
"+m" $ACC register (syntax only)
|
||||
"+q" $Q register (syntax only)
|
||||
"+r" $R register (syntax only)
|
||||
"+y" $I register (syntax only)
|
||||
"#+" "++" decorator in ($reg++) sequence
|
||||
"#-" "--" decorator in (--$reg) sequence
|
||||
|
||||
DSP ASE usage:
|
||||
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
|
||||
"3" 3 bit unsigned immediate (OP_*_SA3)
|
||||
|
|
@ -846,15 +886,15 @@ struct mips_opcode
|
|||
|
||||
Characters used so far, for quick reference when adding more:
|
||||
"1234567890"
|
||||
"%[]<>(),+:'@!$*&\~"
|
||||
"%[]<>(),+:'@!#$*&\~"
|
||||
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
|
||||
"abcdefghijklopqrstuvwxz"
|
||||
|
||||
Extension character sequences used so far ("+" followed by the
|
||||
following), for quick reference when adding more:
|
||||
"1234"
|
||||
"ABCEFGHIJPQSXZ"
|
||||
"abcijpstxz"
|
||||
"1234567890"
|
||||
"ABCEFGHIJKLMNPQSXZ"
|
||||
"abcfgijmpqrstxyz"
|
||||
*/
|
||||
|
||||
/* These are the bits which may be set in the pinfo field of an
|
||||
|
|
@ -960,6 +1000,8 @@ struct mips_opcode
|
|||
#define INSN2_COND_BRANCH 0x00001000
|
||||
/* Reads from $16. This is true of the MIPS16 0x6500 nop. */
|
||||
#define INSN2_READ_GPR_16 0x00002000
|
||||
/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
|
||||
#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
|
||||
|
||||
/* Masks used to mark instructions to indicate which MIPS ISA level
|
||||
they were introduced in. INSN_ISA_MASK masks an enumeration that
|
||||
|
|
@ -1490,6 +1532,7 @@ enum
|
|||
Many instructions are short hand for other instructions (i.e., The
|
||||
jal <register> instruction is short for jalr <register>). */
|
||||
|
||||
extern const struct mips_operand mips_vu0_channel_mask;
|
||||
extern const struct mips_operand *decode_mips_operand (const char *);
|
||||
extern const struct mips_opcode mips_builtin_opcodes[];
|
||||
extern const int bfd_mips_num_builtin_opcodes;
|
||||
|
|
|
|||
|
|
@ -1,3 +1,19 @@
|
|||
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
|
||||
Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
|
||||
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
|
||||
(print_vu0_channel): New function.
|
||||
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
|
||||
(print_insn_args): Handle '#'.
|
||||
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
|
||||
* mips-opc.c (mips_vu0_channel_mask): New constant.
|
||||
(decode_mips_operand): Handle new VU0 operand types.
|
||||
(VU0, VU0CH): New macros.
|
||||
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
|
||||
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
|
||||
Use "+6" rather than "G" for QMFC2 and QMTC2.
|
||||
|
||||
2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
|
||||
|
||||
* mips-formats.h (PCREL): Reorder parameters and update the definition
|
||||
|
|
|
|||
|
|
@ -917,6 +917,30 @@ print_reg (struct disassemble_info *info, const struct mips_opcode *opcode,
|
|||
case OP_REG_HW:
|
||||
info->fprintf_func (info->stream, "%s", mips_hwr_names[regno]);
|
||||
break;
|
||||
|
||||
case OP_REG_VF:
|
||||
info->fprintf_func (info->stream, "$vf%d", regno);
|
||||
break;
|
||||
|
||||
case OP_REG_VI:
|
||||
info->fprintf_func (info->stream, "$vi%d", regno);
|
||||
break;
|
||||
|
||||
case OP_REG_R5900_I:
|
||||
info->fprintf_func (info->stream, "$I");
|
||||
break;
|
||||
|
||||
case OP_REG_R5900_Q:
|
||||
info->fprintf_func (info->stream, "$Q");
|
||||
break;
|
||||
|
||||
case OP_REG_R5900_R:
|
||||
info->fprintf_func (info->stream, "$R");
|
||||
break;
|
||||
|
||||
case OP_REG_R5900_ACC:
|
||||
info->fprintf_func (info->stream, "$ACC");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -941,6 +965,25 @@ init_print_arg_state (struct mips_print_arg_state *state)
|
|||
memset (state, 0, sizeof (*state));
|
||||
}
|
||||
|
||||
/* Print OP_VU0_SUFFIX or OP_VU0_MATCH_SUFFIX operand OPERAND,
|
||||
whose value is given by UVAL. */
|
||||
|
||||
static void
|
||||
print_vu0_channel (struct disassemble_info *info,
|
||||
const struct mips_operand *operand, unsigned int uval)
|
||||
{
|
||||
if (operand->size == 4)
|
||||
info->fprintf_func (info->stream, "%s%s%s%s",
|
||||
uval & 8 ? "x" : "",
|
||||
uval & 4 ? "y" : "",
|
||||
uval & 2 ? "z" : "",
|
||||
uval & 1 ? "w" : "");
|
||||
else if (operand->size == 2)
|
||||
info->fprintf_func (info->stream, "%c", "xyzw"[uval]);
|
||||
else
|
||||
abort ();
|
||||
}
|
||||
|
||||
/* Print operand OPERAND of OPCODE, using STATE to track inter-operand state.
|
||||
UVAL is the encoding of the operand (shifted into bit 0) and BASE_PC is
|
||||
the base address for OP_PCREL operands. */
|
||||
|
|
@ -1201,6 +1244,11 @@ print_insn_arg (struct disassemble_info *info,
|
|||
case OP_PC:
|
||||
infprintf (is, "$pc");
|
||||
break;
|
||||
|
||||
case OP_VU0_SUFFIX:
|
||||
case OP_VU0_MATCH_SUFFIX:
|
||||
print_vu0_channel (info, operand, uval);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1231,6 +1279,11 @@ print_insn_args (struct disassemble_info *info,
|
|||
infprintf (is, "%c", *s);
|
||||
break;
|
||||
|
||||
case '#':
|
||||
++s;
|
||||
infprintf (is, "%c%c", *s, *s);
|
||||
break;
|
||||
|
||||
default:
|
||||
operand = decode_operand (s);
|
||||
if (!operand)
|
||||
|
|
@ -1365,6 +1418,14 @@ print_insn_mips (bfd_vma memaddr,
|
|||
info->insn_type = dis_dref;
|
||||
|
||||
infprintf (is, "%s", op->name);
|
||||
if (op->pinfo2 & INSN2_VU0_CHANNEL_SUFFIX)
|
||||
{
|
||||
unsigned int uval;
|
||||
|
||||
infprintf (is, ".");
|
||||
uval = mips_extract_operand (&mips_vu0_channel_mask, word);
|
||||
print_vu0_channel (info, &mips_vu0_channel_mask, uval);
|
||||
}
|
||||
|
||||
if (op->args[0])
|
||||
{
|
||||
|
|
|
|||
|
|
@ -30,6 +30,9 @@
|
|||
#include "opcode/mips.h"
|
||||
#include "mips-formats.h"
|
||||
|
||||
/* The 4-bit XYZW mask used in some VU0 instructions. */
|
||||
const struct mips_operand mips_vu0_channel_mask = { OP_VU0_SUFFIX, 4, 21 };
|
||||
|
||||
static unsigned char reg_0_map[] = { 0 };
|
||||
|
||||
/* Return the mips_operand structure for the operand at the beginning of P. */
|
||||
|
|
@ -46,6 +49,12 @@ decode_mips_operand (const char *p)
|
|||
case '2': HINT (10, 6);
|
||||
case '3': HINT (15, 6);
|
||||
case '4': HINT (20, 6);
|
||||
case '5': REG (5, 6, VF);
|
||||
case '6': REG (5, 11, VF);
|
||||
case '7': REG (5, 16, VF);
|
||||
case '8': REG (5, 6, VI);
|
||||
case '9': REG (5, 11, VI);
|
||||
case '0': REG (5, 16, VI);
|
||||
|
||||
case 'A': BIT (5, 6, 0); /* (0 .. 31) */
|
||||
case 'B': MSB (5, 11, 1, TRUE, 32); /* (1 .. 32), 32-bit op */
|
||||
|
|
@ -55,6 +64,10 @@ decode_mips_operand (const char *p)
|
|||
case 'G': MSB (5, 11, 33, FALSE, 64); /* (33 .. 64), 64-bit op */
|
||||
case 'H': MSB (5, 11, 1, FALSE, 64); /* (1 .. 32), 64-bit op */
|
||||
case 'J': HINT (10, 11);
|
||||
case 'K': SPECIAL (4, 21, VU0_MATCH_SUFFIX);
|
||||
case 'L': SPECIAL (2, 21, VU0_SUFFIX);
|
||||
case 'M': SPECIAL (2, 23, VU0_SUFFIX);
|
||||
case 'N': SPECIAL (2, 0, VU0_MATCH_SUFFIX);
|
||||
case 'P': BIT (5, 6, 32); /* (32 .. 63) */
|
||||
case 'Q': SINT (10, 6);
|
||||
case 'S': MSB (5, 11, 0, FALSE, 63); /* (0 .. 31), 64-bit op */
|
||||
|
|
@ -64,12 +77,18 @@ decode_mips_operand (const char *p)
|
|||
case 'a': SINT (8, 6);
|
||||
case 'b': SINT (8, 3);
|
||||
case 'c': INT_ADJ (9, 6, 255, 4, FALSE); /* (-256 .. 255) << 4 */
|
||||
case 'f': INT_ADJ (15, 6, 32767, 3, TRUE);
|
||||
case 'g': SINT (5, 6);
|
||||
case 'i': JALX (26, 0, 2);
|
||||
case 'j': SINT (9, 7);
|
||||
case 'm': REG (0, 0, R5900_ACC);
|
||||
case 'p': BIT (5, 6, 0); /* (0 .. 31), 32-bit op */
|
||||
case 'q': REG (0, 0, R5900_Q);
|
||||
case 'r': REG (0, 0, R5900_R);
|
||||
case 's': MSB (5, 11, 0, FALSE, 31); /* (0 .. 31) */
|
||||
case 't': REG (5, 16, COPRO);
|
||||
case 'x': BIT (5, 16, 0); /* (0 .. 31) */
|
||||
case 'y': REG (0, 0, R5900_I);
|
||||
case 'z': REG (5, 0, GP);
|
||||
}
|
||||
break;
|
||||
|
|
@ -267,6 +286,10 @@ decode_mips_operand (const char *p)
|
|||
/* 64 bit CPU with only 32 bit multiplication/division support. */
|
||||
#define M32 EE
|
||||
|
||||
/* Support for VU0 Coprocessor instructions */
|
||||
#define VU0 EE
|
||||
#define VU0CH INSN2_VU0_CHANNEL_SUFFIX
|
||||
|
||||
/* MIPS DSP ASE support.
|
||||
NOTE:
|
||||
1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
|
||||
|
|
@ -403,6 +426,136 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"gslqc1", "+Z,T,+c(b)", 0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LDD, 0, IL3A, 0, 0 },
|
||||
{"gssqc1", "+Z,T,+c(b)", 0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM, 0, IL3A, 0, 0 },
|
||||
|
||||
/* R5900 VU0 Macromode instructions. */
|
||||
{"vabs", "+7+K,+6+K", 0x4a0001fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vadd", "+5+K,+6+K,+7+K", 0x4a000028, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddi", "+5+K,+6+K,+y", 0x4a000022, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddq", "+5+K,+6+K,+q", 0x4a000020, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddw", "+5+K,+6+K,+7+N", 0x4a000003, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddx", "+5+K,+6+K,+7+N", 0x4a000000, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddy", "+5+K,+6+K,+7+N", 0x4a000001, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddz", "+5+K,+6+K,+7+N", 0x4a000002, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vadda", "+m+K,+7+K,+6+K", 0x4a0002bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddai", "+m+K,+6+K,+y", 0x4a00023e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddaq", "+m+K,+6+K,+q", 0x4a00023c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddaw", "+m+K,+6+K,+7+N", 0x4a00003f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddax", "+m+K,+6+K,+7+N", 0x4a00003c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vadday", "+m+K,+6+K,+7+N", 0x4a00003d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vaddaz", "+m+K,+6+K,+7+N", 0x4a00003e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vcallms", "+f", 0x4a000038, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"vcallmsr", "+9", 0x4a000039, 0xffff07ff, CP, 0, VU0, 0, 0 },
|
||||
{"vclipw.xyz", "+6+K,+7+N", 0x4bc001ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vdiv", "+q,+6+L,+7+M", 0x4a0003bc, 0xfe0007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vftoi0", "+7+K,+6+K", 0x4a00017c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vftoi4", "+7+K,+6+K", 0x4a00017d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vftoi12", "+7+K,+6+K", 0x4a00017e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vftoi15", "+7+K,+6+K", 0x4a00017f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"viadd", "+8,+9,+0", 0x4a000030, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"viaddi", "+0,+9,+g", 0x4a000032, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"viand", "+8,+9,+0", 0x4a000034, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"vilwr.w", "+0,(+9)", 0x4a2003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vilwr.x", "+0,(+9)", 0x4b0003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vilwr.y", "+0,(+9)", 0x4a8003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vilwr.z", "+0,(+9)", 0x4a4003fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vior", "+8,+9,+0", 0x4a000035, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"viswr.w", "+0,(+9)", 0x4a2003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"viswr.x", "+0,(+9)", 0x4b0003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"viswr.y", "+0,(+9)", 0x4a8003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"viswr.z", "+0,(+9)", 0x4a4003ff, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"visub", "+8,+9,+0", 0x4a000031, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"vitof0", "+7+K,+6+K", 0x4a00013c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vitof4", "+7+K,+6+K", 0x4a00013d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vitof12", "+7+K,+6+K", 0x4a00013e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vitof15", "+7+K,+6+K", 0x4a00013f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vlqd", "+7+K,(#-+9)", 0x4a00037e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vlqi", "+7+K,(+9#+)", 0x4a00037c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmadd", "+5+K,+6+K,+7+K", 0x4a000029, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddi", "+5+K,+6+K,+y", 0x4a000023, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddq", "+5+K,+6+K,+q", 0x4a000021, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddw", "+5+K,+6+K,+7+N", 0x4a00000b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddx", "+5+K,+6+K,+7+N", 0x4a000008, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddy", "+5+K,+6+K,+7+N", 0x4a000009, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddz", "+5+K,+6+K,+7+N", 0x4a00000a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmadda", "+m+K,+6+K,+7+K", 0x4a0002bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddai", "+m+K,+6+K,+y", 0x4a00023f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddaq", "+m+K,+6+K,+q", 0x4a00023d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddaw", "+m+K,+6+K,+7+N", 0x4a0000bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddax", "+m+K,+6+K,+7+N", 0x4a0000bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmadday", "+m+K,+6+K,+7+N", 0x4a0000bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaddaz", "+m+K,+6+K,+7+N", 0x4a0000be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmax", "+5+K,+6+K,+7+K", 0x4a00002b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaxi", "+5+K,+6+K,+y", 0x4a00001d, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaxw", "+5+K,+6+K,+7+N", 0x4a000013, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaxx", "+5+K,+6+K,+7+N", 0x4a000010, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaxy", "+5+K,+6+K,+7+N", 0x4a000011, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmaxz", "+5+K,+6+K,+7+N", 0x4a000012, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmfir", "+7+K,+9", 0x4a0003fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmini", "+5+K,+6+K,+7+K", 0x4a00002f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vminii", "+5+K,+6+K,+y", 0x4a00001f, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vminiw", "+5+K,+6+K,+7+N", 0x4a000017, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vminix", "+5+K,+6+K,+7+N", 0x4a000014, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vminiy", "+5+K,+6+K,+7+N", 0x4a000015, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vminiz", "+5+K,+6+K,+7+N", 0x4a000016, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmove", "+7+K,+6+K", 0x4a00033c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmr32", "+7+K,+6+K", 0x4a00033d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsub", "+5+K,+6+K,+7+K", 0x4a00002d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubi", "+5+K,+6+K,+y", 0x4a000027, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubq", "+5+K,+6+K,+q", 0x4a000025, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubw", "+5+K,+6+K,+7+N", 0x4a00000f, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubx", "+5+K,+6+K,+7+N", 0x4a00000c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsuby", "+5+K,+6+K,+7+N", 0x4a00000d, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubz", "+5+K,+6+K,+7+N", 0x4a00000e, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsuba", "+m+K,+7+K,+6+K", 0x4a0002fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubai", "+m+K,+6+K,+y", 0x4a00027f, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubaq", "+m+K,+6+K,+q", 0x4a00027d, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubaw", "+m+K,+6+K,+7+N", 0x4a0000ff, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubax", "+m+K,+6+K,+7+N", 0x4a0000fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubay", "+m+K,+6+K,+7+N", 0x4a0000fd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmsubaz", "+m+K,+6+K,+7+N", 0x4a0000fe, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmtir", "+0,+6+L", 0x4a0003fc, 0xff8007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vmul", "+5+K,+6+K,+7+K", 0x4a00002a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmuli", "+5+K,+6+K,+y", 0x4a00001e, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulq", "+5+K,+6+K,+q", 0x4a00001c, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulw", "+5+K,+6+K,+7+N", 0x4a00001b, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulx", "+5+K,+6+K,+7+N", 0x4a000018, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmuly", "+5+K,+6+K,+7+N", 0x4a000019, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulz", "+5+K,+6+K,+7+N", 0x4a00001a, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmula", "+m+K,+6+K,+7+K", 0x4a0002be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulai", "+m+K,+6+K,+y", 0x4a0001fe, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulaq", "+m+K,+6+K,+q", 0x4a0001fc, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulaw", "+m+K,+6+K,+7+N", 0x4a0001bf, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulax", "+m+K,+6+K,+7+N", 0x4a0001bc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulay", "+m+K,+6+K,+7+N", 0x4a0001bd, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vmulaz", "+m+K,+6+K,+7+N", 0x4a0001be, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vnop", "", 0x4a0002ff, 0xffffffff, CP, 0, VU0, 0, 0 },
|
||||
{"vopmula.xyz", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vopmula", "+m+K,+6+K,+7+K", 0x4bc002fe, 0xffe007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vopmsub.xyz", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"vopmsub", "+5+K,+6+K,+7+K", 0x4bc0002e, 0xffe0003f, CP, 0, VU0, 0, 0 },
|
||||
{"vrget", "+7+K,+r", 0x4a00043d, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vrinit", "+r,+6+L", 0x4a00043e, 0xff9f07ff, CP, 0, VU0, 0, 0 },
|
||||
{"vrnext", "+7+K,+r", 0x4a00043c, 0xfe00ffff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vrsqrt", "+q,+6+L,+7+M", 0x4a0003be, 0xfe0007ff, CP, 0, VU0, 0, 0 },
|
||||
{"vrxor", "+r,+6+L", 0x4a00043f, 0xff9f07ff, CP, 0, VU0, 0, 0 },
|
||||
{"vsqd", "+6+K,(#-+0)", 0x4a00037f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsqi", "+6+K,(+0#+)", 0x4a00037d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsqrt", "+q,+7+M", 0x4a2003bd, 0xfe60ffff, CP, 0, VU0, 0, 0 },
|
||||
{"vsub", "+5+K,+6+K,+7+K", 0x4a00002c, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubi", "+5+K,+6+K,+y", 0x4a000026, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubq", "+5+K,+6+K,+q", 0x4a000024, 0xfe1f003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubw", "+5+K,+6+K,+7+N", 0x4a000007, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubx", "+5+K,+6+K,+7+N", 0x4a000004, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsuby", "+5+K,+6+K,+7+N", 0x4a000005, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubz", "+5+K,+6+K,+7+N", 0x4a000006, 0xfe00003f, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsuba", "+m+K,+6+K,+7+K", 0x4a0002fc, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubai", "+m+K,+6+K,+y", 0x4a00027e, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubaq", "+m+K,+6+K,+q", 0x4a00027c, 0xfe1f07ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubaw", "+m+K,+6+K,+7+N", 0x4a00007f, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubax", "+m+K,+6+K,+7+N", 0x4a00007c, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubay", "+m+K,+6+K,+7+N", 0x4a00007d, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vsubaz", "+m+K,+6+K,+7+N", 0x4a00007e, 0xfe0007ff, CP, VU0CH, VU0, 0, 0 },
|
||||
{"vwaitq", "", 0x4a0003bf, 0xffffffff, CP, 0, VU0, 0, 0 },
|
||||
|
||||
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
|
||||
{"abs.s", "D,V", 0x46000005, 0xffff003f, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
|
||||
{"abs.d", "D,V", 0x46200005, 0xffff003f, WR_1|RD_2|FP_D, 0, I1, 0, SF },
|
||||
|
|
@ -1011,8 +1164,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, EE },
|
||||
{"lq", "t,o(b)", 0x78000000, 0xfc000000, WR_1|RD_3, 0, MMI, 0, 0 },
|
||||
{"lq", "t,A(b)", 0, (int) M_LQ_AB, INSN_MACRO, 0, MMI, 0, 0 },
|
||||
{"lqc2", "E,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2, 0, EE, 0, 0 },
|
||||
{"lqc2", "E,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE, 0, 0 },
|
||||
{"lqc2", "+7,o(b)", 0xd8000000, 0xfc000000, RD_3|WR_C2, 0, EE, 0, 0 },
|
||||
{"lqc2", "+7,A(b)", 0, (int) M_LQC2_AB, INSN_MACRO, 0, EE, 0, 0 },
|
||||
{"lui", "t,u", 0x3c000000, 0xffe00000, WR_1, 0, I1, 0, 0 },
|
||||
{"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_D, 0, I5_33|N55, 0, 0},
|
||||
{"lw", "t,o(b)", 0x8c000000, 0xfc000000, WR_1|RD_3|LDD, 0, I1, 0, 0 },
|
||||
|
|
@ -1601,8 +1754,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"snei", "t,r,+Q", 0x7000002f, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 },
|
||||
{"sq", "t,o(b)", 0x7c000000, 0xfc000000, RD_1|RD_3|SM, 0, MMI, 0, 0 },
|
||||
{"sq", "t,A(b)", 0, (int) M_SQ_AB, INSN_MACRO, 0, MMI, 0, 0 },
|
||||
{"sqc2", "E,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, EE, 0, 0 },
|
||||
{"sqc2", "E,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE, 0, 0 },
|
||||
{"sqc2", "+7,o(b)", 0xf8000000, 0xfc000000, RD_3|RD_C2|SM, 0, EE, 0, 0 },
|
||||
{"sqc2", "+7,A(b)", 0, (int) M_SQC2_AB, INSN_MACRO, 0, EE, 0, 0 },
|
||||
{"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_1|RD_2|FP_D, 0, I2, 0, SF },
|
||||
{"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, 0 },
|
||||
{"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_1|RD_2|FP_D, 0, SB1, 0, 0 },
|
||||
|
|
@ -1847,12 +2000,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"bc2t", "N,p", 0x49010000, 0xffe30000, RD_CC|CBD, 0, I32, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2tl", "p", 0x49030000, 0xffff0000, RD_CC|CBL, 0, I2|T3, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"bc2tl", "N,p", 0x49030000, 0xffe30000, RD_CC|CBL, 0, I32, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"cfc2", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"cfc2.i", "t,G", 0x48400001, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 },
|
||||
{"cfc2.ni", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 },
|
||||
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"ctc2.i", "t,G", 0x48c00001, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 },
|
||||
{"ctc2.ni", "t,G", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 },
|
||||
{"cfc2", "t,G", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
|
||||
{"cfc2", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 },
|
||||
{"cfc2.i", "t,+9", 0x48400001, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 },
|
||||
{"cfc2.ni", "t,+9", 0x48400000, 0xffe007ff, WR_1|RD_C2|LCD, 0, EE, 0, 0 },
|
||||
{"ctc2", "t,G", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
|
||||
{"ctc2", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 },
|
||||
{"ctc2.i", "t,+9", 0x48c00001, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 },
|
||||
{"ctc2.ni", "t,+9", 0x48c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, EE, 0, 0 },
|
||||
{"dmfc2", "t,i", 0x48200000, 0xffe00000, WR_1|RD_C2|LCD, 0, IOCT, 0, 0 },
|
||||
{"dmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2|LCD, 0, I3, 0, IOCT|IOCTP|IOCT2|EE },
|
||||
{"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, WR_1|RD_C2|LCD, 0, I64, 0, IOCT|IOCTP|IOCT2 },
|
||||
|
|
@ -1869,12 +2024,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"mthc2", "t,G", 0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD, 0, I33, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD, 0, I33, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"mthc2", "t,i", 0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|COD, 0, I33, 0, IOCT|IOCTP|IOCT2 },
|
||||
{"qmfc2", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
|
||||
{"qmfc2.i", "t,G", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
|
||||
{"qmfc2.ni", "t,G", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
|
||||
{"qmtc2", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
|
||||
{"qmtc2.i", "t,G", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
|
||||
{"qmtc2.ni", "t,G", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
|
||||
{"qmfc2", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
|
||||
{"qmfc2.i", "t,+6", 0x48200001, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
|
||||
{"qmfc2.ni", "t,+6", 0x48200000, 0xffe007ff, WR_1|RD_C2, 0, EE, 0, 0 },
|
||||
{"qmtc2", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
|
||||
{"qmtc2.i", "t,+6", 0x48a00001, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
|
||||
{"qmtc2.ni", "t,+6", 0x48a00000, 0xffe007ff, RD_1|WR_C2, 0, EE, 0, 0 },
|
||||
/* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
|
||||
instructions, so they are here for the latters to take precedence. */
|
||||
{"bc3f", "p", 0x4d000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, IOCT|IOCTP|IOCT2|EE },
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue