x86: also optimize KXOR{D,Q} and KANDN{D,Q}
These can be converted to 2-byte VEX encoding when both source registers are the same, by using KXORW / KANDNW as replacement.
This commit is contained in:
Jan Beulich
Jan Beulich
parent
ae2387feae
commit
1424ad8677
9 changed files with 56 additions and 9 deletions
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@ -1,3 +1,12 @@
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2018-07-31 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (optimize_encoding): Also handle kandnd,
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kandnq, kxord, and kxorq.
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* testsuite/gas/i386/optimize-1.s: Add kandn and kxor tests.
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* testsuite/gas/i386/optimize-1.d,
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testsuite/gas/i386/optimize-4.d,
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testsuite/gas/i386/optimize-5.d: Adjust expectations.
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2018-07-31 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (check_VecOperands): Convert masking handling
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@ -3942,7 +3942,11 @@ optimize_encoding (void)
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|| i.tm.base_opcode == 0x66f8
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|| i.tm.base_opcode == 0x66f9
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|| i.tm.base_opcode == 0x66fa
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|| i.tm.base_opcode == 0x66fb)
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|| i.tm.base_opcode == 0x66fb
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|| i.tm.base_opcode == 0x42
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|| i.tm.base_opcode == 0x6642
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|| i.tm.base_opcode == 0x47
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|| i.tm.base_opcode == 0x6647)
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&& i.tm.extension_opcode == None))
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{
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/* Optimize: -O2:
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@ -3973,6 +3977,12 @@ optimize_encoding (void)
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EVEX VOP %ymmM, %ymmM, %ymmN
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-> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
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-> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16)
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VOP, one of kxord and kxorq:
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VEX VOP %kM, %kM, %kN
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-> VEX kxorw %kM, %kM, %kN
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VOP, one of kandnd and kandnq:
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VEX VOP %kM, %kM, %kN
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-> VEX kandnw %kM, %kM, %kN
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*/
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if (is_evex_encoding (&i.tm))
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{
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@ -3985,6 +3995,11 @@ optimize_encoding (void)
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i.tm.opcode_modifier.evex = 0;
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}
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}
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else if (i.tm.operand_types[0].bitfield.regmask)
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{
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i.tm.base_opcode &= 0xff;
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i.tm.opcode_modifier.vexw = VEXW0;
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}
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else
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i.tm.opcode_modifier.vex = VEX128;
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@ -58,4 +58,8 @@ Disassembly of section .text:
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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#pass
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@ -66,3 +66,9 @@ _start:
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vpsubq %ymm1, %ymm1, %ymm5{z}{%k7}
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vpsubq %zmm1, %zmm1, %zmm5
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vpsubq %ymm1, %ymm1, %ymm5
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kxord %k1, %k1, %k5
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kxorq %k1, %k1, %k5
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kandnd %k1, %k1, %k5
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kandnq %k1, %k1, %k5
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@ -58,6 +58,10 @@ Disassembly of section .text:
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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#pass
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@ -58,6 +58,10 @@ Disassembly of section .text:
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f1 fb e9 vpsubq %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 47 e9 kxorw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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+[a-f0-9]+: c5 f4 42 e9 kandnw %k1,%k1,%k5
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+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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+[a-f0-9]+: 62 f1 f5 08 55 e9 vandnpd %xmm1,%xmm1,%xmm5
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#pass
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@ -1,3 +1,8 @@
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2018-07-31 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
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* i386-init.h, i386-tbl.h: Re-generate.
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2018-07-31 Jan Beulich <jbeulich@suse.com>
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* i386-opc.h (ZEROING_MASKING) Rename to ...
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@ -4211,7 +4211,7 @@ vpmovzxwq, 2, 0x6634, None, 1, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Ve
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kaddd, 3, 0x664A, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kandd, 3, 0x6641, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kandnd, 3, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kandnd, 3, 0x6642, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
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kmovd, 2, 0x6690, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Dword|Unspecified|BaseIndex, RegMask }
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kmovd, 2, 0x6691, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Dword|Unspecified|BaseIndex }
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knotd, 2, 0x6644, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
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@ -4219,10 +4219,10 @@ kord, 3, 0x6645, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|
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kortestd, 2, 0x6698, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
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ktestd, 2, 0x6699, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask }
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kxnord, 3, 0x6646, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kxord, 3, 0x6647, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kxord, 3, 0x6647, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
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kaddq, 3, 0x4A, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kandnq, 3, 0x42, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kandnq, 3, 0x42, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
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kandq, 3, 0x41, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kmovq, 2, 0x90, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask|Qword|Unspecified|BaseIndex, RegMask }
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kmovq, 2, 0x91, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Qword|Unspecified|BaseIndex }
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@ -4233,7 +4233,7 @@ ktestq, 2, 0x99, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=2|IgnoreSize
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kunpckdq, 3, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kunpckwd, 3, 0x4B, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kxnorq, 3, 0x46, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kxorq, 3, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask }
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kxorq, 3, 0x47, None, 1, CpuAVX512BW, Modrm|Vex=2|VexOpcode=0|VexVVVV=1|VexW=2|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegMask, RegMask, RegMask }
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kmovd, 2, 0xF292, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegMask }
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kmovd, 2, 0xF293, None, 1, CpuAVX512BW, Modrm|Vex=1|VexOpcode=0|VexW=1|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, Reg32 }
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@ -67739,7 +67739,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -67918,7 +67918,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -67958,7 +67958,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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@ -68197,7 +68197,7 @@ const insn_template i386_optab[] =
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0, 0, 0, 0 } },
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{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
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1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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2, 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0,
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0, 0 },
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{ { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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