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x86/Intel: correct VFPCLASSP{S,D} handling when displacement is present

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fits_in_disp8() can be called before ambiguous operands get resolved
or rejected (in process_suffix()), which requires that i.memshift be
non-negative to avoid an internal error. This case wasn't covered by
6c0946d0d2 ("x86: correct VFPCLASSP{S,D} operand size handling").
This commit is contained in:
Jan Beulich 2022-01-04 10:05:53 +01:00
parent 5ed4d49d10
commit 125ff8197d
4 changed files with 9 additions and 5 deletions
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6
gas/config/tc-i386.c
View file

@ -6327,7 +6327,7 @@ check_VecOperands (const insn_template *t)
i.memshift = t->opcode_modifier.disp8memshift;
else
{
const i386_operand_type *type = NULL;
const i386_operand_type *type = NULL, *fallback = NULL;
i.memshift = 0;
for (op = 0; op < i.operands; op++)
@ -6341,6 +6341,8 @@ check_VecOperands (const insn_template *t)
type = &t->operand_types[op];
else if (!i.types[op].bitfield.unspecified)
type = &i.types[op];
else /* Ambiguities get resolved elsewhere. */
fallback = &t->operand_types[op];
}
else if (i.types[op].bitfield.class == RegSIMD
&& t->opcode_modifier.evex != EVEXLIG)
@ -6353,6 +6355,8 @@ check_VecOperands (const insn_template *t)
i.memshift = 4;
}
if (!type && !i.memshift)
type = fallback;
if (type)
{
if (type->bitfield.zmmword)

2
gas/testsuite/gas/i386/avx512dq-inval.s
View file

@ -24,7 +24,7 @@ _start:
vcvtuqq2ps xmm0, [rax]
vfpclasspd k0, [eax], 0
vfpclassps k0, [eax], 0
vfpclassps k0, [eax+1], 0
.att_syntax prefix

4
gas/testsuite/gas/i386/noavx512-2.l
View file

@ -104,7 +104,7 @@ GAS LISTING .*
[ ]*[1-9][0-9]*[ ]+\.intel_syntax noprefix
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F3FD48 vfpclasspd k0, \[eax], 0
[ ]*[1-9][0-9]*[ ]+660000
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F37D48 vfpclassps k0, \[eax], 0
[ ]*[1-9][0-9]*[ ]+660000
[ ]*[1-9][0-9]*[ ]+\?\?\?\? 62F37D48 vfpclassps k0, \[eax\+0x80], 0
[ ]*[1-9][0-9]*[ ]+66400200 ?
[ ]*[1-9][0-9]*[ ]+
#pass

2
gas/testsuite/gas/i386/noavx512-2.s
View file

@ -52,6 +52,6 @@
.intel_syntax noprefix
vfpclasspd k0, [eax], 0
vfpclassps k0, [eax], 0
vfpclassps k0, [eax+0x80], 0
.p2align 4