PRU Opcode Port
opcodes/ * Makefile.am: Add PRU source files. * configure.ac: Add PRU target. * disassemble.c (disassembler): Register PRU arch. * pru-dis.c: New file. * pru-opc.c: New file. * Makefile.in: Regenerate. * configure: Regenerate. Signed-off-by: Dimitar Dimitrov <dimitar@dinux.eu>
This commit is contained in:
Dimitar Dimitrov
Alan Modra
parent
889294f6ff
commit
1114684964
9 changed files with 548 additions and 1 deletions
286
opcodes/pru-dis.c
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286
opcodes/pru-dis.c
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/* TI PRU disassemble routines
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Copyright (C) 2014-2016 Free Software Foundation, Inc.
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Contributed by Dimitar Dimitrov <dimitar@dinux.eu>
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This file is part of the GNU opcodes library.
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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#include "sysdep.h"
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#include "dis-asm.h"
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#include "opcode/pru.h"
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#include "libiberty.h"
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#include <string.h>
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#include <assert.h>
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/* No symbol table is available when this code runs out in an embedded
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system as when it is used for disassembler support in a monitor. */
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#if !defined (EMBEDDED_ENV)
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#define SYMTAB_AVAILABLE 1
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#include "elf-bfd.h"
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#include "elf/pru.h"
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#endif
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/* Length of PRU instruction in bytes. */
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#define INSNLEN 4
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/* Return a pointer to an pru_opcode struct for a given instruction
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opcode, or NULL if there is an error. */
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const struct pru_opcode *
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pru_find_opcode (unsigned long opcode)
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{
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const struct pru_opcode *p;
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const struct pru_opcode *op = NULL;
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const struct pru_opcode *pseudo_op = NULL;
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for (p = pru_opcodes; p < &pru_opcodes[NUMOPCODES]; p++)
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{
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if ((p->mask & opcode) == p->match)
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{
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if ((p->pinfo & PRU_INSN_MACRO) == PRU_INSN_MACRO)
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pseudo_op = p;
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else if ((p->pinfo & PRU_INSN_LDI32) == PRU_INSN_LDI32)
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/* ignore - should be caught with regular patterns */;
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else
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op = p;
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}
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}
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return pseudo_op ? pseudo_op : op;
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}
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/* There are 32 regular registers, each with 8 possible subfield selectors. */
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#define NUMREGNAMES (32 * 8)
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static void
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pru_print_insn_arg_reg (unsigned int r, unsigned int sel,
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disassemble_info *info)
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{
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unsigned int i = r * RSEL_NUM_ITEMS + sel;
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assert (i < (unsigned int)pru_num_regs);
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assert (i < NUMREGNAMES);
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(*info->fprintf_func) (info->stream, "%s", pru_regs[i].name);
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}
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/* The function pru_print_insn_arg uses the character pointed
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to by ARGPTR to determine how it print the next token or separator
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character in the arguments to an instruction. */
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static int
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pru_print_insn_arg (const char *argptr,
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unsigned long opcode, bfd_vma address,
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disassemble_info *info)
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{
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long offs = 0;
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unsigned long i = 0;
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unsigned long io = 0;
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switch (*argptr)
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{
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case ',':
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(*info->fprintf_func) (info->stream, "%c ", *argptr);
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break;
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case 'd':
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pru_print_insn_arg_reg (GET_INSN_FIELD (RD, opcode),
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GET_INSN_FIELD (RDSEL, opcode),
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info);
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break;
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case 'D':
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/* The first 4 values for RDB and RSEL are the same, so we
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can reuse some code. */
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pru_print_insn_arg_reg (GET_INSN_FIELD (RD, opcode),
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GET_INSN_FIELD (RDB, opcode),
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info);
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break;
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case 's':
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS1, opcode),
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GET_INSN_FIELD (RS1SEL, opcode),
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info);
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break;
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case 'S':
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS1, opcode),
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RSEL_31_0,
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info);
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break;
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case 'b':
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io = GET_INSN_FIELD (IO, opcode);
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if (io)
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{
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i = GET_INSN_FIELD (IMM8, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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}
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else
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{
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS2, opcode),
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GET_INSN_FIELD (RS2SEL, opcode),
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info);
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}
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break;
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case 'B':
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io = GET_INSN_FIELD (IO, opcode);
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if (io)
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{
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i = GET_INSN_FIELD (IMM8, opcode) + 1;
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(*info->fprintf_func) (info->stream, "%ld", i);
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}
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else
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{
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS2, opcode),
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GET_INSN_FIELD (RS2SEL, opcode),
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info);
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}
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break;
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case 'j':
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io = GET_INSN_FIELD (IO, opcode);
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if (io)
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{
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/* For the sake of pretty-printing, dump text addresses with
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their "virtual" offset that we use for distinguishing
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PMEM vs DMEM. This is needed for printing the correct text
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labels. */
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bfd_vma text_offset = address & ~0x3fffff;
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i = GET_INSN_FIELD (IMM16, opcode) * 4;
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(*info->print_address_func) (i + text_offset, info);
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}
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else
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{
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pru_print_insn_arg_reg (GET_INSN_FIELD (RS2, opcode),
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GET_INSN_FIELD (RS2SEL, opcode),
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info);
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}
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break;
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case 'W':
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i = GET_INSN_FIELD (IMM16, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'o':
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offs = GET_BROFF_SIGNED (opcode) * 4;
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(*info->print_address_func) (address + offs, info);
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break;
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case 'O':
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offs = GET_INSN_FIELD (LOOP_JMPOFFS, opcode) * 4;
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(*info->print_address_func) (address + offs, info);
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break;
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case 'l':
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i = GET_BURSTLEN (opcode);
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if (i < LSSBBO_BYTECOUNT_R0_BITS7_0)
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(*info->fprintf_func) (info->stream, "%ld", i + 1);
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else
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{
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i -= LSSBBO_BYTECOUNT_R0_BITS7_0;
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(*info->fprintf_func) (info->stream, "r0.b%ld", i);
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}
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break;
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case 'n':
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i = GET_INSN_FIELD (XFR_LENGTH, opcode);
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if (i < LSSBBO_BYTECOUNT_R0_BITS7_0)
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(*info->fprintf_func) (info->stream, "%ld", i + 1);
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else
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{
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i -= LSSBBO_BYTECOUNT_R0_BITS7_0;
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(*info->fprintf_func) (info->stream, "r0.b%ld", i);
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}
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break;
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case 'c':
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i = GET_INSN_FIELD (CB, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'w':
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i = GET_INSN_FIELD (WAKEONSTATUS, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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case 'x':
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i = GET_INSN_FIELD (XFR_WBA, opcode);
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(*info->fprintf_func) (info->stream, "%ld", i);
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break;
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default:
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(*info->fprintf_func) (info->stream, "unknown");
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break;
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}
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return 0;
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}
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/* pru_disassemble does all the work of disassembling a PRU
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instruction opcode. */
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static int
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pru_disassemble (bfd_vma address, unsigned long opcode,
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disassemble_info *info)
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{
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const struct pru_opcode *op;
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info->bytes_per_line = INSNLEN;
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info->bytes_per_chunk = INSNLEN;
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info->display_endian = info->endian;
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info->insn_info_valid = 1;
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info->branch_delay_insns = 0;
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info->data_size = 0;
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info->insn_type = dis_nonbranch;
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info->target = 0;
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info->target2 = 0;
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/* Find the major opcode and use this to disassemble
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the instruction and its arguments. */
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op = pru_find_opcode (opcode);
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if (op != NULL)
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{
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(*info->fprintf_func) (info->stream, "%s", op->name);
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const char *argstr = op->args;
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if (argstr != NULL && *argstr != '\0')
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{
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(*info->fprintf_func) (info->stream, "\t");
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while (*argstr != '\0')
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{
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pru_print_insn_arg (argstr, opcode, address, info);
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++argstr;
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}
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}
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}
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else
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{
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/* Handle undefined instructions. */
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info->insn_type = dis_noninsn;
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(*info->fprintf_func) (info->stream, "0x%lx", opcode);
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}
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/* Tell the caller how far to advance the program counter. */
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return INSNLEN;
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}
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/* print_insn_pru is the main disassemble function for PRU. */
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int
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print_insn_pru (bfd_vma address, disassemble_info *info)
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{
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bfd_byte buffer[INSNLEN];
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int status;
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status = (*info->read_memory_func) (address, buffer, INSNLEN, info);
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if (status == 0)
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{
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unsigned long insn;
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insn = (unsigned long) bfd_getl32 (buffer);
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status = pru_disassemble (address, insn, info);
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}
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else
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{
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(*info->memory_error_func) (status, address, info);
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status = -1;
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}
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return status;
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}
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