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include/opcode/i386.h: Allow bswapl, arplw, and other dodgy insns.
opcodes/i386-dis.c: Fix a comment
This commit is contained in:
Alan Modra 1999-06-23 06:00:14 +00:00
parent 83d765b3ed
commit 1008451944
4 changed files with 53 additions and 43 deletions
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6
include/opcode/ChangeLog
View file

@ -1,3 +1,9 @@
1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl,
lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP
flag to fcomi and friends.
Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com)
* hppa.h (pa_opcodes): Move integer arithmetic instructions after

68
include/opcode/i386.h
View file

@ -477,23 +477,23 @@ static const template i386_optab[] = {
{"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} },
/* protection control */
{"arpl", 2, 0x63, X, NoSuf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
{"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
{"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
{"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} },
{"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} },
{"lldt", 1, 0x0f00, 2, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"lmsw", 1, 0x0f01, 6, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
{"ltr", 1, 0x0f00, 3, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} },
{"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} },
{"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
{"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} },
{"str", 1, 0x0f00, 1, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"verr", 1, 0x0f00, 4, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"verw", 1, 0x0f00, 5, NoSuf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
{"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
/* floating point instructions */
@ -766,7 +766,7 @@ static const template i386_optab[] = {
/* 486 extensions */
{"bswap", 1, 0x0fc8, X, NoSuf|ShortForm, { Reg32,0,0 } },
{"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32,0,0 } },
{"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
{"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } },
{"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} },
@ -822,33 +822,33 @@ static const template i386_optab[] = {
{"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
{"fcmovb", 2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnae",2, 0xdac0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmove", 2, 0xdac8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovbe", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovna", 2, 0xdad0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovu", 2, 0xdad8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovae", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnb", 2, 0xdbc0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovne", 2, 0xdbc8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmova", 2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnbe",2, 0xdbd0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnu", 2, 0xdbd8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcomi", 2, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcomi", 0, 0xdbf1, X, NoSuf|ShortForm, { 0, 0, 0} },
{"fcomi", 1, 0xdbf0, X, NoSuf|ShortForm, { FloatReg, 0, 0} },
{"fucomi", 2, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fucomi", 0, 0xdbe9, X, NoSuf|ShortForm, { 0, 0, 0} },
{"fucomi", 1, 0xdbe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} },
{"fcomip", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcompi", 2, 0xdff0, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcompi", 0, 0xdff1, X, NoSuf|ShortForm, { 0, 0, 0} },
{"fcompi", 1, 0xdff0, X, NoSuf|ShortForm, { FloatReg, 0, 0} },
{"fucomip", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fucompi", 2, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, FloatAcc, 0} },
{"fucompi", 0, 0xdfe9, X, NoSuf|ShortForm, { 0, 0, 0} },
{"fucompi", 1, 0xdfe8, X, NoSuf|ShortForm, { FloatReg, 0, 0} },
{"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} },
{"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} },
{"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} },
{"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} },
{"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} },
{"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} },
{"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} },
{"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} },
{"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} },
/* MMX instructions. */

4
opcodes/ChangeLog
View file

@ -1,3 +1,7 @@
1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au>
* i386-dis.c: Mention intel mode specials in macro char comment.
1999-06-21 Ian Lance Taylor <ian@zembu.com>
* alpha-dis.c: Don't include <stdlib.h>.

4
opcodes/i386-dis.c
View file

@ -341,9 +341,9 @@ struct dis386 {
'P' => print 'w' or 'l' if instruction has an operand size prefix,
or suffix_always is true
'Q' => print 'w' or 'l' if no register operands or suffix_always is true
'R' => print 'w' or 'l'
'R' => print 'w' or 'l' ("wd" or "dq" in intel mode)
'S' => print 'w' or 'l' if suffix_always is true
'W' => print 'b' or 'w'
'W' => print 'b' or 'w' ("w" or "de" in intel mode)
*/
static const struct dis386 dis386_att[] = {